diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-10-13 23:21:40 +0100 |
| commit | c87b717dbdf36f4b0ebef1df4592f1ebabad15a5 (patch) | |
| tree | e8dab9b58aef6394538af96fd1c7f1f2ffaf5775 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual | |
| parent | 78dd152a0d5e55e26cd6c501dbc4f73e316937d9 (diff) | |
| download | gem5-c87b717dbdf36f4b0ebef1df4592f1ebabad15a5.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual')
4 files changed, 2959 insertions, 2956 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini index 2a00a6a90..9e59e49a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/config.ini @@ -36,7 +36,7 @@ load_addr_mask=268435455 load_offset=2147483648 machine_type=VExpress_EMM64 mem_mode=timing -mem_ranges=2147483648:2415919103 +mem_ranges=2147483648:2415919103:0:0:0:0 memories=system.physmem system.realview.nvmem system.realview.vram mmap_using_noreserve=false multi_proc=true @@ -73,7 +73,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 +ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 req_size=16 resp_size=16 master=system.iobus.slave[0] @@ -153,7 +153,7 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -250,7 +250,7 @@ port=system.cpu0.toL2Bus.slave[3] [system.cpu0.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -310,7 +310,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -382,7 +382,7 @@ port=system.cpu0.toL2Bus.slave[2] [system.cpu0.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -531,7 +531,7 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -628,7 +628,7 @@ port=system.cpu1.toL2Bus.slave[3] [system.cpu1.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -688,7 +688,7 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 +id_aa64pfr0_el1=34 id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 @@ -760,7 +760,7 @@ port=system.cpu1.toL2Bus.slave[2] [system.cpu1.l2cache] type=Cache children=prefetcher tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl @@ -907,7 +907,7 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=Cache children=tags -addr_ranges=2147483648:2415919103 +addr_ranges=2147483648:2415919103:0:0:0:0 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl @@ -953,7 +953,7 @@ size=1024 [system.l2c] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1051,27 +1051,27 @@ system=system [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1091,6 +1091,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1100,7 +1101,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=2147483648:2415919103 +range=2147483648:2415919103:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1122,9 +1123,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 @@ -1477,7 +1478,7 @@ default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 -gem5_extensions=true +gem5_extensions=false int_latency=10000 it_lines=128 p_state_clk_gate_bins=20 @@ -1790,10 +1791,11 @@ pio=system.iobus.master[21] type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain -conf_table_reported=true +conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -1801,7 +1803,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:67108863 +range=0:67108863:0:0:0:0 port=system.membus.master[1] [system.realview.pci_host] @@ -2032,6 +2034,7 @@ conf_table_reported=false default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -2039,7 +2042,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=402653184:436207615 +range=402653184:436207615:0:0:0:0 port=system.iobus.master[11] [system.realview.watchdog_fake] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout index c648cad5f..7bd8ed2ad 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/simout @@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:41:50 -gem5 executing on e108600-lin, pid 23131 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:59 +gem5 executing on e108600-lin, pid 17314 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual Selected 64-bit ARM architecture, updating default disk image... @@ -15,4 +15,4 @@ info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 47403574916500 because m5_exit instruction encountered +Exiting @ tick 47405012960500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index c73396a86..68cea9e8f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.374315 # Number of seconds simulated -sim_ticks 47374315410500 # Number of ticks simulated -final_tick 47374315410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.405013 # Number of seconds simulated +sim_ticks 47405012960500 # Number of ticks simulated +final_tick 47405012960500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 573964 # Simulator instruction rate (inst/s) -host_op_rate 675116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30496109280 # Simulator tick rate (ticks/s) -host_mem_usage 762100 # Number of bytes of host memory used -host_seconds 1553.45 # Real time elapsed on the host -sim_insts 891626325 # Number of instructions simulated -sim_ops 1048762579 # Number of ops (including micro ops) simulated +host_inst_rate 480061 # Simulator instruction rate (inst/s) +host_op_rate 564722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25874318289 # Simulator tick rate (ticks/s) +host_mem_usage 758156 # Number of bytes of host memory used +host_seconds 1832.13 # Real time elapsed on the host +sim_insts 879531552 # Number of instructions simulated +sim_ops 1034641707 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 107264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 103104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3762996 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 12951880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 13484096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 112000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 117056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2426936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10199632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 12856576 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 431488 # Number of bytes read from this memory -system.physmem.bytes_read::total 56553028 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3762996 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2426936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6189932 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74832448 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 107584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 111616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3269620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13856200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 15427200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 122176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 126272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2852024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 9626320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 10834112 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 432576 # Number of bytes read from this memory +system.physmem.bytes_read::total 56765700 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3269620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2852024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6121644 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 74832256 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74853032 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1676 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1611 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 99204 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 202386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 210689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1829 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 38009 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 159382 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 200884 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6742 # Number of read requests responded to by this memory -system.physmem.num_reads::total 924162 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1169257 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 74852840 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1744 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 91495 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 216516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 241050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1973 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 44651 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 150424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 169283 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6759 # Number of read requests responded to by this memory +system.physmem.num_reads::total 927485 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1169254 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1171831 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2176 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 79431 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 273395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 284629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2364 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 51229 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 215299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 271383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1193749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 79431 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 51229 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 130660 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1579600 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1171828 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2269 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 68972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 292294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 325434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 60163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 203065 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 228544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1197462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 68972 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 60163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 129135 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1578573 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1580034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1579600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2176 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 79431 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 273829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 284629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 51229 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 215299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 271383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2773783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 924162 # Number of read requests accepted -system.physmem.writeReqs 1171831 # Number of write requests accepted -system.physmem.readBursts 924162 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1171831 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 59123712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22656 # Total number of bytes read from write queue -system.physmem.bytesWritten 74852544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56553028 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 74853032 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 354 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1579007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1578573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2269 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2355 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 68972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 292728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 325434 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 60163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 203066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 228544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2776469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 927485 # Number of read requests accepted +system.physmem.writeReqs 1171828 # Number of write requests accepted +system.physmem.readBursts 927485 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1171828 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59337472 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21568 # Total number of bytes read from write queue +system.physmem.bytesWritten 74850880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56765700 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 74852840 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 337 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54791 # Per bank write bursts -system.physmem.perBankRdBursts::1 60963 # Per bank write bursts -system.physmem.perBankRdBursts::2 51680 # Per bank write bursts -system.physmem.perBankRdBursts::3 61600 # Per bank write bursts -system.physmem.perBankRdBursts::4 56399 # Per bank write bursts -system.physmem.perBankRdBursts::5 67623 # Per bank write bursts -system.physmem.perBankRdBursts::6 62592 # Per bank write bursts -system.physmem.perBankRdBursts::7 58195 # Per bank write bursts -system.physmem.perBankRdBursts::8 51047 # Per bank write bursts -system.physmem.perBankRdBursts::9 95684 # Per bank write bursts -system.physmem.perBankRdBursts::10 47816 # Per bank write bursts -system.physmem.perBankRdBursts::11 53141 # Per bank write bursts -system.physmem.perBankRdBursts::12 48535 # Per bank write bursts -system.physmem.perBankRdBursts::13 54663 # Per bank write bursts -system.physmem.perBankRdBursts::14 49130 # Per bank write bursts -system.physmem.perBankRdBursts::15 49949 # Per bank write bursts -system.physmem.perBankWrBursts::0 71660 # Per bank write bursts -system.physmem.perBankWrBursts::1 78743 # Per bank write bursts -system.physmem.perBankWrBursts::2 71851 # Per bank write bursts -system.physmem.perBankWrBursts::3 78616 # Per bank write bursts -system.physmem.perBankWrBursts::4 73485 # Per bank write bursts -system.physmem.perBankWrBursts::5 81529 # Per bank write bursts -system.physmem.perBankWrBursts::6 75635 # Per bank write bursts -system.physmem.perBankWrBursts::7 74455 # Per bank write bursts -system.physmem.perBankWrBursts::8 70456 # Per bank write bursts -system.physmem.perBankWrBursts::9 72917 # Per bank write bursts -system.physmem.perBankWrBursts::10 67611 # Per bank write bursts -system.physmem.perBankWrBursts::11 70918 # Per bank write bursts -system.physmem.perBankWrBursts::12 67621 # Per bank write bursts -system.physmem.perBankWrBursts::13 71486 # Per bank write bursts -system.physmem.perBankWrBursts::14 70570 # Per bank write bursts -system.physmem.perBankWrBursts::15 72018 # Per bank write bursts +system.physmem.perBankRdBursts::0 53188 # Per bank write bursts +system.physmem.perBankRdBursts::1 58555 # Per bank write bursts +system.physmem.perBankRdBursts::2 49548 # Per bank write bursts +system.physmem.perBankRdBursts::3 58849 # Per bank write bursts +system.physmem.perBankRdBursts::4 61060 # Per bank write bursts +system.physmem.perBankRdBursts::5 64213 # Per bank write bursts +system.physmem.perBankRdBursts::6 58593 # Per bank write bursts +system.physmem.perBankRdBursts::7 62574 # Per bank write bursts +system.physmem.perBankRdBursts::8 53530 # Per bank write bursts +system.physmem.perBankRdBursts::9 96457 # Per bank write bursts +system.physmem.perBankRdBursts::10 50033 # Per bank write bursts +system.physmem.perBankRdBursts::11 57571 # Per bank write bursts +system.physmem.perBankRdBursts::12 47029 # Per bank write bursts +system.physmem.perBankRdBursts::13 51615 # Per bank write bursts +system.physmem.perBankRdBursts::14 49510 # Per bank write bursts +system.physmem.perBankRdBursts::15 54823 # Per bank write bursts +system.physmem.perBankWrBursts::0 69378 # Per bank write bursts +system.physmem.perBankWrBursts::1 74382 # Per bank write bursts +system.physmem.perBankWrBursts::2 69427 # Per bank write bursts +system.physmem.perBankWrBursts::3 75087 # Per bank write bursts +system.physmem.perBankWrBursts::4 76532 # Per bank write bursts +system.physmem.perBankWrBursts::5 78990 # Per bank write bursts +system.physmem.perBankWrBursts::6 75385 # Per bank write bursts +system.physmem.perBankWrBursts::7 77589 # Per bank write bursts +system.physmem.perBankWrBursts::8 70916 # Per bank write bursts +system.physmem.perBankWrBursts::9 76207 # Per bank write bursts +system.physmem.perBankWrBursts::10 70858 # Per bank write bursts +system.physmem.perBankWrBursts::11 75862 # Per bank write bursts +system.physmem.perBankWrBursts::12 66596 # Per bank write bursts +system.physmem.perBankWrBursts::13 70423 # Per bank write bursts +system.physmem.perBankWrBursts::14 68869 # Per bank write bursts +system.physmem.perBankWrBursts::15 73044 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 85 # Number of times write queue was full causing retry -system.physmem.totGap 47374312061000 # Total gap between requests +system.physmem.numWrRetry 516 # Number of times write queue was full causing retry +system.physmem.totGap 47405009605000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 25 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 880937 # Read request sizes (log2) +system.physmem.readPktSize::6 884260 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1169257 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 656925 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 77551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 28745 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22090 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 18063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2611 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1169254 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 645919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 88942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 28634 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 25074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 21962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 18312 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2962 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1110 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -189,173 +189,184 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 29578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 64054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 66659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 68456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 71033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 71567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 75072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 77359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 72847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 72784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 77929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 71715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 64345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2561 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1786 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 524 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 453 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 259 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 927168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 144.500035 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.409552 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 191.008164 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 615708 66.41% 66.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 189300 20.42% 86.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44500 4.80% 91.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20695 2.23% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 14869 1.60% 95.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9173 0.99% 96.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6380 0.69% 97.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5518 0.60% 97.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 21025 2.27% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 927168 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60983 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.148533 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 130.608088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60979 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 28620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 36458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 48218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 60726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 63711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 65994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 67665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 70176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 73600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 75174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 72029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 70698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 71278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 75021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 68576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 668 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 1236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1170 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 929017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 144.440810 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.331936 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 191.352121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 617371 66.45% 66.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 189527 20.40% 86.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44674 4.81% 91.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20356 2.19% 93.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 14838 1.60% 95.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 9142 0.98% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6196 0.67% 97.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5371 0.58% 97.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 21542 2.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 929017 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60832 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.240992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 130.606668 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60830 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60983 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60983 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.178640 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.436589 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.785486 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 49393 80.99% 80.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 4571 7.50% 88.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2800 4.59% 93.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1776 2.91% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1006 1.65% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 308 0.51% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 149 0.24% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 125 0.20% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 64 0.10% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 38 0.06% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.05% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 41 0.07% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 435 0.71% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 54 0.09% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 52 0.09% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 40 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 33 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 60832 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.225819 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.418138 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.471341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 49295 81.03% 81.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 4521 7.43% 88.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 2878 4.73% 93.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1749 2.88% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 1023 1.68% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 226 0.37% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 91 0.15% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 113 0.19% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 47 0.08% 98.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 23 0.04% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.02% 98.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 42 0.07% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 494 0.81% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 82 0.13% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 51 0.08% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 57 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 26 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.00% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 4 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 21 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 13 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 2 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-243 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60983 # Writes before turning the bus around for reads -system.physmem.totQLat 30413749694 # Total ticks spent queuing -system.physmem.totMemAccLat 47735149694 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4619040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32922.15 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 60832 # Writes before turning the bus around for reads +system.physmem.totQLat 46218732203 # Total ticks spent queuing +system.physmem.totMemAccLat 63602757203 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4635740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 49850.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51672.15 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 68600.44 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.25 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.58 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.58 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing -system.physmem.readRowHits 683627 # Number of row buffer hits during reads -system.physmem.writeRowHits 482581 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.00 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 41.26 # Row buffer hit rate for writes -system.physmem.avgGap 22602323.61 # Average gap between requests -system.physmem.pageHitRate 55.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3700302480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2019014250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3695975400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3926705040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1192499073090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27378533808750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31678634457810 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.688048 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45546210437205 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581932300000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 246167130795 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3308936400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1805471250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3509181000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3651784560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3094259578800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1178425765395 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27390878815500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31675839532905 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.629051 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45566794873385 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581932300000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 225582219115 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 685692 # Number of row buffer hits during reads +system.physmem.writeRowHits 481982 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 41.21 # Row buffer hit rate for writes +system.physmem.avgGap 22581201.38 # Average gap between requests +system.physmem.pageHitRate 55.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3446827860 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1832028660 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3331381200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3115139400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 41510941680.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 46501533090 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2234866560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 80625696300 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 57761558880 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 11279719224960 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 11520096687780 # Total energy per rank (pJ) +system.physmem_0.averagePower 243.014314 # Core power per rank (mW) +system.physmem_0.totalIdleTime 47297174723637 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3911587994 # Time in different power states +system.physmem_0.memoryStateTime::REF 17636282000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 46969945639000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 150420602883 # Time in different power states +system.physmem_0.memoryStateTime::ACT 86288423369 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 176810425254 # Time in different power states +system.physmem_1.actEnergy 3186367800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1693590855 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3288455520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 2989885500 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 39461117280.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47361781080 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2153404320 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 72224847060 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 55366694400 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 11285008491285 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 11512750460370 # Total energy per rank (pJ) +system.physmem_1.averagePower 242.859346 # Core power per rank (mW) +system.physmem_1.totalIdleTime 47295506898407 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3731843770 # Time in different power states +system.physmem_1.memoryStateTime::REF 16766470000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 46992934432500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 144184093324 # Time in different power states +system.physmem_1.memoryStateTime::ACT 89007700573 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 158388420333 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -382,17 +393,17 @@ system.realview.nvmem.bw_total::cpu0.data 1 # T system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1674 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -422,73 +433,71 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 101108 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 101108 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9051 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76906 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 101094 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 101094 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 101094 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 85971 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 24170.842493 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22339.898543 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14600.032387 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 76182 88.61% 88.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 8727 10.15% 98.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 200 0.23% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 718 0.84% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 29 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 34 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 12 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 19 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 11 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 85971 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -250064880 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.334382 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.471774 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -166447796 66.56% 66.56% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -83617084 33.44% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -250064880 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 76906 89.47% 89.47% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9051 10.53% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 85957 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101108 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 110745 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 110745 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10295 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84545 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 110723 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.234820 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 78.136585 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 110722 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 110723 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 94862 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23879.314162 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22054.085361 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16759.177694 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 93763 98.84% 98.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 840 0.89% 99.73% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 113 0.12% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 52 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 94862 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples -2682325288 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 2.121047 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 3007013124 -112.10% -112.10% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 -5689338412 212.10% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total -2682325288 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 84546 89.14% 89.14% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10295 10.86% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 94841 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 110745 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101108 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85957 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 110745 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94841 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85957 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 187065 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 205586 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 84046306 # DTB read hits -system.cpu0.dtb.read_misses 73432 # DTB read misses -system.cpu0.dtb.write_hits 77237834 # DTB write hits -system.cpu0.dtb.write_misses 27676 # DTB write misses +system.cpu0.dtb.read_hits 86849149 # DTB read hits +system.cpu0.dtb.read_misses 83538 # DTB read misses +system.cpu0.dtb.write_hits 78785461 # DTB write hits +system.cpu0.dtb.write_misses 27207 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 35922 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 37555 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4635 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4746 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9711 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84119738 # DTB read accesses -system.cpu0.dtb.write_accesses 77265510 # DTB write accesses +system.cpu0.dtb.perms_faults 9443 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 86932687 # DTB read accesses +system.cpu0.dtb.write_accesses 78812668 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 161284140 # DTB hits -system.cpu0.dtb.misses 101108 # DTB misses -system.cpu0.dtb.accesses 161385248 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 165634610 # DTB hits +system.cpu0.dtb.misses 110745 # DTB misses +system.cpu0.dtb.accesses 165745355 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,763 +527,759 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 58460 # Table walker walks requested -system.cpu0.itb.walker.walksLong 58460 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 540 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52669 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 58460 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 58460 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 58460 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 53209 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 26190.982728 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24044.890366 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17871.734437 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 47169 88.65% 88.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 4943 9.29% 97.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 65 0.12% 98.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 859 1.61% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.07% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.03% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 25 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 20 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 53209 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -282313796 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -282313796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 52669 98.99% 98.99% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 540 1.01% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 53209 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 57780 # Table walker walks requested +system.cpu0.itb.walker.walksLong 57780 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 572 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51544 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 57780 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 57780 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 57780 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 52116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 25803.102694 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23425.328726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 22386.426518 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 51056 97.97% 97.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 692 1.33% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 219 0.42% 99.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 60 0.12% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::589824-655359 14 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::655360-720895 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 52116 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 14842204 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 14842204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 14842204 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 51544 98.90% 98.90% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 572 1.10% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 52116 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 58460 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 58460 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57780 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57780 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53209 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53209 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 111669 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 449335815 # ITB inst hits -system.cpu0.itb.inst_misses 58460 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52116 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52116 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 109896 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 463942995 # ITB inst hits +system.cpu0.itb.inst_misses 57780 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 24946 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26477 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 449394275 # ITB inst accesses -system.cpu0.itb.hits 449335815 # DTB hits -system.cpu0.itb.misses 58460 # DTB misses -system.cpu0.itb.accesses 449394275 # DTB accesses -system.cpu0.numPwrStateTransitions 8624 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 4312 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 10857440365.954313 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 156382311444.961365 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3059 70.94% 70.94% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 1229 28.50% 99.44% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.05% 99.49% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.05% 99.54% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 2 0.05% 99.58% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+11-5.5e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.63% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.65% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.02% 99.68% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 14 0.32% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 464000775 # ITB inst accesses +system.cpu0.itb.hits 463942995 # DTB hits +system.cpu0.itb.misses 57780 # DTB misses +system.cpu0.itb.accesses 464000775 # DTB accesses +system.cpu0.numPwrStateTransitions 8984 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 4492 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 10426010818.709705 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 169261679723.888153 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3260 72.57% 72.57% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 1205 26.83% 99.40% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 8 0.18% 99.58% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.64% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 12 0.27% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7470353528320 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 4312 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 557032552505 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 46817282857995 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 94748630821 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7033293863000 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 4492 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 571372362856 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 46833640597644 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 94810025915 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4312 # number of quiesce instructions executed -system.cpu0.committedInsts 449083110 # Number of instructions committed -system.cpu0.committedOps 528384419 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 485390643 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 507449 # Number of float alu accesses -system.cpu0.num_func_calls 26866500 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68160489 # number of instructions that are conditional controls -system.cpu0.num_int_insts 485390643 # number of integer instructions -system.cpu0.num_fp_insts 507449 # number of float instructions -system.cpu0.num_int_register_reads 703891240 # number of times the integer registers were read -system.cpu0.num_int_register_writes 384865941 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 816779 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 435492 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117650799 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117386896 # number of times the CC registers were written -system.cpu0.num_mem_refs 161276211 # number of memory refs -system.cpu0.num_load_insts 84042257 # Number of load instructions -system.cpu0.num_store_insts 77233954 # Number of store instructions -system.cpu0.num_idle_cycles 93634565715.988022 # Number of idle cycles -system.cpu0.num_busy_cycles 1114065105.011976 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011758 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988242 # Percentage of idle cycles -system.cpu0.Branches 100200450 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 366086093 69.25% 69.25% # Class of executed instruction -system.cpu0.op_class::IntMult 1185979 0.22% 69.47% # Class of executed instruction -system.cpu0.op_class::IntDiv 59083 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 72839 0.01% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::MemRead 84042257 15.90% 85.39% # Class of executed instruction -system.cpu0.op_class::MemWrite 77233954 14.61% 100.00% # Class of executed instruction +system.cpu0.kern.inst.quiesce 4492 # number of quiesce instructions executed +system.cpu0.committedInsts 463690677 # Number of instructions committed +system.cpu0.committedOps 544305781 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 499985272 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 430429 # Number of float alu accesses +system.cpu0.num_func_calls 27825312 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 70353837 # number of instructions that are conditional controls +system.cpu0.num_int_insts 499985272 # number of integer instructions +system.cpu0.num_fp_insts 430429 # number of float instructions +system.cpu0.num_int_register_reads 725660016 # number of times the integer registers were read +system.cpu0.num_int_register_writes 396645033 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 713342 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 322808 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 121489824 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 121106505 # number of times the CC registers were written +system.cpu0.num_mem_refs 165624912 # number of memory refs +system.cpu0.num_load_insts 86844124 # Number of load instructions +system.cpu0.num_store_insts 78780788 # Number of store instructions +system.cpu0.num_idle_cycles 93667281189.358337 # Number of idle cycles +system.cpu0.num_busy_cycles 1142744725.641658 # Number of busy cycles +system.cpu0.not_idle_fraction 0.012053 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.987947 # Percentage of idle cycles +system.cpu0.Branches 103560532 # Number of branches fetched +system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 377679680 69.35% 69.35% # Class of executed instruction +system.cpu0.op_class::IntMult 1190205 0.22% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 61578 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 44848 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 86844124 15.95% 85.53% # Class of executed instruction +system.cpu0.op_class::MemWrite 78780788 14.47% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 528680248 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 5566798 # number of replacements -system.cpu0.dcache.tags.tagsinuse 502.671926 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 155470196 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5567308 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.925560 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4031081000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.671926 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981781 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.981781 # Average percentage of cache occupancy +system.cpu0.op_class::total 544601223 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 5731745 # number of replacements +system.cpu0.dcache.tags.tagsinuse 479.859189 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 159669170 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5732255 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.854513 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4328406000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.859189 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937225 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.937225 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 452 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 328131694 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 328131694 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78275725 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78275725 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72837974 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72837974 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200143 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 200143 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 232092 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 232092 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1764306 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1764306 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1721538 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1721538 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 151345791 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 151345791 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 151545934 # number of overall hits -system.cpu0.dcache.overall_hits::total 151545934 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2974115 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 2974115 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1412109 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1412109 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649854 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 649854 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 801670 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 801670 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 161158 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 161158 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202775 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 202775 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 5187894 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 5187894 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5837748 # number of overall misses -system.cpu0.dcache.overall_misses::total 5837748 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44497648000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 44497648000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 28844482000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 28844482000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 25694293000 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 25694293000 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2462602000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2462602000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4821620000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4821620000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2416000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2416000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 99036423000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 99036423000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 99036423000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 99036423000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 81249840 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 81249840 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74250083 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74250083 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 849997 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 849997 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1033762 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1033762 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1925464 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1925464 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1924313 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1924313 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 156533685 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 156533685 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 157383682 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 157383682 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036605 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036605 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019018 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019018 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764537 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.764537 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.775488 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.775488 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.083698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.083698 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.105375 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.105375 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033142 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033142 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037092 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037092 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14961.643380 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14961.643380 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20426.526564 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20426.526564 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 32050.959871 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 32050.959871 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15280.668661 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15280.668661 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23778.177783 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23778.177783 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 337018109 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 337018109 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 80850678 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80850678 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 74290365 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 74290365 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 206988 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 206988 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 237888 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 237888 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1848102 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1848102 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1813975 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1813975 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 155378931 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 155378931 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 155585919 # number of overall hits +system.cpu0.dcache.overall_hits::total 155585919 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3109712 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3109712 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1421405 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1421405 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 649654 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 649654 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796576 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 796576 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 167654 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 167654 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200528 # 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number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 5566798 # number of writebacks -system.cpu0.dcache.writebacks::total 5566798 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 29633 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 29633 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21518 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21518 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 45711 # 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number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24892623000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24892623000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1575244000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1575244000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4618898000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4618898000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2363000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2363000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 91924261000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 91924261000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 106881965500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 106881965500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3989550000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3989550000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3989550000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3989550000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036240 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036240 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018728 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018728 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762553 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.762553 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.775488 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.775488 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.105375 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.105375 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032816 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032816 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036757 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.036757 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13613.618456 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13613.618456 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19377.792248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19377.792248 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23076.894416 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23076.894416 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31050.959871 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31050.959871 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13644.737412 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13644.737412 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22778.439157 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22778.439157 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 5731745 # number of writebacks +system.cpu0.dcache.writebacks::total 5731745 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26385 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 26385 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21245 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21245 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44162 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44162 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 47630 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 47630 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 47630 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 47630 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3083327 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3083327 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1400160 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1400160 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 648080 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 648080 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 796576 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 796576 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123492 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123492 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200528 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 200528 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5280063 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5280063 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5928143 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5928143 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16381 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16381 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17694 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17694 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34075 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34075 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44323294000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44323294000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28148510000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28148510000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14944693500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14944693500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 24904149500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24904149500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1681387500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1681387500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4558410500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4558410500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2192000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2192000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 97375953500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 97375953500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 112320647000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 112320647000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3040589500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3040589500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3040589500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3040589500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036724 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036724 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018493 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018493 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756535 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756535 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.770037 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.770037 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.099542 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.099542 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032855 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.032855 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036692 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.036692 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14375.151906 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14375.151906 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20103.780996 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20103.780996 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23059.951703 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23059.951703 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 31263.996781 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 31263.996781 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13615.355651 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13615.355651 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22732.039915 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22732.039915 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17895.437050 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17895.437050 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18475.991333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18475.991333 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189752.675386 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189752.675386 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91897.588280 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91897.588280 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 5174135 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.907744 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 444161163 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5174647 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.834099 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30089682000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.907744 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999820 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999820 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18442.195387 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18442.195387 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18947.020509 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18947.020509 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185616.842684 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185616.842684 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89232.267058 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89232.267058 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 4959559 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.903947 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 458982923 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4960071 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 92.535555 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 30768955000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.903947 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999812 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999812 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 421 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 903846282 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 903846282 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 444161163 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 444161163 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 444161163 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 444161163 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 444161163 # number of overall hits -system.cpu0.icache.overall_hits::total 444161163 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5174652 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5174652 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5174652 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5174652 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5174652 # number of overall misses -system.cpu0.icache.overall_misses::total 5174652 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 55704586500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 55704586500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 55704586500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 55704586500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 55704586500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 55704586500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 449335815 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 449335815 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 449335815 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 449335815 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 449335815 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 449335815 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011516 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011516 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011516 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011516 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011516 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011516 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10764.895205 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10764.895205 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10764.895205 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10764.895205 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10764.895205 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 932846061 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 932846061 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 458982923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 458982923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 458982923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 458982923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 458982923 # number of overall hits +system.cpu0.icache.overall_hits::total 458982923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4960072 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4960072 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4960072 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4960072 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4960072 # number of overall misses +system.cpu0.icache.overall_misses::total 4960072 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 54306348500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 54306348500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 54306348500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 54306348500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 54306348500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 54306348500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 463942995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 463942995 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 463942995 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 463942995 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 463942995 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 463942995 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010691 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010691 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010691 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010691 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010691 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010691 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10948.701652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10948.701652 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10948.701652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10948.701652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10948.701652 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 5174135 # number of writebacks -system.cpu0.icache.writebacks::total 5174135 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5174652 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5174652 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5174652 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5174652 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5174652 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5174652 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 4959559 # number of writebacks +system.cpu0.icache.writebacks::total 4959559 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4960072 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4960072 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4960072 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4960072 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4960072 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4960072 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 53117260500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 53117260500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 53117260500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 53117260500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 53117260500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 53117260500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3819470000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3819470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3819470000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011516 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011516 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011516 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011516 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10264.895205 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10264.895205 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10264.895205 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88567.420290 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88567.420290 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88567.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7568346 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7568354 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 51826313000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 51826313000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 51826313000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 51826313000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 51826313000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 51826313000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4116534000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4116534000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4116534000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010691 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010691 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010691 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10448.701753 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10448.701753 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10448.701753 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95455.860870 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95455.860870 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95455.860870 # average overall mshr uncacheable latency +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7732053 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7732077 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 981182 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 2342884 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15723.839714 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 9135802 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2358598 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 3.873404 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5100393500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 15407.459260 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 38.158261 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 27.135006 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 251.087187 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.940397 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002329 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001656 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.015325 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.959707 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 345 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15297 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 130 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 167 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 29 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 1019171 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 2286879 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15893.622807 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9162734 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2302009 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 3.980321 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5406430500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 15603.896064 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 29.949034 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 16.856945 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 242.920764 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.952386 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001828 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001029 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.014827 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.970070 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 306 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14757 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 139 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 67 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 53 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1333 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5696 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7896 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.021057 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.933655 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 370311903 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 370311903 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 225709 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 148168 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 373877 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 3696575 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 3696575 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 7043197 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 7043197 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 878685 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 878685 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 4695575 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 4695575 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2752703 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 2752703 # number of ReadSharedReq hits -system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216682 # number of InvalidateReq hits -system.cpu0.l2cache.InvalidateReq_hits::total 216682 # number of InvalidateReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 225709 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 148168 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4695575 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3631388 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8700840 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 225709 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 148168 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4695575 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3631388 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8700840 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 18676 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10607 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 29283 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 251664 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 251664 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202763 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 202763 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 12 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 12 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278535 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 278535 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 479077 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 479077 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 955394 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 955394 # number of ReadSharedReq misses -system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 582714 # number of InvalidateReq misses -system.cpu0.l2cache.InvalidateReq_misses::total 582714 # number of InvalidateReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 18676 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10607 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 479077 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1233929 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1742289 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 18676 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10607 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 479077 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1233929 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1742289 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 564732000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 371950000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 936682000 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 916815500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 916815500 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 321936500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 321936500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2282499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2282499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12626438998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 12626438998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 17151939500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 17151939500 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 33121351500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 33121351500 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 399249500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.InvalidateReq_miss_latency::total 399249500 # number of InvalidateReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 564732000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 371950000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 17151939500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 45747790498 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 63836411998 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 564732000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 371950000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 17151939500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 45747790498 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 63836411998 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 244385 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 158775 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 403160 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3696575 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 3696575 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 7043197 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 7043197 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 251664 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 251664 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202763 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 202763 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 12 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 12 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1157220 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1157220 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5174652 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 5174652 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3708097 # 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number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6702281000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.062868 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1283,123 +1288,124 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.236016 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.236016 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092581 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257538 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257538 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728943 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728943 # mshr miss rate for InvalidateReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.166278 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.076420 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066805 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092581 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252419 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.204964 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.204964 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092084 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.242633 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242633 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.726644 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.726644 # mshr miss rate for InvalidateReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.159374 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.065709 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057923 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092084 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233795 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.235841 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25987.228085 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 43310.223511 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18525.289672 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18525.289672 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15274.090934 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15274.090934 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 163708.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 163708.250000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38278.277545 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38278.277545 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29802.051653 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28643.524399 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28643.524399 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32147.228314 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32147.228314 # average InvalidateReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30433.782810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 24238.380810 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 29066.465542 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29802.051653 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30786.242975 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 43310.223511 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34231.791627 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181726.848989 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114058.293063 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81067.420290 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 88010.665008 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 84550.596270 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 22270826 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11431607 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1159 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 634641 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 634635 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 532548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9516927 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 22389 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 22388 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 5262772 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 7044356 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 1133181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 892107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 438346 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 371201 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 524392 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1190804 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1167926 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5174652 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4606140 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 845268 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateResp 799396 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 15609689 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18074319 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 333482 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 538074 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 34555564 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 662494868 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 674962485 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1270200 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1955080 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1340682633 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5171785 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 107950516 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 16772894 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.051983 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.221994 # Request fanout histogram +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231324 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28364.489475 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49385.735208 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18573.965548 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18573.965548 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15227.675321 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15227.675321 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178549.700000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178549.700000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 48088.156473 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 48088.156473 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31960.284185 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 32588.368843 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32588.368843 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 32541.105310 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 32541.105310 # average InvalidateReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34607.596091 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25373.768091 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34271.746385 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31960.284185 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35776.277762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49385.735208 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39204.122111 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177595.049142 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112632.020300 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87955.860870 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85375.920763 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86817.111399 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 22159208 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 11368269 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1008 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 619514 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 619512 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 553426 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 9465318 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 17695 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 17694 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 5316723 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 6896635 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1098455 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 916448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 433150 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 369627 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 506111 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1214944 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1192020 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4960072 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4756139 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 842201 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateResp 794505 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 14965952 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18512478 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 327835 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 591529 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 34397794 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 635028820 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 696134983 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1241656 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2161912 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1334567371 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5130075 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 104832276 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 16684270 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.051566 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.221149 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 15900995 94.80% 94.80% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 871893 5.20% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 15823936 94.84% 94.84% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 860332 5.16% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 2 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 16772894 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 22046960997 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 16684270 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 21945410994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 203834159 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 195855793 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7805103000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 7483231500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7957435977 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8196031021 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 174707000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 172628000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 293689000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 321290000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1429,75 +1435,71 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 113512 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 113512 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10824 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86665 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 27 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 113485 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.290787 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 77.918264 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 113483 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 113485 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 97516 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23769.576275 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22071.904189 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14608.572728 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 88342 90.59% 90.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 8042 8.25% 98.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 147 0.15% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 810 0.83% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 21 0.02% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 18 0.02% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 45 0.05% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 17 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 36 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 97516 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 14762172 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 194.841712 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -2861524688 -19384.17% -19384.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 2876286860 19484.17% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 14762172 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 86666 88.90% 88.90% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 10824 11.10% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 97490 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 113512 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 99152 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 99152 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8586 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 75770 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 99148 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.080687 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 25.406685 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 99147 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 99148 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 84360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 24513.021574 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22367.425597 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 18734.439703 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 83116 98.53% 98.53% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 940 1.11% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 161 0.19% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 58 0.07% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 36 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 23 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 84360 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 407519048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 2.490877 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -607560648 -149.09% -149.09% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1015079696 249.09% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 407519048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 75770 89.82% 89.82% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8586 10.18% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 84356 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99152 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 113512 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97490 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99152 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84356 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97490 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 211002 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84356 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 183508 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83873503 # DTB read hits -system.cpu1.dtb.read_misses 85876 # DTB read misses -system.cpu1.dtb.write_hits 75393075 # DTB write hits -system.cpu1.dtb.write_misses 27636 # DTB write misses +system.cpu1.dtb.read_hits 78885011 # DTB read hits +system.cpu1.dtb.read_misses 72039 # DTB read misses +system.cpu1.dtb.write_hits 71761800 # DTB write hits +system.cpu1.dtb.write_misses 27113 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 39012 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 36637 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3907 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3802 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10199 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83959379 # DTB read accesses -system.cpu1.dtb.write_accesses 75420711 # DTB write accesses +system.cpu1.dtb.perms_faults 10123 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78957050 # DTB read accesses +system.cpu1.dtb.write_accesses 71788913 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159266578 # DTB hits -system.cpu1.dtb.misses 113512 # DTB misses -system.cpu1.dtb.accesses 159380090 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 150646811 # DTB hits +system.cpu1.dtb.misses 99152 # DTB misses +system.cpu1.dtb.accesses 150745963 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1527,759 +1529,759 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 59776 # Table walker walks requested -system.cpu1.itb.walker.walksLong 59776 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 674 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 53293 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 59776 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 59776 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 59776 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 53967 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25622.306224 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 23504.254601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18586.945639 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 52820 97.87% 97.87% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 977 1.81% 99.68% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 34 0.06% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 58 0.11% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 61 0.11% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 53967 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1314622148 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1314622148 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1314622148 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 53293 98.75% 98.75% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 674 1.25% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 53967 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 58316 # Table walker walks requested +system.cpu1.itb.walker.walksLong 58316 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52495 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 58316 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 58316 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 58316 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 53121 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27183.693831 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24219.790403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 26514.333195 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 51734 97.39% 97.39% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 949 1.79% 99.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 242 0.46% 99.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 79 0.15% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.02% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 33 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::655360-720895 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 53121 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -615394148 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -615394148 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -615394148 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 52495 98.82% 98.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 626 1.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 53121 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59776 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59776 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 58316 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 58316 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53967 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53967 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 113743 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 442849873 # ITB inst hits -system.cpu1.itb.inst_misses 59776 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53121 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53121 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 111437 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 416140593 # ITB inst hits +system.cpu1.itb.inst_misses 58316 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41711 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 27503 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41059 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 25699 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 442909649 # ITB inst accesses -system.cpu1.itb.hits 442849873 # DTB hits -system.cpu1.itb.misses 59776 # DTB misses -system.cpu1.itb.accesses 442909649 # DTB accesses -system.cpu1.numPwrStateTransitions 28574 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 14287 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3279405691.982362 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 123453533761.994095 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 4140 28.98% 28.98% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 10126 70.88% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 7 0.05% 99.90% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.91% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.92% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.93% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.07% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 416198909 # ITB inst accesses +system.cpu1.itb.hits 416140593 # DTB hits +system.cpu1.itb.misses 58316 # DTB misses +system.cpu1.itb.accesses 416198909 # DTB accesses +system.cpu1.numPwrStateTransitions 28692 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 14346 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 3269284130.341071 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 86001867955.202789 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3953 27.55% 27.55% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 10364 72.24% 99.80% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11813601970000 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 14287 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 521446289148 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 46852869121352 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 94748630821 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 7510077904252 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 14346 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 503862826627 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 46901150133873 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 94810025921 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 14287 # number of quiesce instructions executed -system.cpu1.committedInsts 442543215 # Number of instructions committed -system.cpu1.committedOps 520378160 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 478315040 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 404780 # Number of float alu accesses -system.cpu1.num_func_calls 26483096 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 67217461 # number of instructions that are conditional controls -system.cpu1.num_int_insts 478315040 # number of integer instructions -system.cpu1.num_fp_insts 404780 # number of float instructions -system.cpu1.num_int_register_reads 696723237 # number of times the integer registers were read -system.cpu1.num_int_register_writes 379679857 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 664337 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 317564 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 114632172 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 114267384 # number of times the CC registers were written -system.cpu1.num_mem_refs 159256484 # number of memory refs -system.cpu1.num_load_insts 83870110 # Number of load instructions -system.cpu1.num_store_insts 75386374 # Number of store instructions -system.cpu1.num_idle_cycles 93705738242.702026 # Number of idle cycles -system.cpu1.num_busy_cycles 1042892578.297978 # Number of busy cycles -system.cpu1.not_idle_fraction 0.011007 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.988993 # Percentage of idle cycles -system.cpu1.Branches 98643380 # Number of branches fetched -system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 360264761 69.19% 69.19% # Class of executed instruction -system.cpu1.op_class::IntMult 1062033 0.20% 69.39% # Class of executed instruction -system.cpu1.op_class::IntDiv 60918 0.01% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 40731 0.01% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 83870110 16.11% 85.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 75386374 14.48% 100.00% # Class of executed instruction +system.cpu1.kern.inst.quiesce 14346 # number of quiesce instructions executed +system.cpu1.committedInsts 415840875 # Number of instructions committed +system.cpu1.committedOps 490335926 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 450775425 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 467875 # Number of float alu accesses +system.cpu1.num_func_calls 24835210 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 63203882 # number of instructions that are conditional controls +system.cpu1.num_int_insts 450775425 # number of integer instructions +system.cpu1.num_fp_insts 467875 # number of float instructions +system.cpu1.num_int_register_reads 655878523 # number of times the integer registers were read +system.cpu1.num_int_register_writes 357644258 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 746575 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 415812 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 107608929 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 107374492 # number of times the CC registers were written +system.cpu1.num_mem_refs 150638767 # number of memory refs +system.cpu1.num_load_insts 78882725 # Number of load instructions +system.cpu1.num_store_insts 71756042 # Number of store instructions +system.cpu1.num_idle_cycles 93802300267.744019 # Number of idle cycles +system.cpu1.num_busy_cycles 1007725653.255979 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010629 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989371 # Percentage of idle cycles +system.cpu1.Branches 92635099 # Number of branches fetched +system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 338840052 69.06% 69.06% # Class of executed instruction +system.cpu1.op_class::IntMult 1031473 0.21% 69.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 58381 0.01% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 67037 0.01% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction +system.cpu1.op_class::MemRead 78882725 16.08% 85.37% # Class of executed instruction +system.cpu1.op_class::MemWrite 71756042 14.63% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 520684927 # Class of executed instruction -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 5203972 # number of replacements -system.cpu1.dcache.tags.tagsinuse 424.411021 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 153866536 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5204484 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 29.564225 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8378899013000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 424.411021 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.828928 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.828928 # Average percentage of cache occupancy +system.cpu1.op_class::total 490635753 # Class of executed instruction +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 4949273 # number of replacements +system.cpu1.dcache.tags.tagsinuse 456.328608 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 145491110 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4949785 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.393420 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379669141000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.328608 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891267 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.891267 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323742508 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323742508 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 78110378 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78110378 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71558729 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71558729 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177304 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 177304 # number of SoftPFReq hits -system.cpu1.dcache.WriteLineReq_hits::cpu1.data 95899 # number of WriteLineReq hits -system.cpu1.dcache.WriteLineReq_hits::total 95899 # number of WriteLineReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1773602 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1773602 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1738086 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1738086 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 149765006 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 149765006 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 149942310 # number of overall hits -system.cpu1.dcache.overall_hits::total 149942310 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2993339 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2993339 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1322577 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1322577 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630415 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 630415 # number of SoftPFReq misses -system.cpu1.dcache.WriteLineReq_misses::cpu1.data 446111 # number of WriteLineReq misses -system.cpu1.dcache.WriteLineReq_misses::total 446111 # number of WriteLineReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170906 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 170906 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 205163 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 205163 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4762027 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4762027 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5392442 # number of overall misses -system.cpu1.dcache.overall_misses::total 5392442 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43487315000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 43487315000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 24009342500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 24009342500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10785817000 # number of WriteLineReq miss cycles -system.cpu1.dcache.WriteLineReq_miss_latency::total 10785817000 # number of WriteLineReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2544188500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2544188500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4864957000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4864957000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2180500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2180500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 78282474500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 78282474500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 78282474500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 78282474500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81103717 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81103717 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 72881306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 72881306 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 807719 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 807719 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 542010 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.WriteLineReq_accesses::total 542010 # number of WriteLineReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1944508 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1944508 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1943249 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1943249 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154527033 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154527033 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 155334752 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 155334752 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036908 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036908 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018147 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018147 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780488 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780488 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.823068 # miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_miss_rate::total 0.823068 # miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.087892 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.087892 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105577 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105577 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.030817 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.030817 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034715 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.034715 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14528.028733 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14528.028733 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18153.455338 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18153.455338 # average WriteReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24177.428936 # average WriteLineReq miss latency -system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24177.428936 # average WriteLineReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14886.478532 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14886.478532 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23712.643118 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23712.643118 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 306227498 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 306227498 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 73475131 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73475131 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 68103188 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 68103188 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 168046 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 168046 # number of SoftPFReq hits +system.cpu1.dcache.WriteLineReq_hits::cpu1.data 87192 # number of WriteLineReq hits +system.cpu1.dcache.WriteLineReq_hits::total 87192 # number of WriteLineReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1644934 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1644934 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1602204 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1602204 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 141665511 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 141665511 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141833557 # number of overall hits +system.cpu1.dcache.overall_hits::total 141833557 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2804863 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2804863 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1292961 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1292961 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609189 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 609189 # number of SoftPFReq misses +system.cpu1.dcache.WriteLineReq_misses::cpu1.data 443031 # number of WriteLineReq misses +system.cpu1.dcache.WriteLineReq_misses::total 443031 # number of WriteLineReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 160663 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 160663 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202242 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 202242 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4540855 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4540855 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5150044 # number of overall misses +system.cpu1.dcache.overall_misses::total 5150044 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 42649111500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 42649111500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 25017964000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 25017964000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10518897000 # number of WriteLineReq miss cycles +system.cpu1.dcache.WriteLineReq_miss_latency::total 10518897000 # number of WriteLineReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2505987000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2505987000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4791659000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4791659000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2159000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2159000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 78185972500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 78185972500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 78185972500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 78185972500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 76279994 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 76279994 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69396149 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69396149 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 777235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 777235 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 530223 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.WriteLineReq_accesses::total 530223 # number of WriteLineReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1805597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1805597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1804446 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1804446 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 146206366 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 146206366 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 146983601 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 146983601 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036771 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036771 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018632 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018632 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.783790 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.783790 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.835556 # miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_miss_rate::total 0.835556 # miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.088981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.088981 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112080 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112080 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031058 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031058 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035038 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035038 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.416985 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.416985 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19349.357019 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19349.357019 # average WriteReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23743.027012 # average WriteLineReq miss latency +system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23743.027012 # average WriteLineReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15597.785427 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15597.785427 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23692.699835 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23692.699835 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16438.897658 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16438.897658 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14517.073063 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14517.073063 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17218.337185 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17218.337185 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15181.612526 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15181.612526 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 5203972 # number of writebacks -system.cpu1.dcache.writebacks::total 5203972 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 14156 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 14156 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 216 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44175 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44175 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 14372 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 14372 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 14372 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 14372 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2979183 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2979183 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1322361 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1322361 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630415 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 630415 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 446111 # number of WriteLineReq MSHR misses -system.cpu1.dcache.WriteLineReq_mshr_misses::total 446111 # number of WriteLineReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 126731 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 126731 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 205163 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 205163 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4747655 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4747655 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5378070 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5378070 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17577 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17577 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16125 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16125 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 33702 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 33702 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39805955500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39805955500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22681350000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22681350000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12330973000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12330973000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10339706000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10339706000 # number of WriteLineReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1686365000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1686365000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4659843000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4659843000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2131500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2131500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72827011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 72827011500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85157984500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 85157984500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2978895500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2978895500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2978895500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2978895500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036733 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036733 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018144 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018144 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780488 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780488 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.823068 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.823068 # mshr miss rate for WriteLineReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065174 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105577 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105577 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030724 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030724 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034622 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.034622 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13361.366354 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13361.366354 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17152.161929 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17152.161929 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19560.088196 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19560.088196 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23177.428936 # average WriteLineReq mshr miss latency -system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23177.428936 # average WriteLineReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13306.649517 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13306.649517 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22712.881952 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22712.881952 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 4949273 # number of writebacks +system.cpu1.dcache.writebacks::total 4949273 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18154 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 18154 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 423 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 423 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 43805 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 43805 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 18577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 18577 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 18577 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 18577 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2786709 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2786709 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1292538 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1292538 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 609189 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 609189 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 443031 # number of WriteLineReq MSHR misses +system.cpu1.dcache.WriteLineReq_mshr_misses::total 443031 # number of WriteLineReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116858 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116858 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202242 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 202242 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4522278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4522278 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 5131467 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 5131467 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22203 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22203 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20755 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20755 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 42958 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 42958 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38628648000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38628648000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23695979500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23695979500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13886318000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13886318000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10075866000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10075866000 # number of WriteLineReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623112500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1623112500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4589466000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4589466000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2110000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2110000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 72400493500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 72400493500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 86286811500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 86286811500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3923399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3923399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3923399500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3923399500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036533 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036533 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018626 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018626 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.783790 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.783790 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.835556 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.835556 # mshr miss rate for WriteLineReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064720 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112080 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112080 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030931 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030931 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034912 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.034912 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13861.744445 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13861.744445 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18332.907427 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18332.907427 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22794.761560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22794.761560 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22743.027012 # average WriteLineReq mshr miss latency +system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22743.027012 # average WriteLineReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13889.613890 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13889.613890 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22692.942119 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22692.942119 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15339.575327 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15339.575327 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15834.301989 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15834.301989 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169476.901633 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 169476.901633 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 88389.279568 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 88389.279568 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 4895837 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.209399 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 437953524 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4896349 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 89.444916 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378871626000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.209399 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969159 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969159 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16009.739671 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16009.739671 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16815.232662 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16815.232662 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176705.828041 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176705.828041 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91331.055915 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91331.055915 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 4981311 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.212019 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 411158765 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4981823 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 82.531789 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8379594860000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.212019 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969164 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969164 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 890596095 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 890596095 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 437953524 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 437953524 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 437953524 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 437953524 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 437953524 # number of overall hits -system.cpu1.icache.overall_hits::total 437953524 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4896349 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4896349 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4896349 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4896349 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4896349 # number of overall misses -system.cpu1.icache.overall_misses::total 4896349 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51444170000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 51444170000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 51444170000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 51444170000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 51444170000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 51444170000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 442849873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 442849873 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 442849873 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 442849873 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 442849873 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 442849873 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011056 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011056 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011056 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011056 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011056 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011056 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10506.638722 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10506.638722 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10506.638722 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10506.638722 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10506.638722 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 837263014 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 837263014 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 411158765 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 411158765 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 411158765 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 411158765 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 411158765 # number of overall hits +system.cpu1.icache.overall_hits::total 411158765 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4981828 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4981828 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4981828 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4981828 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4981828 # number of overall misses +system.cpu1.icache.overall_misses::total 4981828 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54111358000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54111358000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54111358000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54111358000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54111358000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54111358000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 416140593 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 416140593 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 416140593 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 416140593 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 416140593 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 416140593 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011972 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.011972 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011972 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.011972 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011972 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.011972 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10861.747535 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10861.747535 # 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Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1876890 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.671537 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 12823.617935 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 17.493162 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 11.479573 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 226.246124 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.782692 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001068 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000701 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013809 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.798269 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 286 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 54 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15409 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 107 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 144 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 39 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 868 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6435 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7258 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 673 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017456 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003296 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940491 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 348956442 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 348956442 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 258658 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 151547 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 410205 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 3266667 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 3266667 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 6832390 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 6832390 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 881671 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 881671 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4452144 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 4452144 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2841120 # 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Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.775748 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001700 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001407 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.013147 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.792002 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 377 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 55 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15415 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 69 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 165 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 25 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1400 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5858 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4122 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3918 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.023010 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940857 # 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number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3071337500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3071337500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1741999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1741999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9224946500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9224946500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14216700500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14216700500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 26383538000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 26383538000 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6621907000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6621907000 # number of InvalidateReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 360967500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14216700500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 35608484500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 50668548000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482395500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 360967500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14216700500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 35608484500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27800562984 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 78469110984 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9647000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3745274000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3754921000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9647000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3745274000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3754921000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.071192 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses @@ -2288,128 +2290,129 @@ system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.205818 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.205818 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090722 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.239512 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239512 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.567411 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.567411 # mshr miss rate for InvalidateReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.156724 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.066348 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.057520 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090722 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.231758 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.226946 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.226946 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.090876 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.253009 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.253009 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.565542 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.565542 # mshr miss rate for InvalidateReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161990 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.075295 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.065005 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.090876 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246853 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.225464 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26936.029678 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41804.228740 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18587.327591 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18587.327591 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15206.589959 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15206.589959 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 588000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 588000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34644.743535 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34644.743535 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27535.565786 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27162.496717 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27162.496717 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 27231.035824 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 27231.035824 # average InvalidateReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28339.662371 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24495.946902 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31785.328144 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27535.565786 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28691.702955 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41804.228740 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32444.781937 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161459.720089 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160997.031718 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87063.636364 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 84207.984689 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 84217.274932 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 20954555 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10760929 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 564007 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 564007 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228826 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29868.359541 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41689.317380 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18486.785462 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18486.785462 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15186.672699 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15186.672699 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 580666.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 580666.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37417.342684 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37417.342684 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31402.300057 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 29685.784689 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29685.784689 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26547.838498 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26547.838498 # average InvalidateReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31349.139312 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26863.924932 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35116.986088 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31402.300057 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31364.768581 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41689.317380 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34369.290310 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168683.241003 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168284.004840 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 87700 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87184.552353 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87185.868859 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 20600525 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10578683 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 558580 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 558580 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 525208 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9244496 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 16125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 16125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 4351848 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 6833141 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 1083593 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 850253 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 408331 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 372440 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 477174 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1146242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1123232 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4896349 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4644090 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 493781 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateResp 444195 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14688755 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16849115 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 339302 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 606054 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 32483226 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 626700344 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 649733422 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1286368 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2216312 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1279936446 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4601099 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 75959664 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 15521649 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.052382 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.222797 # Request fanout histogram +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 484798 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9068801 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 20755 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 20755 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 4199993 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 6807874 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 1098101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 809012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 385894 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 368515 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 474989 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 57 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1114310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1093127 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 4981828 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4385137 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 490192 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateResp 441051 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 14945187 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16097398 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332311 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 526789 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 31901685 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 637641336 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 617397659 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1265008 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1907912 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1258211915 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4504290 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 75632944 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 15215883 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.052359 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.222750 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 14708591 94.76% 94.76% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 813058 5.24% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 14419192 94.76% 94.76% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 796691 5.24% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 15521649 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 20731667993 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 15215883 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 20375325498 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 171895510 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176794994 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7344633500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 7472852000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7734220026 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7357432377 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 178506000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 174185000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 329015998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 288300000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40399 # Transaction distribution -system.iobus.trans_dist::ReadResp 40399 # Transaction distribution -system.iobus.trans_dist::WriteReq 136980 # Transaction distribution -system.iobus.trans_dist::WriteResp 136980 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47798 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40355 # Transaction distribution +system.iobus.trans_dist::ReadResp 40355 # Transaction distribution +system.iobus.trans_dist::WriteReq 136628 # Transaction distribution +system.iobus.trans_dist::WriteResp 136628 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) @@ -2420,15 +2423,15 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122940 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231738 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231738 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122664 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354758 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47818 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2439,23 +2442,23 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155955 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7355304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155794 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7513345 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 37010502 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36982500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2469,75 +2472,75 @@ system.iobus.reqLayer16.occupancy 14000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 26741000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 26451500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 37418500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 37417000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 570750713 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 569427501 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 92947000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92767000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 148178000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115853 # number of replacements -system.iocache.tags.tagsinuse 11.245503 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115615 # number of replacements +system.iocache.tags.tagsinuse 11.298649 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115869 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9136243501000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.839816 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.405687 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239988 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.462855 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.702844 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9136560427000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.416178 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.882471 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463511 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.242654 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706166 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1043178 # Number of tag accesses -system.iocache.tags.data_accesses 1043178 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040856 # Number of tag accesses +system.iocache.tags.data_accesses 1040856 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8885 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8922 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses -system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115869 # number of demand (read+write) misses -system.iocache.demand_misses::total 115909 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses +system.iocache.demand_misses::total 115651 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115869 # number of overall misses -system.iocache.overall_misses::total 115909 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5278000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1633593087 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1638871087 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115611 # number of overall misses +system.iocache.overall_misses::total 115651 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5193500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1828649003 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1833842503 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12911092626 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12911092626 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5647000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14544685713 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14550332713 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5647000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14544685713 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14550332713 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13346157998 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13346157998 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5562500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15174807001 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15180369501 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5562500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15174807001 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15180369501 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8885 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8922 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) -system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115869 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115909 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115869 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115909 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2551,53 +2554,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 142648.648649 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183859.660889 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183688.756669 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140364.864865 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 205859.394686 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 205587.724552 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120682.463041 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120682.463041 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 141175 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125532.380687 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 141175 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125526.980582 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 125532.380687 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31750 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125048.328442 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125048.328442 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 131260.166371 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139062.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 131257.466859 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 131260.166371 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 41899 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3454 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.192241 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.852617 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106953 # number of writebacks -system.iocache.writebacks::total 106953 # number of writebacks +system.iocache.writebacks::writebacks 106702 # number of writebacks +system.iocache.writebacks::total 106702 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8885 # 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number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1384499003 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1387842503 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7553188799 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 7553188799 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3647000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 8742531886 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 8746178886 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3647000 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2611,662 +2614,659 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 92648.648649 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133859.660889 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133688.756669 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90364.864865 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 155859.394686 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 155587.724552 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70601.106698 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70601.106698 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 91175 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 75451.862759 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 75457.288787 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1378015 # number of replacements -system.l2c.tags.tagsinuse 64998.786153 # Cycle average of tags in use -system.l2c.tags.total_refs 6107230 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1440978 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.238253 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9552186500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11716.268844 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.184810 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 146.917074 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4004.381376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 14231.433494 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7902.194687 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 315.518093 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 369.695425 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2763.350410 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11175.503416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 12240.338524 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.178776 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002242 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061102 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.217154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.120578 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004814 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.005641 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.042165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.170525 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.186773 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.991803 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 12060 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 189 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 50714 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 60 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 153 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 1009 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 1115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9723 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 184 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1849 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9563 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 39124 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.184021 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.002884 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.773834 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 69629880 # Number of tag accesses -system.l2c.tags.data_accesses 69629880 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 2641101 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 2641101 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 213424 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 155298 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 368722 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 50511 # 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number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 512398 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 278781 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 2494703 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 136557 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 120325 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 256882 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 10681 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 422841 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 630910 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 276728 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9775 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 406188 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 561391 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 278781 # number of demand (read+write) hits -system.l2c.demand_hits::total 2607346 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 10681 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5935 # number of overall hits -system.l2c.overall_hits::cpu0.inst 422841 # number of overall hits -system.l2c.overall_hits::cpu0.data 630910 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 276728 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9775 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4116 # number of overall hits -system.l2c.overall_hits::cpu1.inst 406188 # number of overall hits -system.l2c.overall_hits::cpu1.data 561391 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 278781 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14223.146945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 128.223998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 149.509582 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3193.954857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6240.562219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5949.868833 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.180717 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004651 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.005443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.291221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217028 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001957 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002281 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.048736 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.095223 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.090788 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.992758 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 11266 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 259 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 48663 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 152 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 297 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 10816 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 888 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4525 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43209 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.171906 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.003952 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.742538 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 68586261 # Number of tag accesses +system.l2c.tags.data_accesses 68586261 # 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average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80065.548777 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97673.842846 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19906.284749 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19870.744158 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19898.586767 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80641.112172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82903.479826 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76244.907652 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80138.148487 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 114944.988331 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 79929.429143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 78810.825588 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76423.394880 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78953.433292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110557.251321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 94877.918238 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163719.381879 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143473.769616 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 106203.079428 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63067.408696 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 79289.613802 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69050 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 74823.486677 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 72216.646766 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3586859 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2135577 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3113 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.113100 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.123828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.118083 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012676 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.011369 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.012028 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.613362 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.462767 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.542745 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.208316 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.161585 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.235132 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779663 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.455362 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.684738 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.255958 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.154475 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.311206 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105983 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.270672 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470237 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.154126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.262088 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098419 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.206484 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.383460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.255958 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20237.632473 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20659.972419 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20443.328506 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24145.700637 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24889.891697 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24494.500846 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98522.851552 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99422.497215 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 98882.548681 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99545.289138 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 106746.113985 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 114384.543404 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19876.275455 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20102.436048 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19920.298767 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89774.836407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 93508.314220 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104469.653728 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99188.605696 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 123141.079136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 91695.652174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 96817.791688 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 105812.454698 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 104299.249859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124840.992483 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 112159.039894 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159587.876320 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150694.833566 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 109809.654497 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69955.849275 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76719.266383 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69686.363636 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77883.788062 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 74703.544659 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3576184 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2127782 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3085 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 81835 # Transaction distribution -system.membus.trans_dist::ReadResp 841453 # Transaction distribution -system.membus.trans_dist::WriteReq 38513 # Transaction distribution -system.membus.trans_dist::WriteResp 38513 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1169257 # Transaction distribution -system.membus.trans_dist::CleanEvict 224172 # Transaction distribution -system.membus.trans_dist::UpgradeReq 330190 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 306798 # Transaction distribution -system.membus.trans_dist::UpgradeResp 21 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 142313 # Transaction distribution -system.membus.trans_dist::ReadExResp 124217 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 759618 # Transaction distribution -system.membus.trans_dist::InvalidateReq 654423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122940 # Packet count per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 81817 # Transaction distribution +system.membus.trans_dist::ReadResp 843472 # Transaction distribution +system.membus.trans_dist::WriteReq 38449 # Transaction distribution +system.membus.trans_dist::WriteResp 38449 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1169254 # Transaction distribution +system.membus.trans_dist::CleanEvict 223620 # Transaction distribution +system.membus.trans_dist::UpgradeReq 320332 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 305580 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 143723 # Transaction distribution +system.membus.trans_dist::ReadExResp 125482 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 761655 # Transaction distribution +system.membus.trans_dist::InvalidateReq 651499 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122664 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4320804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4469902 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238504 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 238504 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4708406 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155955 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4313500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4462434 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238025 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 238025 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4700459 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124129580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 124337871 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7276480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7276480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131614351 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 603280 # Total snoops (count) -system.membus.snoopTraffic 185472 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2313692 # Request fanout histogram -system.membus.snoop_fanout::mean 0.013382 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.114902 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52356 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 124357036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 124565390 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7261504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7261504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131826894 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 595046 # Total snoops (count) +system.membus.snoopTraffic 184128 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2303059 # Request fanout histogram +system.membus.snoop_fanout::mean 0.014256 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.118544 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2282731 98.66% 98.66% # Request fanout histogram -system.membus.snoop_fanout::1 30961 1.34% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2270227 98.57% 98.57% # Request fanout histogram +system.membus.snoop_fanout::1 32832 1.43% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2313692 # Request fanout histogram -system.membus.reqLayer0.occupancy 101576998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2303059 # Request fanout histogram +system.membus.reqLayer0.occupancy 101257500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21542999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 21679000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8037178912 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8033203938 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4828786098 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4846349578 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 45456460 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 45469982 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3309,78 +3309,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 10929949 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 5951808 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1800454 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 181173 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 166358 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 14815 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47374315410500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 81837 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4119674 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38513 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38513 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 3703405 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2363493 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 695815 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 407836 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1103651 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 294367 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 294367 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 4038548 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 834564 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 806756 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8843715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7139942 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15983657 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 216752505 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 175713942 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 392466447 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2839573 # Total snoops (count) -system.toL2Bus.snoopTraffic 122328784 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 7769609 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.368989 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486467 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 10759482 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 5851735 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1766751 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 181547 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 166860 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 14687 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47405012960500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 81819 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4062742 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38449 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38449 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 3651776 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2342209 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 672985 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 402667 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1075652 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 288170 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 288170 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 3981632 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 828938 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 799211 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8607895 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7128520 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15736415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 211923339 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 174059331 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 385982670 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2818319 # Total snoops (count) +system.toL2Bus.snoopTraffic 121467536 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 7671705 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.367658 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486122 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 4917524 63.29% 63.29% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 2837270 36.52% 99.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 14815 0.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 4865825 63.43% 63.43% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 2791193 36.38% 99.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 14687 0.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 7769609 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 8597464366 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7671705 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8456586164 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 2599172 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2556167 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4012155776 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3921212144 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3555978029 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3534160915 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal index 8a6e02412..1ab2ced54 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000027] Console: colour dummy device 80x25
-[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000032] pid_max: default: 32768 minimum: 301
-[ 0.000045] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000047] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000186] hw perfevents: no hardware support available
-[ 0.060051] CPU1: Booted secondary processor
-[ 1.080095] CPU2: failed to come online
-[ 2.100183] CPU3: failed to come online
-[ 2.100186] Brought up 2 CPUs
-[ 2.100188] SMP: Total of 2 processors activated.
-[ 2.100259] devtmpfs: initialized
-[ 2.100898] atomic64_test: passed
-[ 2.100952] regulator-dummy: no parameters
-[ 2.101389] NET: Registered protocol family 16
-[ 2.101557] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 2.101563] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 2.102363] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 2.102366] Serial: AMBA PL011 UART driver
-[ 2.102592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 2.102637] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 2.103214] console [ttyAMA0] enabled
-[ 2.103383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 2.103459] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 2.103535] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 2.103603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 2.130362] 3V3: 3300 mV
-[ 2.130420] vgaarb: loaded
-[ 2.130477] SCSI subsystem initialized
-[ 2.130513] libata version 3.00 loaded.
-[ 2.130567] usbcore: registered new interface driver usbfs
-[ 2.130587] usbcore: registered new interface driver hub
-[ 2.130614] usbcore: registered new device driver usb
-[ 2.130645] pps_core: LinuxPPS API ver. 1 registered
-[ 2.130654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 2.130674] PTP clock support registered
-[ 2.130822] Switched to clocksource arch_sys_counter
-[ 2.132478] NET: Registered protocol family 2
-[ 2.132574] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 2.132593] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 2.132613] TCP: Hash tables configured (established 2048 bind 2048)
-[ 2.132642] TCP: reno registered
-[ 2.132649] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.132663] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 2.132704] NET: Registered protocol family 1
-[ 2.132763] RPC: Registered named UNIX socket transport module.
-[ 2.132774] RPC: Registered udp transport module.
-[ 2.132782] RPC: Registered tcp transport module.
-[ 2.132791] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 2.132804] PCI: CLS 0 bytes, default 64
-[ 2.133012] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 2.133128] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 2.135205] fuse init (API version 7.23)
-[ 2.135350] msgmni has been set to 469
-[ 2.135656] io scheduler noop registered
-[ 2.135718] io scheduler cfq registered (default)
-[ 2.136286] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 2.136300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 2.136311] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 2.136324] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 2.136335] pci_bus 0000:00: scanning bus
-[ 2.136346] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 2.136360] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 2.136375] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.136416] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 2.136429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 2.136440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 2.136452] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 2.136463] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 2.136474] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 2.136486] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 2.136527] pci_bus 0000:00: fixups for bus
-[ 2.136536] pci_bus 0000:00: bus scan returning with max=00
-[ 2.136548] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 2.136569] pci 0000:00:00.0: fixup irq: got 33
-[ 2.136578] pci 0000:00:00.0: assigning IRQ 33
-[ 2.136589] pci 0000:00:01.0: fixup irq: got 34
-[ 2.136598] pci 0000:00:01.0: assigning IRQ 34
-[ 2.136609] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 2.136623] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 2.136636] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 2.136650] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 2.136662] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 2.136674] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 2.136686] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 2.136698] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 2.137491] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 2.137826] ata_piix 0000:00:01.0: version 2.13
-[ 2.137837] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 2.137864] ata_piix 0000:00:01.0: enabling bus mastering
-[ 2.138204] scsi0 : ata_piix
-[ 2.138329] scsi1 : ata_piix
-[ 2.138380] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 2.138393] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 2.138543] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 2.138556] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 2.138573] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 2.138585] e1000 0000:00:00.0: enabling bus mastering
-[ 2.280852] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 2.280862] ata1.00: 2096640 sectors, multi 0: LBA
-[ 2.280892] ata1.00: configured for UDMA/33
-[ 2.280951] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 2.281082] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 2.281116] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 2.281160] sd 0:0:0:0: [sda] Write Protect is off
-[ 2.281170] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 2.281192] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 2.281337] sda: sda1
-[ 2.281470] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 2.401164] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 2.401177] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 2.401211] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 2.401224] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 2.401253] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 2.401268] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 2.401414] usbcore: registered new interface driver usb-storage
-[ 2.401486] mousedev: PS/2 mouse device common for all mice
-[ 2.401677] usbcore: registered new interface driver usbhid
-[ 2.401687] usbhid: USB HID core driver
-[ 2.401726] TCP: cubic registered
-[ 2.401734] NET: Registered protocol family 17
- -[ 2.402215] devtmpfs: mounted
-[ 2.402270] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000029] Console: colour dummy device 80x25
+[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000033] pid_max: default: 32768 minimum: 301
+[ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000190] hw perfevents: no hardware support available
+[ 0.060052] CPU1: Booted secondary processor
+[ 1.080092] CPU2: failed to come online
+[ 2.100178] CPU3: failed to come online
+[ 2.100181] Brought up 2 CPUs
+[ 2.100182] SMP: Total of 2 processors activated.
+[ 2.100254] devtmpfs: initialized
+[ 2.100899] atomic64_test: passed
+[ 2.100953] regulator-dummy: no parameters
+[ 2.101395] NET: Registered protocol family 16
+[ 2.101565] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 2.101572] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 2.102371] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 2.102374] Serial: AMBA PL011 UART driver
+[ 2.102603] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 2.102648] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 2.103226] console [ttyAMA0] enabled
+[ 2.103397] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 2.103474] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 2.103550] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 2.103618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 2.130484] 3V3: 3300 mV
+[ 2.130542] vgaarb: loaded
+[ 2.130598] SCSI subsystem initialized
+[ 2.130640] libata version 3.00 loaded.
+[ 2.130696] usbcore: registered new interface driver usbfs
+[ 2.130716] usbcore: registered new interface driver hub
+[ 2.130745] usbcore: registered new device driver usb
+[ 2.130775] pps_core: LinuxPPS API ver. 1 registered
+[ 2.130785] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 2.130805] PTP clock support registered
+[ 2.130963] Switched to clocksource arch_sys_counter
+[ 2.132610] NET: Registered protocol family 2
+[ 2.132708] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 2.132728] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 2.132748] TCP: Hash tables configured (established 2048 bind 2048)
+[ 2.132775] TCP: reno registered
+[ 2.132782] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132796] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 2.132838] NET: Registered protocol family 1
+[ 2.132904] RPC: Registered named UNIX socket transport module.
+[ 2.132915] RPC: Registered udp transport module.
+[ 2.132923] RPC: Registered tcp transport module.
+[ 2.132932] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 2.132945] PCI: CLS 0 bytes, default 64
+[ 2.133141] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 2.133256] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 2.135328] fuse init (API version 7.23)
+[ 2.135440] msgmni has been set to 469
+[ 2.135797] io scheduler noop registered
+[ 2.135862] io scheduler cfq registered (default)
+[ 2.136433] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 2.136447] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 2.136458] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 2.136472] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 2.136482] pci_bus 0000:00: scanning bus
+[ 2.136494] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 2.136508] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 2.136523] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136564] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 2.136577] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 2.136588] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 2.136600] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 2.136611] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 2.136622] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 2.136634] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 2.136675] pci_bus 0000:00: fixups for bus
+[ 2.136684] pci_bus 0000:00: bus scan returning with max=00
+[ 2.136697] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 2.136718] pci 0000:00:00.0: fixup irq: got 33
+[ 2.136727] pci 0000:00:00.0: assigning IRQ 33
+[ 2.136739] pci 0000:00:01.0: fixup irq: got 34
+[ 2.136748] pci 0000:00:01.0: assigning IRQ 34
+[ 2.136760] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 2.136773] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 2.136787] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 2.136801] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 2.136813] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 2.136825] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 2.136837] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 2.136849] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 2.137426] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 2.137740] ata_piix 0000:00:01.0: version 2.13
+[ 2.137750] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 2.137778] ata_piix 0000:00:01.0: enabling bus mastering
+[ 2.138110] scsi0 : ata_piix
+[ 2.138200] scsi1 : ata_piix
+[ 2.138235] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 2.138247] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 2.138381] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 2.138393] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 2.138410] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 2.138423] e1000 0000:00:00.0: enabling bus mastering
+[ 2.290984] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 2.290994] ata1.00: 2096640 sectors, multi 0: LBA
+[ 2.291024] ata1.00: configured for UDMA/33
+[ 2.291083] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 2.291212] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 2.291226] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 2.291255] sd 0:0:0:0: [sda] Write Protect is off
+[ 2.291265] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 2.291288] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 2.291434] sda: sda1
+[ 2.291570] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 2.411274] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 2.411288] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 2.411313] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 2.411324] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 2.411348] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 2.411360] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 2.411448] usbcore: registered new interface driver usb-storage
+[ 2.411534] mousedev: PS/2 mouse device common for all mice
+[ 2.411744] usbcore: registered new interface driver usbhid
+[ 2.411754] usbhid: USB HID core driver
+[ 2.411794] TCP: cubic registered
+[ 2.411802] NET: Registered protocol family 17
+ +[ 2.412341] devtmpfs: mounted
+[ 2.412395] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 2.442337] udevd[608]: starting version 182
+[ 2.452586] udevd[609]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 2.533997] random: dd urandom read with 18 bits of entropy available
+[ 2.534161] random: dd urandom read with 18 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 2.671053] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 2.671190] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|