stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 81 insertions, 101 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
index 3c1e4fda0..9849a9aeb 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                 51.759374                       # Nu
 sim_ticks                                51759374264500                       # Number of ticks simulated
 final_tick                               51759374264500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1125548                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1322684                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            69608471837                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 675480                       # Number of bytes of host memory used
-host_seconds                                   743.58                       # Real time elapsed on the host
+host_inst_rate                                 729832                       # Simulator instruction rate (inst/s)
+host_op_rate                                   857659                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            45135767006                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 675484                       # Number of bytes of host memory used
+host_seconds                                  1146.75                       # Real time elapsed on the host
 sim_insts                                   836933434                       # Number of instructions simulated
 sim_ops                                     983519389                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -613,10 +613,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data      3338150
 system.cpu.dcache.LoadLockedReq_hits::total      3338150                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data      3623891                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total      3623891                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data     283201595                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        283201595                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    283575709                       # number of overall hits
-system.cpu.dcache.overall_hits::total       283575709                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     283534216                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        283534216                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    283908330                       # number of overall hits
+system.cpu.dcache.overall_hits::total       283908330                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      4894991                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       4894991                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      1998130                       # number of WriteReq misses
@@ -629,10 +629,10 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data       287378
 system.cpu.dcache.LoadLockedReq_misses::total       287378                       # number of LoadLockedReq misses
 system.cpu.dcache.StoreCondReq_misses::cpu.data            1                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            1                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data      6893121                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        6893121                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      8029572                       # number of overall misses
-system.cpu.dcache.overall_misses::total       8029572                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data      8114631                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        8114631                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9251082                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9251082                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data  84471929500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total  84471929500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data  70206054500                       # number of WriteReq miss cycles
@@ -643,10 +643,10 @@ system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4418678000
 system.cpu.dcache.LoadLockedReq_miss_latency::total   4418678000                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        82000                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total        82000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 154677984000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 154677984000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 154677984000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 154677984000                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 202906742000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 202906742000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 202906742000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 202906742000                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data    152330440                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total    152330440                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    137764276                       # number of WriteReq accesses(hits+misses)
@@ -659,10 +659,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3625528
 system.cpu.dcache.LoadLockedReq_accesses::total      3625528                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data      3623892                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total      3623892                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    290094716                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    290094716                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    291605281                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    291605281                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    291648847                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    291648847                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    293159412                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    293159412                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032134                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.032134                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014504                       # miss rate for WriteReq accesses
@@ -675,10 +675,10 @@ system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.079265
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.079265                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000000                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000000                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.023762                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.023762                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.027536                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.027536                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.027823                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.027823                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.031556                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.031556                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297                       # average WriteReq miss latency
@@ -689,18 +689,16 @@ system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487                       # average LoadLockedReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        82000                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        82000                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22439.470307                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19263.540323                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25005.048535                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 21933.298397                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks      7313678                       # number of writebacks
 system.cpu.dcache.writebacks::total           7313678                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21981                       # number of ReadReq MSHR hits
@@ -725,10 +723,10 @@ system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       218778
 system.cpu.dcache.LoadLockedReq_mshr_misses::total       218778                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            1                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            1                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      6849886                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      6849886                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      7984572                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      7984572                       # number of overall MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      8071396                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      8071396                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9206082                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9206082                       # number of overall MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.ReadReq_mshr_uncacheable::total        33702                       # number of ReadReq MSHR uncacheable
 system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33708                       # number of WriteReq MSHR uncacheable
@@ -747,16 +745,14 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3007041000
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3007041000                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        81000                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        81000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 145533577500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 166975219500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 192540825500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 213982467500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6199681500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6199681500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6217603000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6217603000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12417284500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total  12417284500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6199681500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   6199681500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.031990                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.031990                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014350                       # mshr miss rate for WriteReq accesses
@@ -769,10 +765,10 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060344
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060344                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000000                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023613                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.023613                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027381                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.027381                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027675                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.027675                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031403                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031403                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701                       # average WriteReq mshr miss latency
@@ -785,17 +781,14 @@ system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        81000                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        81000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819                       # average overall mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540                       # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680                       # average overall mshr uncacheable latency
 system.cpu.icache.tags.replacements          13331164                       # number of replacements
 system.cpu.icache.tags.tagsinuse           511.820795                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           824117568                       # Total number of references to valid blocks.
@@ -855,8 +848,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks     13331164                       # number of writebacks
 system.cpu.icache.writebacks::total          13331164                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13331681                       # number of ReadReq MSHR misses
@@ -895,7 +886,6 @@ system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188
 system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188                       # average ReadReq mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188                       # average overall mshr uncacheable latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188                       # average overall mshr uncacheable latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements          1036266                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        65255.052774                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs           41658706                       # Total number of references to valid blocks.
@@ -1087,8 +1077,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       879823                       # number of writebacks
 system.cpu.l2cache.writebacks::total           879823                       # number of writebacks
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         2426                       # number of ReadReq MSHR misses
@@ -1152,11 +1140,9 @@ system.cpu.l2cache.overall_mshr_miss_latency::total  78834601014
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5777601500                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total  10675326000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5829950000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5829950000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   4897724500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607551500                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total  16505276000                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5777601500                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total  10675326000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.007675                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010168                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.008763                       # mshr miss rate for ReadReq accesses
@@ -1210,12 +1196,9 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515                       # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103                       # average overall mshr uncacheable latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531                       # average overall mshr uncacheable latency
 system.cpu.toL2Bus.snoop_filter.tot_requests     45953712                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests     23239521                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1757                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
@@ -1372,11 +1355,11 @@ system.iocache.WriteReq_misses::total               3                       # nu
 system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
 system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
 system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide         8860                       # number of demand (read+write) misses
-system.iocache.demand_misses::total              8900                       # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide       115524                       # number of demand (read+write) misses
+system.iocache.demand_misses::total            115564                       # number of demand (read+write) misses
 system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
-system.iocache.overall_misses::realview.ide         8860                       # number of overall misses
-system.iocache.overall_misses::total             8900                       # number of overall misses
+system.iocache.overall_misses::realview.ide       115524                       # number of overall misses
+system.iocache.overall_misses::total           115564                       # number of overall misses
 system.iocache.ReadReq_miss_latency::realview.ethernet      5070000                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::realview.ide   1628892126                       # number of ReadReq miss cycles
 system.iocache.ReadReq_miss_latency::total   1633962126                       # number of ReadReq miss cycles
@@ -1385,11 +1368,11 @@ system.iocache.WriteReq_miss_latency::total       351000                       #
 system.iocache.WriteLineReq_miss_latency::realview.ide  13410994738                       # number of WriteLineReq miss cycles
 system.iocache.WriteLineReq_miss_latency::total  13410994738                       # number of WriteLineReq miss cycles
 system.iocache.demand_miss_latency::realview.ethernet      5421000                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide   1628892126                       # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total   1634313126                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide  15039886864                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total  15045307864                       # number of demand (read+write) miss cycles
 system.iocache.overall_miss_latency::realview.ethernet      5421000                       # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide   1628892126                       # number of overall miss cycles
-system.iocache.overall_miss_latency::total   1634313126                       # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide  15039886864                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total  15045307864                       # number of overall miss cycles
 system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::realview.ide         8860                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total           8897                       # number of ReadReq accesses(hits+misses)
@@ -1398,11 +1381,11 @@ system.iocache.WriteReq_accesses::total             3                       # nu
 system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
 system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide         8860                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total            8900                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide       115524                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::total          115564                       # number of demand (read+write) accesses
 system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide         8860                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total           8900                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide       115524                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::total         115564                       # number of overall (read+write) accesses
 system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
 system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
@@ -1424,19 +1407,17 @@ system.iocache.WriteReq_avg_miss_latency::total       117000
 system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949                       # average WriteLineReq miss latency
 system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949                       # average WriteLineReq miss latency
 system.iocache.demand_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183847.869752                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 183630.688315                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 130188.418545                       # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 130190.265688                       # average overall miss latency
 system.iocache.overall_avg_miss_latency::realview.ethernet       135525                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183847.869752                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 183630.688315                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 130188.418545                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 130190.265688                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs         32190                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                 3353                       # number of cycles access was blocked
 system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
 system.iocache.avg_blocked_cycles::no_mshrs     9.600358                       # average number of cycles each access was blocked
 system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
 system.iocache.writebacks::writebacks          106631                       # number of writebacks
 system.iocache.writebacks::total               106631                       # number of writebacks
 system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
@@ -1447,11 +1428,11 @@ system.iocache.WriteReq_mshr_misses::total            3                       #
 system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
 system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
 system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide         8860                       # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total         8900                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::realview.ide       115524                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total       115564                       # number of demand (read+write) MSHR misses
 system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide         8860                       # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total         8900                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::realview.ide       115524                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total       115564                       # number of overall MSHR misses
 system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3220000                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::realview.ide   1185892126                       # number of ReadReq MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_latency::total   1189112126                       # number of ReadReq MSHR miss cycles
@@ -1460,11 +1441,11 @@ system.iocache.WriteReq_mshr_miss_latency::total       201000
 system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8072604881                       # number of WriteLineReq MSHR miss cycles
 system.iocache.WriteLineReq_mshr_miss_latency::total   8072604881                       # number of WriteLineReq MSHR miss cycles
 system.iocache.demand_mshr_miss_latency::realview.ethernet      3421000                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide   1185892126                       # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total   1189313126                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide   9258497007                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   9261918007                       # number of demand (read+write) MSHR miss cycles
 system.iocache.overall_mshr_miss_latency::realview.ethernet      3421000                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide   1185892126                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total   1189313126                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide   9258497007                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   9261918007                       # number of overall MSHR miss cycles
 system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
 system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
@@ -1486,12 +1467,11 @@ system.iocache.WriteReq_avg_mshr_miss_latency::total        67000
 system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823                       # average WriteLineReq mshr miss latency
 system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823                       # average WriteLineReq mshr miss latency
 system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752                       # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 133630.688315                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053                       # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 80145.356746                       # average overall mshr miss latency
 system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        85525                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 133630.688315                       # average overall mshr miss latency
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 80145.356746                       # average overall mshr miss latency
 system.membus.trans_dist::ReadReq               76827                       # Transaction distribution
 system.membus.trans_dist::ReadResp             389416                       # Transaction distribution
 system.membus.trans_dist::WriteReq              33708                       # Transaction distribution