diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt | 2134 |
1 files changed, 1068 insertions, 1066 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index b27222f80..f5f82f47e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811415 # Number of seconds simulated -sim_ticks 51811415265500 # Number of ticks simulated -final_tick 51811415265500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.811400 # Number of seconds simulated +sim_ticks 51811399994500 # Number of ticks simulated +final_tick 51811399994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 625298 # Simulator instruction rate (inst/s) -host_op_rate 734839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39084409400 # Simulator tick rate (ticks/s) -host_mem_usage 677180 # Number of bytes of host memory used -host_seconds 1325.63 # Real time elapsed on the host -sim_insts 828913449 # Number of instructions simulated -sim_ops 974124045 # Number of ops (including micro ops) simulated +host_inst_rate 805770 # Simulator instruction rate (inst/s) +host_op_rate 946938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50389185573 # Simulator tick rate (ticks/s) +host_mem_usage 678984 # Number of bytes of host memory used +host_seconds 1028.22 # Real time elapsed on the host +sim_insts 828512987 # Number of instructions simulated +sim_ops 973664549 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 133696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 141376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4656308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65123848 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401856 # Number of bytes read from this memory -system.physmem.bytes_read::total 70457084 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4656308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4656308 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61286080 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 141952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4623732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 65034376 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 398080 # Number of bytes read from this memory +system.physmem.bytes_read::total 70331708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4623732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4623732 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61230400 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 61306660 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 113162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1017573 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6279 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1141312 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 957595 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61250980 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2218 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 112653 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1016175 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1139353 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 956725 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 960168 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2580 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 2729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 89870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1256940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1359876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1182868 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 959298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 2740 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 89242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1255214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1357456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 89242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89242 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1181794 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1183265 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1182868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2580 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 2729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1257337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2543141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1141312 # Number of read requests accepted -system.physmem.writeReqs 960168 # Number of write requests accepted -system.physmem.readBursts 1141312 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 960168 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72995200 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 48768 # Total number of bytes read from write queue -system.physmem.bytesWritten 61305216 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70457084 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 61306660 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 762 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2248 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 295918 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70676 # Per bank write bursts -system.physmem.perBankRdBursts::1 76921 # Per bank write bursts -system.physmem.perBankRdBursts::2 71652 # Per bank write bursts -system.physmem.perBankRdBursts::3 67938 # Per bank write bursts -system.physmem.perBankRdBursts::4 64385 # Per bank write bursts -system.physmem.perBankRdBursts::5 70205 # Per bank write bursts -system.physmem.perBankRdBursts::6 66024 # Per bank write bursts -system.physmem.perBankRdBursts::7 63727 # Per bank write bursts -system.physmem.perBankRdBursts::8 65795 # Per bank write bursts -system.physmem.perBankRdBursts::9 109889 # Per bank write bursts -system.physmem.perBankRdBursts::10 68785 # Per bank write bursts -system.physmem.perBankRdBursts::11 70022 # Per bank write bursts -system.physmem.perBankRdBursts::12 67859 # Per bank write bursts -system.physmem.perBankRdBursts::13 71968 # Per bank write bursts -system.physmem.perBankRdBursts::14 68874 # Per bank write bursts -system.physmem.perBankRdBursts::15 65830 # Per bank write bursts -system.physmem.perBankWrBursts::0 58715 # Per bank write bursts -system.physmem.perBankWrBursts::1 63168 # Per bank write bursts -system.physmem.perBankWrBursts::2 61317 # Per bank write bursts -system.physmem.perBankWrBursts::3 60411 # Per bank write bursts -system.physmem.perBankWrBursts::4 56741 # Per bank write bursts -system.physmem.perBankWrBursts::5 60657 # Per bank write bursts -system.physmem.perBankWrBursts::6 57878 # Per bank write bursts -system.physmem.perBankWrBursts::7 57357 # Per bank write bursts -system.physmem.perBankWrBursts::8 58434 # Per bank write bursts -system.physmem.perBankWrBursts::9 60882 # Per bank write bursts -system.physmem.perBankWrBursts::10 59842 # Per bank write bursts -system.physmem.perBankWrBursts::11 61839 # Per bank write bursts -system.physmem.perBankWrBursts::12 59187 # Per bank write bursts -system.physmem.perBankWrBursts::13 62791 # Per bank write bursts -system.physmem.perBankWrBursts::14 60690 # Per bank write bursts -system.physmem.perBankWrBursts::15 57985 # Per bank write bursts +system.physmem.bw_write::total 1182191 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1181794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 2740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 89242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1255611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2539647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1139353 # Number of read requests accepted +system.physmem.writeReqs 959298 # Number of write requests accepted +system.physmem.readBursts 1139353 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 959298 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 72868032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 50560 # Total number of bytes read from write queue +system.physmem.bytesWritten 61249856 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 70331708 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 61250980 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 790 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 69574 # Per bank write bursts +system.physmem.perBankRdBursts::1 73483 # Per bank write bursts +system.physmem.perBankRdBursts::2 70905 # Per bank write bursts +system.physmem.perBankRdBursts::3 67568 # Per bank write bursts +system.physmem.perBankRdBursts::4 64326 # Per bank write bursts +system.physmem.perBankRdBursts::5 70688 # Per bank write bursts +system.physmem.perBankRdBursts::6 65575 # Per bank write bursts +system.physmem.perBankRdBursts::7 64409 # Per bank write bursts +system.physmem.perBankRdBursts::8 65562 # Per bank write bursts +system.physmem.perBankRdBursts::9 110058 # Per bank write bursts +system.physmem.perBankRdBursts::10 69387 # Per bank write bursts +system.physmem.perBankRdBursts::11 70852 # Per bank write bursts +system.physmem.perBankRdBursts::12 67727 # Per bank write bursts +system.physmem.perBankRdBursts::13 71395 # Per bank write bursts +system.physmem.perBankRdBursts::14 70177 # Per bank write bursts +system.physmem.perBankRdBursts::15 66877 # Per bank write bursts +system.physmem.perBankWrBursts::0 57914 # Per bank write bursts +system.physmem.perBankWrBursts::1 61200 # Per bank write bursts +system.physmem.perBankWrBursts::2 60974 # Per bank write bursts +system.physmem.perBankWrBursts::3 59703 # Per bank write bursts +system.physmem.perBankWrBursts::4 56782 # Per bank write bursts +system.physmem.perBankWrBursts::5 61096 # Per bank write bursts +system.physmem.perBankWrBursts::6 57709 # Per bank write bursts +system.physmem.perBankWrBursts::7 57516 # Per bank write bursts +system.physmem.perBankWrBursts::8 58389 # Per bank write bursts +system.physmem.perBankWrBursts::9 61168 # Per bank write bursts +system.physmem.perBankWrBursts::10 60736 # Per bank write bursts +system.physmem.perBankWrBursts::11 62143 # Per bank write bursts +system.physmem.perBankWrBursts::12 59319 # Per bank write bursts +system.physmem.perBankWrBursts::13 62705 # Per bank write bursts +system.physmem.perBankWrBursts::14 61087 # Per bank write bursts +system.physmem.perBankWrBursts::15 58588 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 35 # Number of times write queue was full causing retry -system.physmem.totGap 51811412436500 # Total gap between requests +system.physmem.numWrRetry 61 # Number of times write queue was full causing retry +system.physmem.totGap 51811397057500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1098196 # Read request sizes (log2) +system.physmem.readPktSize::6 1096237 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 957595 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1113641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 463 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 69 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 956725 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 21338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 330 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 485 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,117 +159,123 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13676 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 54291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 56655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 57800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 58177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 58681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 59112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 63114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 58508 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 57924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 55949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 55254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 54682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 493 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 342 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 451440 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.492681 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.675079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.019607 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 180783 40.05% 40.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 110069 24.38% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39371 8.72% 73.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22726 5.03% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15993 3.54% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11772 2.61% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9986 2.21% 86.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8783 1.95% 88.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51957 11.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 451440 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 53917 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.153458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 336.779025 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 53915 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 13396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 55236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 55847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 56596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 57293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 56619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 58037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 57181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 56145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 56000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 450226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 297.889433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.979745 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.177331 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 179632 39.90% 39.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 110318 24.50% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39188 8.70% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22734 5.05% 78.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 15887 3.53% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11846 2.63% 84.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9963 2.21% 86.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8722 1.94% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 51936 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 450226 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 53627 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.230425 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 337.691151 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 53625 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 53917 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 53917 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.766085 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.131013 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.603955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51657 95.81% 95.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 251 0.47% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 85 0.16% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 305 0.57% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 61 0.11% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 347 0.64% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 210 0.39% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.03% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 56 0.10% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 148 0.27% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 29 0.05% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 23 0.04% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 456 0.85% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 29 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 32 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 152 0.28% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 7 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 53627 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 53627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.846029 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.135395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.325860 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51578 96.18% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 290 0.54% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 64 0.12% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 105 0.20% 97.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 36 0.07% 97.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 101 0.19% 97.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 231 0.43% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.05% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 324 0.60% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 70 0.13% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 27 0.05% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 55 0.10% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 281 0.52% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 24 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 27 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 150 0.28% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 183 0.34% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 26 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 53917 # Writes before turning the bus around for reads -system.physmem.totQLat 14358242809 # Total ticks spent queuing -system.physmem.totMemAccLat 35743555309 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5702750000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12588.88 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 16 0.03% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 53627 # Writes before turning the bus around for reads +system.physmem.totQLat 14356871098 # Total ticks spent queuing +system.physmem.totMemAccLat 35704927348 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5692815000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12609.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31338.88 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31359.64 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s @@ -279,40 +285,40 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.21 # Average write queue length when enqueuing -system.physmem.readRowHits 919470 # Number of row buffer hits during reads -system.physmem.writeRowHits 727533 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.95 # Row buffer hit rate for writes -system.physmem.avgGap 24654725.45 # Average gap between requests -system.physmem.pageHitRate 78.49 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1712392920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 934341375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4301879400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3086061120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1295992039365 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29950012638750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34640108967570 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.580666 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49823953491004 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730096940000 # Time in different power states +system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing +system.physmem.readRowHits 917761 # Number of row buffer hits during reads +system.physmem.writeRowHits 727604 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.03 # Row buffer hit rate for writes +system.physmem.avgGap 24687952.91 # Average gap between requests +system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1698338880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 926673000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4262879400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3064353120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1294076187855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951683866750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34639780896525 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.574535 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49826749097915 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730096420000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 257364177996 # Time in different power states +system.physmem_0.memoryStateTime::ACT 254553819585 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1700493480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 927848625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4594371600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3121092000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384069614640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1294725453480 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29951123679000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34640262552825 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.583630 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49825763906946 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730096940000 # Time in different power states +system.physmem_1.actEnergy 1705369680 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 930509250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4617873000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3137194800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1296366805530 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29949674553000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34640500902780 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.588432 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49823352477739 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730096420000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 255552101804 # Time in different power states +system.physmem_1.memoryStateTime::ACT 257948478511 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -366,71 +372,70 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 185222 # Table walker walks requested -system.cpu.dtb.walker.walksLong 185222 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12899 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144060 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 185205 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.215977 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.785904 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 185203 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 185086 # Table walker walks requested +system.cpu.dtb.walker.walksLong 185086 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12788 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144037 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 185071 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.216133 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.811526 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 185069 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 185205 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 156976 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24757.998038 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20851.674753 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17681.260030 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 155823 99.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 3 0.00% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1006 0.64% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 12 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 72 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 20 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 30 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::total 185071 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 156840 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24753.656593 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20840.255945 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 17740.873102 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 155696 99.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.27% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 981 0.63% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 36 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 156976 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 3935879148 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.602257 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489432 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1565466704 39.77% 39.77% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 2370412444 60.23% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 3935879148 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 144061 91.78% 91.78% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12899 8.22% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 156960 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 156840 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -374556148 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 5.053125 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 1518122704 -405.31% -405.31% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -1892678852 505.31% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -374556148 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 144038 91.85% 91.85% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12788 8.15% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 156826 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185086 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185222 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156960 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185086 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156826 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156960 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 342182 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156826 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 341912 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 156096920 # DTB read hits -system.cpu.dtb.read_misses 137670 # DTB read misses -system.cpu.dtb.write_hits 141678029 # DTB write hits -system.cpu.dtb.write_misses 47552 # DTB write misses +system.cpu.dtb.read_hits 156026006 # DTB read hits +system.cpu.dtb.read_misses 137641 # DTB read misses +system.cpu.dtb.write_hits 141600690 # DTB write hits +system.cpu.dtb.write_misses 47445 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70722 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 70612 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6537 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 156234590 # DTB read accesses -system.cpu.dtb.write_accesses 141725581 # DTB write accesses +system.cpu.dtb.read_accesses 156163647 # DTB read accesses +system.cpu.dtb.write_accesses 141648135 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 297774949 # DTB hits -system.cpu.dtb.misses 185222 # DTB misses -system.cpu.dtb.accesses 297960171 # DTB accesses +system.cpu.dtb.hits 297626696 # DTB hits +system.cpu.dtb.misses 185086 # DTB misses +system.cpu.dtb.accesses 297811782 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,44 +465,42 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 118503 # Table walker walks requested -system.cpu.itb.walker.walksLong 118503 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walks 118473 # Table walker walks requested +system.cpu.itb.walker.walksLong 118473 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107075 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 118503 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 118503 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 118503 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108185 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28674.682257 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24804.583165 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21241.542539 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 106795 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1213 1.12% 99.84% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 32 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 69 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 26 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 33 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108185 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107045 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 118473 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 118473 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 118473 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108155 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28668.184550 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24838.617630 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 20892.143337 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 106773 98.72% 98.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1223 1.13% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 21 0.02% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 63 0.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 24 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 37 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108155 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107075 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107045 98.97% 98.97% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108185 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108155 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118503 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 118503 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118473 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 118473 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108185 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108185 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 226688 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 829424054 # ITB inst hits -system.cpu.itb.inst_misses 118503 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108155 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108155 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 226628 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 829023400 # ITB inst hits +system.cpu.itb.inst_misses 118473 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -506,48 +509,48 @@ system.cpu.itb.flush_tlb 10 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50494 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 50418 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 829542557 # ITB inst accesses -system.cpu.itb.hits 829424054 # DTB hits -system.cpu.itb.misses 118503 # DTB misses -system.cpu.itb.accesses 829542557 # DTB accesses -system.cpu.numCycles 103622830531 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 829141873 # ITB inst accesses +system.cpu.itb.hits 829023400 # DTB hits +system.cpu.itb.misses 118473 # DTB misses +system.cpu.itb.accesses 829141873 # DTB accesses +system.cpu.numCycles 103622799989 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed -system.cpu.committedInsts 828913449 # Number of instructions committed -system.cpu.committedOps 974124045 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 895594684 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899411 # Number of float alu accesses -system.cpu.num_func_calls 49818288 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 125653589 # number of instructions that are conditional controls -system.cpu.num_int_insts 895594684 # number of integer instructions -system.cpu.num_fp_insts 899411 # number of float instructions -system.cpu.num_int_register_reads 1295586183 # number of times the integer registers were read -system.cpu.num_int_register_writes 709722189 # number of times the integer registers were written +system.cpu.kern.inst.quiesce 15972 # number of quiesce instructions executed +system.cpu.committedInsts 828512987 # Number of instructions committed +system.cpu.committedOps 973664549 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 895161313 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 899443 # Number of float alu accesses +system.cpu.num_func_calls 49782138 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 125600972 # number of instructions that are conditional controls +system.cpu.num_int_insts 895161313 # number of integer instructions +system.cpu.num_fp_insts 899443 # number of float instructions +system.cpu.num_int_register_reads 1295047006 # number of times the integer registers were read +system.cpu.num_int_register_writes 709396185 # number of times the integer registers were written system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read -system.cpu.num_fp_register_writes 757584 # number of times the floating registers were written -system.cpu.num_cc_register_reads 214510161 # number of times the CC registers were read -system.cpu.num_cc_register_writes 213901888 # number of times the CC registers were written -system.cpu.num_mem_refs 297752944 # number of memory refs -system.cpu.num_load_insts 156086585 # Number of load instructions -system.cpu.num_store_insts 141666359 # Number of store instructions -system.cpu.num_idle_cycles 100538909625.142059 # Number of idle cycles -system.cpu.num_busy_cycles 3083920905.857941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029761 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970239 # Percentage of idle cycles -system.cpu.Branches 184946450 # Number of branches fetched +system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written +system.cpu.num_cc_register_reads 214441530 # number of times the CC registers were read +system.cpu.num_cc_register_writes 213833710 # number of times the CC registers were written +system.cpu.num_mem_refs 297604519 # number of memory refs +system.cpu.num_load_insts 156015499 # Number of load instructions +system.cpu.num_store_insts 141589020 # Number of store instructions +system.cpu.num_idle_cycles 100541051528.316055 # Number of idle cycles +system.cpu.num_busy_cycles 3081748460.683940 # Number of busy cycles +system.cpu.not_idle_fraction 0.029740 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970260 # Percentage of idle cycles +system.cpu.Branches 184855625 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 674595310 69.21% 69.21% # Class of executed instruction -system.cpu.op_class::IntMult 2119774 0.22% 69.43% # Class of executed instruction -system.cpu.op_class::IntDiv 97321 0.01% 69.44% # Class of executed instruction +system.cpu.op_class::IntAlu 674284702 69.21% 69.21% # Class of executed instruction +system.cpu.op_class::IntMult 2119126 0.22% 69.43% # Class of executed instruction +system.cpu.op_class::IntDiv 97314 0.01% 69.44% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction @@ -574,120 +577,120 @@ system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::MemRead 156086585 16.01% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 141666359 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 156015499 16.01% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 141589020 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 974677774 # Class of executed instruction -system.cpu.dcache.tags.replacements 9257096 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.942792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288320002 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9257608 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.144114 # Average number of references to valid blocks. +system.cpu.op_class::total 974218086 # Class of executed instruction +system.cpu.dcache.tags.replacements 9250712 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.942785 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 288177954 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9251224 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.150251 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.942792 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.942785 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1200023494 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1200023494 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146178724 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146178724 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 134536913 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 134536913 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 373150 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 373150 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333652 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333652 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286715 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3286715 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3569347 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3569347 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 280715637 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 280715637 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4352844000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 248500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 248500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149878281000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149878281000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149878281000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149878281000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 151011161 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 151011161 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 136506417 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 136506417 # 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number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 288998688 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 288998688 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032001 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014428 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014428 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748061 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.748061 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785082 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785082 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079601 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079601 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1199424100 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1199424100 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146113650 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146113650 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 134461846 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 134461846 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 373199 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 373199 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 333438 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 333438 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286002 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3286002 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149602152500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 150940828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 150940828 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 136430012 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 136430012 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481467 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1481467 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552465 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1552465 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3570029 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3568412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3568412 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 287370840 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 287370840 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 288852307 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 288852307 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031981 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.031981 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014426 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014426 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748088 # 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miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17168.642550 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17168.642550 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33973.984059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33973.984059 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60224.433485 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60224.433485 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15313.327611 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15313.327611 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82833.333333 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82833.333333 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22034.634085 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22034.634085 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18948.186709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18948.186709 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023647 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023647 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027362 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027362 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17167.083232 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17167.083232 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33906.482482 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33906.482482 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60158.309455 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60158.309455 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15286.789636 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15286.789636 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22015.390612 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22015.390612 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18928.327010 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18928.327010 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,154 +699,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7253164 # number of writebacks -system.cpu.dcache.writebacks::total 7253164 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23327 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 23327 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21303 # 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number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7246265 # number of writebacks +system.cpu.dcache.writebacks::total 7246265 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23319 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 23319 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21298 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21298 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67614 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 67614 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 44617 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 44617 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 44617 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 44617 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4803859 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 4803859 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1946868 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1946868 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106488 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1106488 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1219027 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1219027 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216413 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 216413 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 6750727 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6750727 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 7857215 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 7857215 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76783212500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76783212500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63978351000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 63978351000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20966645000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20966645000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72183391000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72183391000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2984919500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2984919500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 245500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 245500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140761563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 140761563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161728208500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161728208500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199745000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199745000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217608000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217608000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417353000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031846 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031846 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014272 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014272 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746859 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785082 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785082 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060717 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060717 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76693371000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 76693371000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63803384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 63803384500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20983567500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20983567500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72115576500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72115576500 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970992000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970992000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140496755500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 140496755500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161480323000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 161480323000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199653000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199653000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217623500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217623500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417276500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417276500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746887 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746887 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785220 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785220 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060619 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060619 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023502 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023502 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027209 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15966.200087 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15966.200087 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32839.707505 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32839.707505 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18954.098790 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18954.098790 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59224.433485 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59224.433485 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13766.935863 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13766.935863 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81833.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81833.333333 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20831.002673 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20831.002673 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20566.973180 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20566.973180 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183957.776987 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183957.776987 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.966180 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.966180 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184206.393710 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184206.393710 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023491 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023491 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027201 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15964.950470 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15964.950470 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32772.321750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32772.321750 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18964.116647 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.116647 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59158.309455 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59158.309455 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13728.343491 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13728.343491 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20812.092609 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20812.092609 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20551.852406 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20551.852406 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.047178 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.047178 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.426012 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.426012 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.258864 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.258864 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13398086 # number of replacements +system.cpu.icache.tags.replacements 13387387 # number of replacements system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 816025451 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13398598 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.903794 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 815635496 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13387899 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 60.923338 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 185 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 842822657 # Number of tag accesses -system.cpu.icache.tags.data_accesses 842822657 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 816025451 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 816025451 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 816025451 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 816025451 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 816025451 # number of overall hits -system.cpu.icache.overall_hits::total 816025451 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13398603 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13398603 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13398603 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13398603 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13398603 # number of overall misses -system.cpu.icache.overall_misses::total 13398603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182979269500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182979269500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182979269500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182979269500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182979269500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182979269500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 829424054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 829424054 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 829424054 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 829424054 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 829424054 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 829424054 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016154 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016154 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016154 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016154 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016154 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016154 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13656.593116 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13656.593116 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13656.593116 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13656.593116 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13656.593116 # average overall miss latency +system.cpu.icache.tags.tag_accesses 842411304 # Number of tag accesses +system.cpu.icache.tags.data_accesses 842411304 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 815635496 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 815635496 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 815635496 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 815635496 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 815635496 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182784455500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 829023400 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 829023400 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 829023400 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 829023400 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 829023400 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 829023400 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016149 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016149 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016149 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016149 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.027813 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.027813 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126219.744483 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67946.365507 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67946.365507 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121102.587946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121102.587946 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122363.271760 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122363.271760 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123109.369405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123109.369405 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120254.867813 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120254.867813 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171433.935671 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138953.636091 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.639848 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.639848 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171431.205863 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.438596 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172955.099680 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172955.099680 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172194.355437 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149322.350387 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.220590 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.658298 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 45828995 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23172776 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1754 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2709 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2709 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 45794965 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23155820 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2699 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2699 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 972528 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20504109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 972147 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20487667 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8210793 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13396481 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2163559 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 41501 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 41504 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1906703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1906703 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13398603 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6140983 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1325475 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1218811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40279937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27990886 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 853214 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69722195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1715057876 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978932526 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1952280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2493088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2698435770 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1573850 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24936909 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019271 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137475 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8203050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13387387 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2163174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 41410 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 41412 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1905461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1905461 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13387904 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6135636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1325691 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1219027 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40249445 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27971705 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598323 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 852523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69671996 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1713791124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978068334 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1954320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2489888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2696303666 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1571708 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 24917471 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019294 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.137557 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24456353 98.07% 98.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 480556 1.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24436707 98.07% 98.07% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 480764 1.93% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24936909 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43847676000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 24917471 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43812763500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1611389 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1591387 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20141029500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20124981000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12738944468 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12729124462 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 354123000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 354033000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 541578000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 541287000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40323 # Transaction distribution -system.iobus.trans_dist::ReadResp 40323 # Transaction distribution +system.iobus.trans_dist::ReadReq 40324 # Transaction distribution +system.iobus.trans_dist::ReadResp 40324 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1286,11 +1289,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1305,12 +1308,12 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42147000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1332,73 +1335,73 @@ system.iobus.reqLayer16.occupancy 16500 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25743500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25712000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 565463411 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566837671 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115483 # number of replacements -system.iocache.tags.tagsinuse 10.446937 # Cycle average of tags in use +system.iocache.tags.replacements 115484 # number of replacements +system.iocache.tags.tagsinuse 10.446945 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183709784000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511467 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935470 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219467 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433467 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13183709781000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511462 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935482 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433468 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039875 # Number of tag accesses -system.iocache.tags.data_accesses 1039875 # Number of data accesses +system.iocache.tags.tag_accesses 1039884 # Number of tag accesses +system.iocache.tags.data_accesses 1039884 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses -system.iocache.demand_misses::total 8878 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses +system.iocache.demand_misses::total 8879 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8838 # number of overall misses -system.iocache.overall_misses::total 8878 # number of overall misses +system.iocache.overall_misses::realview.ide 8839 # number of overall misses +system.iocache.overall_misses::total 8879 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1645846130 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1650916630 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1648554138 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1653624638 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13863091781 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13863091781 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13411902033 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13411902033 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1645846130 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1651267630 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1648554138 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1653975638 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1645846130 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1651267630 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1648554138 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1653975638 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1413,54 +1416,54 @@ system.iocache.overall_miss_rate::realview.ethernet 1 system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186223.821000 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186018.775211 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186509.122978 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186302.910996 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129969.734690 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 129969.734690 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.725053 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125739.725053 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 185995.452805 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 186279.495213 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186223.821000 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 185995.452805 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33963 # number of cycles access was blocked +system.iocache.overall_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 186279.495213 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32796 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3509 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3360 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.678826 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.760714 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1203946130 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1207166630 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206604138 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1209824638 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8529891781 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8529891781 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073565122 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8073565122 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1203946130 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1207367630 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1206604138 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1210025638 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1203946130 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1207367630 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1206604138 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1210025638 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1475,72 +1478,71 @@ system.iocache.overall_mshr_miss_rate::realview.ethernet 1 system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136223.821000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136018.775211 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136509.122978 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136302.910996 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79969.734690 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79969.734690 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.565308 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.565308 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136223.821000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 135995.452805 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 380834 # Transaction distribution +system.membus.trans_dist::ReadResp 380206 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 957595 # Transaction distribution -system.membus.trans_dist::CleanEvict 155985 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33274 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 33277 # Transaction distribution -system.membus.trans_dist::ReadExReq 797439 # Transaction distribution -system.membus.trans_dist::ReadExResp 797439 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 304007 # Transaction distribution +system.membus.trans_dist::WritebackDirty 956725 # Transaction distribution +system.membus.trans_dist::CleanEvict 157718 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33138 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 796168 # Transaction distribution +system.membus.trans_dist::ReadExResp 796168 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 303379 # Transaction distribution system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution -system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3343278 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3472970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 341196 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3814166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3304162 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3433854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237247 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3671101 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124537568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124707394 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7226176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7226176 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131933570 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3258 # Total snoops (count) -system.membus.snoop_fanout::samples 2468309 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124360288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124530114 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7222400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7222400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 131752514 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3318 # Total snoops (count) +system.membus.snoop_fanout::samples 2464390 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2468309 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2464390 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2468309 # Request fanout histogram -system.membus.reqLayer0.occupancy 106920500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2464390 # Request fanout histogram +system.membus.reqLayer0.occupancy 106890000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5785500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5800500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6298398949 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6292280855 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 6051404500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5974901047 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 227572547 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44724954 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |