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author | Joel Hestness <jthestness@gmail.com> | 2015-10-10 16:45:41 -0500 |
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committer | Joel Hestness <jthestness@gmail.com> | 2015-10-10 16:45:41 -0500 |
commit | 735c4a87665119a33443cf8d191d329c66191c6e (patch) | |
tree | 619a6c346beb6f7972acfa41a737b065f6c701c5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt | |
parent | 1f2e7c1aaa17e55b06504264e40bde1a000f2214 (diff) | |
download | gem5-735c4a87665119a33443cf8d191d329c66191c6e.tar.xz |
stats: Update for UDelayEvent quiesce change
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 5ecc0e3a9..b90977aa0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 51.811426 # Nu sim_ticks 51811426272500 # Number of ticks simulated final_tick 51811426272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 673469 # Simulator instruction rate (inst/s) -host_op_rate 791455 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42067688868 # Simulator tick rate (ticks/s) -host_mem_usage 720644 # Number of bytes of host memory used -host_seconds 1231.62 # Real time elapsed on the host +host_inst_rate 429786 # Simulator instruction rate (inst/s) +host_op_rate 505081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26846252166 # Simulator tick rate (ticks/s) +host_mem_usage 669952 # Number of bytes of host memory used +host_seconds 1929.93 # Real time elapsed on the host sim_insts 829457901 # Number of instructions simulated sim_ops 974772546 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -519,6 +519,8 @@ system.cpu.itb.accesses 830088208 # DT system.cpu.numCycles 103622852545 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed system.cpu.committedInsts 829457901 # Number of instructions committed system.cpu.committedOps 974772546 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 896189211 # Number of integer alu accesses @@ -576,8 +578,6 @@ system.cpu.op_class::MemWrite 141762556 14.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 975326961 # Class of executed instruction -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 18851 # number of quiesce instructions executed system.cpu.dcache.tags.replacements 9274254 # number of replacements system.cpu.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 288519025 # Total number of references to valid blocks. |