diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-24 04:16:59 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-24 04:16:59 -0500 |
| commit | 28289e5995f80ce15fdf26a61e865b30cde48af7 (patch) | |
| tree | c674350be3f0cde557c720c44285eeeec6fb806a /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing | |
| parent | 7958f34797857fecf803fa4a2fcd018a8fffb640 (diff) | |
| download | gem5-28289e5995f80ce15fdf26a61e865b30cde48af7.tar.xz | |
stats: Update stats to reflect forwarding of InvalidateReq
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt | 2275 |
1 files changed, 1138 insertions, 1137 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index f5f82f47e..3c1e4fda0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.811400 # Number of seconds simulated -sim_ticks 51811399994500 # Number of ticks simulated -final_tick 51811399994500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.759374 # Number of seconds simulated +sim_ticks 51759374264500 # Number of ticks simulated +final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 805770 # Simulator instruction rate (inst/s) -host_op_rate 946938 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50389185573 # Simulator tick rate (ticks/s) -host_mem_usage 678984 # Number of bytes of host memory used -host_seconds 1028.22 # Real time elapsed on the host -sim_insts 828512987 # Number of instructions simulated -sim_ops 973664549 # Number of ops (including micro ops) simulated +host_inst_rate 1125548 # Simulator instruction rate (inst/s) +host_op_rate 1322684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 69608471837 # Simulator tick rate (ticks/s) +host_mem_usage 675480 # Number of bytes of host memory used +host_seconds 743.58 # Real time elapsed on the host +sim_insts 836933434 # Number of instructions simulated +sim_ops 983519389 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 133568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 141952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4623732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 65034376 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 398080 # Number of bytes read from this memory -system.physmem.bytes_read::total 70331708 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4623732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4623732 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 61230400 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory +system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 61250980 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2218 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 112653 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1016175 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6220 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1139353 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 956725 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory +system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 959298 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 2740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 89242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1255214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7683 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1357456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 89242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 89242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1181794 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1182191 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1181794 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 2740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 89242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1255611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2539647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1139353 # Number of read requests accepted -system.physmem.writeReqs 959298 # Number of write requests accepted -system.physmem.readBursts 1139353 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 959298 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72868032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50560 # Total number of bytes read from write queue -system.physmem.bytesWritten 61249856 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 70331708 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 61250980 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 790 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one +system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 693427 # Number of read requests accepted +system.physmem.writeReqs 989027 # Number of write requests accepted +system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue +system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 69574 # Per bank write bursts -system.physmem.perBankRdBursts::1 73483 # Per bank write bursts -system.physmem.perBankRdBursts::2 70905 # Per bank write bursts -system.physmem.perBankRdBursts::3 67568 # Per bank write bursts -system.physmem.perBankRdBursts::4 64326 # Per bank write bursts -system.physmem.perBankRdBursts::5 70688 # Per bank write bursts -system.physmem.perBankRdBursts::6 65575 # Per bank write bursts -system.physmem.perBankRdBursts::7 64409 # Per bank write bursts -system.physmem.perBankRdBursts::8 65562 # Per bank write bursts -system.physmem.perBankRdBursts::9 110058 # Per bank write bursts -system.physmem.perBankRdBursts::10 69387 # Per bank write bursts -system.physmem.perBankRdBursts::11 70852 # Per bank write bursts -system.physmem.perBankRdBursts::12 67727 # Per bank write bursts -system.physmem.perBankRdBursts::13 71395 # Per bank write bursts -system.physmem.perBankRdBursts::14 70177 # Per bank write bursts -system.physmem.perBankRdBursts::15 66877 # Per bank write bursts -system.physmem.perBankWrBursts::0 57914 # Per bank write bursts -system.physmem.perBankWrBursts::1 61200 # Per bank write bursts -system.physmem.perBankWrBursts::2 60974 # Per bank write bursts -system.physmem.perBankWrBursts::3 59703 # Per bank write bursts -system.physmem.perBankWrBursts::4 56782 # Per bank write bursts -system.physmem.perBankWrBursts::5 61096 # Per bank write bursts -system.physmem.perBankWrBursts::6 57709 # Per bank write bursts -system.physmem.perBankWrBursts::7 57516 # Per bank write bursts -system.physmem.perBankWrBursts::8 58389 # Per bank write bursts -system.physmem.perBankWrBursts::9 61168 # Per bank write bursts -system.physmem.perBankWrBursts::10 60736 # Per bank write bursts -system.physmem.perBankWrBursts::11 62143 # Per bank write bursts -system.physmem.perBankWrBursts::12 59319 # Per bank write bursts -system.physmem.perBankWrBursts::13 62705 # Per bank write bursts -system.physmem.perBankWrBursts::14 61087 # Per bank write bursts -system.physmem.perBankWrBursts::15 58588 # Per bank write bursts +system.physmem.perBankRdBursts::0 40853 # Per bank write bursts +system.physmem.perBankRdBursts::1 42497 # Per bank write bursts +system.physmem.perBankRdBursts::2 39380 # Per bank write bursts +system.physmem.perBankRdBursts::3 40815 # Per bank write bursts +system.physmem.perBankRdBursts::4 36874 # Per bank write bursts +system.physmem.perBankRdBursts::5 45606 # Per bank write bursts +system.physmem.perBankRdBursts::6 38207 # Per bank write bursts +system.physmem.perBankRdBursts::7 36804 # Per bank write bursts +system.physmem.perBankRdBursts::8 38817 # Per bank write bursts +system.physmem.perBankRdBursts::9 83381 # Per bank write bursts +system.physmem.perBankRdBursts::10 47849 # Per bank write bursts +system.physmem.perBankRdBursts::11 45678 # Per bank write bursts +system.physmem.perBankRdBursts::12 39735 # Per bank write bursts +system.physmem.perBankRdBursts::13 40223 # Per bank write bursts +system.physmem.perBankRdBursts::14 37028 # Per bank write bursts +system.physmem.perBankRdBursts::15 38885 # Per bank write bursts +system.physmem.perBankWrBursts::0 61132 # Per bank write bursts +system.physmem.perBankWrBursts::1 62574 # Per bank write bursts +system.physmem.perBankWrBursts::2 60681 # Per bank write bursts +system.physmem.perBankWrBursts::3 62576 # Per bank write bursts +system.physmem.perBankWrBursts::4 57559 # Per bank write bursts +system.physmem.perBankWrBursts::5 64093 # Per bank write bursts +system.physmem.perBankWrBursts::6 59756 # Per bank write bursts +system.physmem.perBankWrBursts::7 59796 # Per bank write bursts +system.physmem.perBankWrBursts::8 61252 # Per bank write bursts +system.physmem.perBankWrBursts::9 63246 # Per bank write bursts +system.physmem.perBankWrBursts::10 66784 # Per bank write bursts +system.physmem.perBankWrBursts::11 64593 # Per bank write bursts +system.physmem.perBankWrBursts::12 60371 # Per bank write bursts +system.physmem.perBankWrBursts::13 61779 # Per bank write bursts +system.physmem.perBankWrBursts::14 59591 # Per bank write bursts +system.physmem.perBankWrBursts::15 60974 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 61 # Number of times write queue was full causing retry -system.physmem.totGap 51811397057500 # Total gap between requests +system.physmem.numWrRetry 25 # Number of times write queue was full causing retry +system.physmem.totGap 51759371327500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1096237 # Read request sizes (log2) +system.physmem.readPktSize::6 650311 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 956725 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1111594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 21338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 330 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 485 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 111 # What read queue length does an incoming req see +system.physmem.writePktSize::6 986454 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,166 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 56112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 55236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 55847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 56596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 57293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 56619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 58037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 57181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 56145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 56000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 794 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 160 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 450226 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.889433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 171.979745 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.177331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 179632 39.90% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 110318 24.50% 64.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39188 8.70% 73.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 22734 5.05% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15887 3.53% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11846 2.63% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9963 2.21% 86.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8722 1.94% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 51936 11.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 450226 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 53627 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.230425 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 337.691151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 53625 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::20480-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 53627 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 53627 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.846029 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.135395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.325860 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51578 96.18% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 290 0.54% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 64 0.12% 96.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 105 0.20% 97.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 36 0.07% 97.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 101 0.19% 97.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 231 0.43% 97.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 25 0.05% 97.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 324 0.60% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 70 0.13% 98.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 27 0.05% 98.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 55 0.10% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 281 0.52% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 24 0.04% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 27 0.05% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 150 0.28% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 183 0.34% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 16 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 53627 # Writes before turning the bus around for reads -system.physmem.totQLat 14356871098 # Total ticks spent queuing -system.physmem.totMemAccLat 35704927348 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5692815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12609.64 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads +system.physmem.totQLat 9243736951 # Total ticks spent queuing +system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31359.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.12 # Average write queue length when enqueuing -system.physmem.readRowHits 917761 # Number of row buffer hits during reads -system.physmem.writeRowHits 727604 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.03 # Row buffer hit rate for writes -system.physmem.avgGap 24687952.91 # Average gap between requests -system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1698338880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 926673000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4262879400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3064353120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1294076187855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951683866750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34639780896525 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.574535 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49826749097915 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730096420000 # Time in different power states +system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing +system.physmem.readRowHits 510166 # Number of row buffer hits during reads +system.physmem.writeRowHits 727396 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes +system.physmem.avgGap 30764211.88 # Average gap between requests +system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.514508 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 254553819585 # Time in different power states +system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1705369680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 930509250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4617873000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3137194800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384068597520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1296366805530 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29949674553000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34640500902780 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.588432 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49823352477739 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730096420000 # Time in different power states +system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.532817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 257948478511 # Time in different power states +system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -372,70 +371,71 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 185086 # Table walker walks requested -system.cpu.dtb.walker.walksLong 185086 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12788 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 144037 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 15 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 185071 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.216133 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.811526 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 185069 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 187211 # Table walker walks requested +system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 185071 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 156840 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24753.656593 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20840.255945 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 17740.873102 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 155696 99.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.27% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 981 0.63% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 68 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 23 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 36 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 156840 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -374556148 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 5.053125 # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1518122704 -405.31% -405.31% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -1892678852 505.31% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -374556148 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 144038 91.85% 91.85% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12788 8.15% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 156826 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 185086 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 185086 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 156826 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 156826 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 341912 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 156026006 # DTB read hits -system.cpu.dtb.read_misses 137641 # DTB read misses -system.cpu.dtb.write_hits 141600690 # DTB write hits -system.cpu.dtb.write_misses 47445 # DTB write misses +system.cpu.dtb.read_hits 157500215 # DTB read hits +system.cpu.dtb.read_misses 138721 # DTB read misses +system.cpu.dtb.write_hits 142992331 # DTB write hits +system.cpu.dtb.write_misses 48490 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70612 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 71001 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6537 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 18565 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 156163647 # DTB read accesses -system.cpu.dtb.write_accesses 141648135 # DTB write accesses +system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 157638936 # DTB read accesses +system.cpu.dtb.write_accesses 143040821 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 297626696 # DTB hits -system.cpu.dtb.misses 185086 # DTB misses -system.cpu.dtb.accesses 297811782 # DTB accesses +system.cpu.dtb.hits 300492546 # DTB hits +system.cpu.dtb.misses 187211 # DTB misses +system.cpu.dtb.accesses 300679757 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -465,232 +465,234 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 118473 # Table walker walks requested -system.cpu.itb.walker.walksLong 118473 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1110 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107045 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 118473 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 118473 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 118473 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 108155 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28668.184550 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24838.617630 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 20892.143337 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 106773 98.72% 98.72% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1223 1.13% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 21 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 63 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 24 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 37 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 108155 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 119486 # Table walker walks requested +system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107045 98.97% 98.97% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1110 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 108155 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 118473 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 118473 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108155 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 108155 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 226628 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 829023400 # ITB inst hits -system.cpu.itb.inst_misses 118473 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 837449249 # ITB inst hits +system.cpu.itb.inst_misses 119486 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 37806 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 999 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50418 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 50677 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 829141873 # ITB inst accesses -system.cpu.itb.hits 829023400 # DTB hits -system.cpu.itb.misses 118473 # DTB misses -system.cpu.itb.accesses 829141873 # DTB accesses -system.cpu.numCycles 103622799989 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 837568735 # ITB inst accesses +system.cpu.itb.hits 837449249 # DTB hits +system.cpu.itb.misses 119486 # DTB misses +system.cpu.itb.accesses 837568735 # DTB accesses +system.cpu.numCycles 103518748529 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 15972 # number of quiesce instructions executed -system.cpu.committedInsts 828512987 # Number of instructions committed -system.cpu.committedOps 973664549 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 895161313 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 899443 # Number of float alu accesses -system.cpu.num_func_calls 49782138 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 125600972 # number of instructions that are conditional controls -system.cpu.num_int_insts 895161313 # number of integer instructions -system.cpu.num_fp_insts 899443 # number of float instructions -system.cpu.num_int_register_reads 1295047006 # number of times the integer registers were read -system.cpu.num_int_register_writes 709396185 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1452745 # number of times the floating registers were read -system.cpu.num_fp_register_writes 757712 # number of times the floating registers were written -system.cpu.num_cc_register_reads 214441530 # number of times the CC registers were read -system.cpu.num_cc_register_writes 213833710 # number of times the CC registers were written -system.cpu.num_mem_refs 297604519 # number of memory refs -system.cpu.num_load_insts 156015499 # Number of load instructions -system.cpu.num_store_insts 141589020 # Number of store instructions -system.cpu.num_idle_cycles 100541051528.316055 # Number of idle cycles -system.cpu.num_busy_cycles 3081748460.683940 # Number of busy cycles -system.cpu.not_idle_fraction 0.029740 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970260 # Percentage of idle cycles -system.cpu.Branches 184855625 # Number of branches fetched +system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed +system.cpu.committedInsts 836933434 # Number of instructions committed +system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses +system.cpu.num_func_calls 50188688 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls +system.cpu.num_int_insts 904020212 # number of integer instructions +system.cpu.num_fp_insts 901230 # number of float instructions +system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read +system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written +system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read +system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written +system.cpu.num_mem_refs 300471292 # number of memory refs +system.cpu.num_load_insts 157490392 # Number of load instructions +system.cpu.num_store_insts 142980900 # Number of store instructions +system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles +system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970405 # Percentage of idle cycles +system.cpu.Branches 186768786 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 674284702 69.21% 69.21% # Class of executed instruction -system.cpu.op_class::IntMult 2119126 0.22% 69.43% # Class of executed instruction -system.cpu.op_class::IntDiv 97314 0.01% 69.44% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 8 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 13 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 21 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 112382 0.01% 69.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu.op_class::MemRead 156015499 16.01% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 141589020 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction +system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction +system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 974218086 # Class of executed instruction -system.cpu.dcache.tags.replacements 9250712 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.942785 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 288177954 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9251224 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.150251 # Average number of references to valid blocks. +system.cpu.op_class::total 984078328 # Class of executed instruction +system.cpu.dcache.tags.replacements 9381962 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.942785 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1199424100 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1199424100 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146113650 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146113650 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 134461846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 134461846 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 373199 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 373199 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 333438 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 333438 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3286002 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3286002 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3568410 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3568410 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 280575496 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 280575496 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 280948695 # number of overall hits -system.cpu.dcache.overall_hits::total 280948695 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4827178 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4827178 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1968166 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1968166 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1108268 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1108268 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1219027 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1219027 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 284027 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 284027 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 6795344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 6795344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7903612 # number of overall misses -system.cpu.dcache.overall_misses::total 7903612 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 82868566500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 82868566500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 66733586000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 66733586000 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 73334603500 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 73334603500 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4341861000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4341861000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149602152500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149602152500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 149602152500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 149602152500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 150940828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 150940828 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 136430012 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 136430012 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1481467 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1481467 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1552465 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1552465 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3570029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3570029 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3568412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3568412 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 287370840 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 287370840 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 288852307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 288852307 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031981 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.031981 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014426 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014426 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.748088 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.748088 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785220 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785220 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079559 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023647 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023647 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.027362 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.027362 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17167.083232 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17167.083232 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33906.482482 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33906.482482 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 60158.309455 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 60158.309455 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15286.789636 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15286.789636 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22015.390612 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22015.390612 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18928.327010 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18928.327010 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 283201595 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 283201595 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 283575709 # number of overall hits +system.cpu.dcache.overall_hits::total 283575709 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 6893121 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 6893121 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8029572 # number of overall misses +system.cpu.dcache.overall_misses::total 8029572 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 154677984000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 154677984000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 154677984000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 154677984000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 290094716 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 290094716 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 291605281 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 291605281 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023762 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023762 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.027536 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.027536 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22439.470307 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22439.470307 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19263.540323 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19263.540323 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -699,154 +701,154 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7246265 # number of writebacks -system.cpu.dcache.writebacks::total 7246265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 23319 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 23319 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21298 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21298 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 67614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 67614 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 44617 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 44617 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 44617 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 44617 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4803859 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4803859 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1946868 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1946868 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1106488 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1106488 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1219027 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1219027 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 216413 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 216413 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 6750727 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 6750727 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 7857215 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 7857215 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks +system.cpu.dcache.writebacks::total 7313678 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 6849886 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 6849886 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 7984572 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 7984572 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 76693371000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 76693371000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 63803384500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 63803384500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20983567500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20983567500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 72115576500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 72115576500 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2970992000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2970992000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 163500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 140496755500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 140496755500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161480323000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161480323000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199653000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199653000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217623500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217623500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417276500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417276500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031826 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014270 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014270 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.746887 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.746887 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785220 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785220 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060619 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060619 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023491 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.023491 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027201 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027201 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15964.950470 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15964.950470 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32772.321750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32772.321750 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18964.116647 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.116647 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 59158.309455 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 59158.309455 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13728.343491 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13728.343491 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20812.092609 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20812.092609 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20551.852406 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20551.852406 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.047178 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.047178 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184455.426012 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184455.426012 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.258864 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.258864 # average overall mshr uncacheable latency +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145533577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 145533577500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 166975219500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 166975219500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6217603000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6217603000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12417284500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 12417284500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023613 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.023613 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027381 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027381 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21246.131322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21246.131322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20912.231676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20912.231676 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184454.817847 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184454.817847 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184205.377540 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184205.377540 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13387387 # number of replacements -system.cpu.icache.tags.tagsinuse 511.782420 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 815635496 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13387899 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 60.923338 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 61704805500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.782420 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999575 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999575 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13331164 # number of replacements +system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 842411304 # Number of tag accesses -system.cpu.icache.tags.data_accesses 842411304 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 815635496 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 815635496 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 815635496 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 815635496 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 815635496 # number of overall hits -system.cpu.icache.overall_hits::total 815635496 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # 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number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 169396551500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 169396551500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 169396551500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 169396551500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 169396551500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 169396551500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016149 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016149 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016149 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016149 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12652.955347 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12652.955347 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12652.955347 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12652.955347 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 999968 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65207.127423 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 41555308 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1062213 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 39.121446 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.281611 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994982 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 61992 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5510 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53605 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003860 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945923 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 371220882 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 371220882 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 309149 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242072 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 551221 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7246265 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7246265 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13385787 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13385787 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 8844 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 8844 # 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number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16505276000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.166206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.166206 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005196 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036011 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036011 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.393790 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.393790 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.027813 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006706 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009079 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005196 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.066897 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.027813 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126219.744483 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67946.365507 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67946.365507 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121102.587946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121102.587946 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122363.271760 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122363.271760 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123109.369405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123109.369405 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 120254.867813 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 120254.867813 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 125901.054145 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126519.612263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122363.271760 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 121926.589148 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122006.529756 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171431.205863 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.438596 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172955.099680 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172955.099680 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172954.491515 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172954.491515 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.220590 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.658298 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172193.317015 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149321.717103 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 45794965 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23155820 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2699 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2699 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 972147 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20487667 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8203050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13387387 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2163174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 41410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 41412 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1905461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1905461 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13387904 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6135636 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1325691 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1219027 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40249445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27971705 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 598323 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 852523 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69671996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1713791124 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 978068334 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1954320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2489888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2696303666 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1571708 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 24917471 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019294 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.137557 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24436707 98.07% 98.07% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 480764 1.93% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 24917471 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43812763500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1591387 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20124981000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12729124462 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 354033000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 541287000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40324 # Transaction distribution -system.iobus.trans_dist::ReadResp 40324 # Transaction distribution +system.iobus.trans_dist::ReadReq 40345 # Transaction distribution +system.iobus.trans_dist::ReadResp 40345 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1289,11 +1290,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353790 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1308,20 +1309,20 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42148500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1331,77 +1332,77 @@ system.iobus.reqLayer14.occupancy 11000 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25712000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566837671 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147766000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.446945 # Cycle average of tags in use +system.iocache.tags.replacements 115506 # number of replacements +system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13183709781000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511462 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935482 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219466 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433468 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652934 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.tags.tag_accesses 1040073 # Number of tag accesses +system.iocache.tags.data_accesses 1040073 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses -system.iocache.demand_misses::total 8879 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8860 # number of demand (read+write) misses +system.iocache.demand_misses::total 8900 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8839 # number of overall misses -system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1648554138 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1653624638 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8860 # number of overall misses +system.iocache.overall_misses::total 8900 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411902033 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411902033 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1648554138 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1653975638 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1648554138 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1653975638 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1628892126 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1634313126 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1628892126 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1634313126 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8860 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8900 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8860 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8900 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1415,55 +1416,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186509.122978 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186302.910996 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125739.725053 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125739.725053 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 186279.495213 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 186509.122978 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 186279.495213 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32796 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183630.688315 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183847.869752 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183630.688315 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3360 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.760714 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8860 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8900 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1206604138 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1209824638 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8860 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8900 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073565122 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073565122 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1206604138 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1210025638 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1206604138 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1210025638 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1185892126 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1189313126 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1185892126 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1189313126 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1477,72 +1478,72 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136509.122978 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 136302.910996 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.565308 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.565308 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 136509.122978 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 136279.495213 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 133847.869752 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 133630.688315 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 380206 # Transaction distribution +system.membus.trans_dist::ReadResp 389416 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 956725 # Transaction distribution -system.membus.trans_dist::CleanEvict 157718 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33138 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 796168 # Transaction distribution -system.membus.trans_dist::ReadExResp 796168 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 303379 # Transaction distribution -system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution +system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution +system.membus.trans_dist::CleanEvict 164302 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 7 # Transaction distribution +system.membus.trans_dist::ReadExReq 341030 # Transaction distribution +system.membus.trans_dist::ReadExResp 341030 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution +system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3304162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3433854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237247 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3671101 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 124360288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 124530114 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7222400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7222400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 131752514 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3318 # Total snoops (count) -system.membus.snoop_fanout::samples 2464390 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3315 # Total snoops (count) +system.membus.snoop_fanout::samples 2537144 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2464390 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2464390 # Request fanout histogram -system.membus.reqLayer0.occupancy 106890000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2537144 # Request fanout histogram +system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5800500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6292280855 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5974901047 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44724954 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |