diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing')
5 files changed, 1533 insertions, 1269 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini index 27116f25e..ebadfb41e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/config.ini @@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm64 +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64 boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -40,12 +42,18 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -58,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -86,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img read_only=true [system.clk_domain] @@ -104,6 +117,7 @@ branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 +default_p_state=UNDEFINED do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -121,6 +135,10 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 simpoint_start_insts= @@ -139,13 +157,17 @@ addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -164,8 +186,13 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -188,9 +215,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker [system.cpu.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.dtb] @@ -204,9 +236,14 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[3] @@ -217,13 +254,17 @@ addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -242,8 +283,13 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -301,9 +347,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker [system.cpu.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu.itb] @@ -317,9 +368,14 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu.toL2Bus.slave[2] @@ -330,13 +386,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -355,8 +415,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -364,9 +429,15 @@ size=4194304 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu.toL2Bus.snoop_filter snoop_response_latency=1 @@ -411,9 +482,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -427,13 +503,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -452,8 +532,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -461,9 +546,15 @@ size=1024 type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -477,11 +568,16 @@ slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side s [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -526,6 +622,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -537,7 +634,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -580,10 +681,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -664,14 +770,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -680,13 +791,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -696,6 +812,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -766,10 +883,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -849,17 +971,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -885,12 +1012,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -898,14 +1031,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -991,14 +1129,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -1007,13 +1150,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -1022,13 +1170,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -1036,11 +1189,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1054,11 +1212,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1072,19 +1235,25 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1130,14 +1299,29 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -1146,11 +1330,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -1160,21 +1349,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=12 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=788529152 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -1184,12 +1383,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -1198,10 +1402,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -1211,12 +1420,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -1226,26 +1440,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -1254,10 +1478,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -1265,10 +1494,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -1276,21 +1510,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1304,11 +1548,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -1319,11 +1568,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -1331,10 +1585,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr index 3c2cf37c0..082803b1b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simerr @@ -3,6 +3,7 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout index 9326fddff..ad2b5e63e 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 14:13:19 -gem5 executing on e104799-lin, pid 14780 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 15:07:38 +gem5 executing on e108600-lin, pid 24412 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-simple-timing Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80080000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 51811415265500 because m5_exit instruction encountered +Exiting @ tick 51759347706500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 04a520211..89d0e34be 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.759374 # Number of seconds simulated -sim_ticks 51759374264500 # Number of ticks simulated -final_tick 51759374264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.759348 # Number of seconds simulated +sim_ticks 51759347706500 # Number of ticks simulated +final_tick 51759347706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622194 # Simulator instruction rate (inst/s) -host_op_rate 731170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38479042536 # Simulator tick rate (ticks/s) -host_mem_usage 677104 # Number of bytes of host memory used -host_seconds 1345.13 # Real time elapsed on the host -sim_insts 836933434 # Number of instructions simulated -sim_ops 983519389 # Number of ops (including micro ops) simulated +host_inst_rate 706961 # Simulator instruction rate (inst/s) +host_op_rate 830795 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43773319280 # Simulator tick rate (ticks/s) +host_mem_usage 670816 # Number of bytes of host memory used +host_seconds 1182.44 # Real time elapsed on the host +sim_insts 835939132 # Number of instructions simulated +sim_ops 982366087 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.dtb.walker 155264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 159360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 4743732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 36334600 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 399488 # Number of bytes read from this memory -system.physmem.bytes_read::total 41792444 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 4743732 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4743732 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 63133056 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.dtb.walker 152192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 158144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 4715828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 36073224 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 410496 # Number of bytes read from this memory +system.physmem.bytes_read::total 41509884 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 4715828 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4715828 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 62909632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 63153636 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 2426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2490 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 114528 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 567741 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6242 # Number of read requests responded to by this memory -system.physmem.num_reads::total 693427 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 986454 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 62930212 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 2378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 114092 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 563657 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6414 # Number of read requests responded to by this memory +system.physmem.num_reads::total 689012 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 982963 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 989027 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 3000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 3079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 91650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 701991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 807437 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 91650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1219741 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 985536 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3055 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 91111 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 696941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 801978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 91111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 91111 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1215426 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1220139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1219741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 3000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 3079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 91650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 702388 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2027576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 693427 # Number of read requests accepted -system.physmem.writeReqs 989027 # Number of write requests accepted -system.physmem.readBursts 693427 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 989027 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 44328448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 50880 # Total number of bytes read from write queue -system.physmem.bytesWritten 63152448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 41792444 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 63153636 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 795 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2250 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1215823 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1215426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 91111 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 697339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2017802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 689012 # Number of read requests accepted +system.physmem.writeReqs 985536 # Number of write requests accepted +system.physmem.readBursts 689012 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 985536 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 44056384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 40384 # Total number of bytes read from write queue +system.physmem.bytesWritten 62928960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41509884 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 62930212 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 631 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 40853 # Per bank write bursts -system.physmem.perBankRdBursts::1 42497 # Per bank write bursts -system.physmem.perBankRdBursts::2 39380 # Per bank write bursts -system.physmem.perBankRdBursts::3 40815 # Per bank write bursts -system.physmem.perBankRdBursts::4 36874 # Per bank write bursts -system.physmem.perBankRdBursts::5 45606 # Per bank write bursts -system.physmem.perBankRdBursts::6 38207 # Per bank write bursts -system.physmem.perBankRdBursts::7 36804 # Per bank write bursts -system.physmem.perBankRdBursts::8 38817 # Per bank write bursts -system.physmem.perBankRdBursts::9 83381 # Per bank write bursts -system.physmem.perBankRdBursts::10 47849 # Per bank write bursts -system.physmem.perBankRdBursts::11 45678 # Per bank write bursts -system.physmem.perBankRdBursts::12 39735 # Per bank write bursts -system.physmem.perBankRdBursts::13 40223 # Per bank write bursts -system.physmem.perBankRdBursts::14 37028 # Per bank write bursts -system.physmem.perBankRdBursts::15 38885 # Per bank write bursts -system.physmem.perBankWrBursts::0 61132 # Per bank write bursts -system.physmem.perBankWrBursts::1 62574 # Per bank write bursts -system.physmem.perBankWrBursts::2 60681 # Per bank write bursts -system.physmem.perBankWrBursts::3 62576 # Per bank write bursts -system.physmem.perBankWrBursts::4 57559 # Per bank write bursts -system.physmem.perBankWrBursts::5 64093 # Per bank write bursts -system.physmem.perBankWrBursts::6 59756 # Per bank write bursts -system.physmem.perBankWrBursts::7 59796 # Per bank write bursts -system.physmem.perBankWrBursts::8 61252 # Per bank write bursts -system.physmem.perBankWrBursts::9 63246 # Per bank write bursts -system.physmem.perBankWrBursts::10 66784 # Per bank write bursts -system.physmem.perBankWrBursts::11 64593 # Per bank write bursts -system.physmem.perBankWrBursts::12 60371 # Per bank write bursts -system.physmem.perBankWrBursts::13 61779 # Per bank write bursts -system.physmem.perBankWrBursts::14 59591 # Per bank write bursts -system.physmem.perBankWrBursts::15 60974 # Per bank write bursts +system.physmem.perBankRdBursts::0 41424 # Per bank write bursts +system.physmem.perBankRdBursts::1 42196 # Per bank write bursts +system.physmem.perBankRdBursts::2 39305 # Per bank write bursts +system.physmem.perBankRdBursts::3 41228 # Per bank write bursts +system.physmem.perBankRdBursts::4 37796 # Per bank write bursts +system.physmem.perBankRdBursts::5 46284 # Per bank write bursts +system.physmem.perBankRdBursts::6 37646 # Per bank write bursts +system.physmem.perBankRdBursts::7 36984 # Per bank write bursts +system.physmem.perBankRdBursts::8 37874 # Per bank write bursts +system.physmem.perBankRdBursts::9 85067 # Per bank write bursts +system.physmem.perBankRdBursts::10 43899 # Per bank write bursts +system.physmem.perBankRdBursts::11 46232 # Per bank write bursts +system.physmem.perBankRdBursts::12 39321 # Per bank write bursts +system.physmem.perBankRdBursts::13 40035 # Per bank write bursts +system.physmem.perBankRdBursts::14 35465 # Per bank write bursts +system.physmem.perBankRdBursts::15 37625 # Per bank write bursts +system.physmem.perBankWrBursts::0 61899 # Per bank write bursts +system.physmem.perBankWrBursts::1 62487 # Per bank write bursts +system.physmem.perBankWrBursts::2 61087 # Per bank write bursts +system.physmem.perBankWrBursts::3 63695 # Per bank write bursts +system.physmem.perBankWrBursts::4 58991 # Per bank write bursts +system.physmem.perBankWrBursts::5 64628 # Per bank write bursts +system.physmem.perBankWrBursts::6 58592 # Per bank write bursts +system.physmem.perBankWrBursts::7 59025 # Per bank write bursts +system.physmem.perBankWrBursts::8 60354 # Per bank write bursts +system.physmem.perBankWrBursts::9 64900 # Per bank write bursts +system.physmem.perBankWrBursts::10 63044 # Per bank write bursts +system.physmem.perBankWrBursts::11 64791 # Per bank write bursts +system.physmem.perBankWrBursts::12 60176 # Per bank write bursts +system.physmem.perBankWrBursts::13 61598 # Per bank write bursts +system.physmem.perBankWrBursts::14 57895 # Per bank write bursts +system.physmem.perBankWrBursts::15 60103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 25 # Number of times write queue was full causing retry -system.physmem.totGap 51759371327500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 51759344769500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 650311 # Read request sizes (log2) +system.physmem.readPktSize::6 645896 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 986454 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 663933 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 23086 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 455 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 539 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 340 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 163 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 982963 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 659454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 23139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -160,167 +160,168 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32057 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 54666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 57679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 55454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 58825 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 55973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 56654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 56029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 57159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 59457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 57206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 57286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 59007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 55988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 54822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 54598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 31865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 37580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 54935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 54491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 55206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 58598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 55686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 56443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 55845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 56872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 59532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 57169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 57139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 58902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 55823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 54603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 54399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 304 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 207 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 220 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 441826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.264489 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.730249 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 285.608942 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 196692 44.52% 44.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 117501 26.59% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 39119 8.85% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20402 4.62% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13280 3.01% 87.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8813 1.99% 89.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7349 1.66% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5826 1.32% 92.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32844 7.43% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 441826 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 52334 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.234628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.708770 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 52332 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 47 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 438828 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 243.797169 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.013209 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 285.979705 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 194919 44.42% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 116778 26.61% 71.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 38832 8.85% 79.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20430 4.66% 84.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13130 2.99% 87.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8793 2.00% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7414 1.69% 91.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5819 1.33% 92.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 32713 7.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 438828 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 52143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.201312 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 141.003763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 52140 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 52334 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 52334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.854989 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.140951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.267205 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 48626 92.91% 92.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 1874 3.58% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 113 0.22% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 103 0.20% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 52 0.10% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 95 0.18% 97.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 242 0.46% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 26 0.05% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 308 0.59% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 80 0.15% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 37 0.07% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 50 0.10% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 303 0.58% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 32 0.06% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 32 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 137 0.26% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 171 0.33% 99.90% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 52143 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 52143 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.857085 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.140227 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.284435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 48446 92.91% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 1855 3.56% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 116 0.22% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 101 0.19% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 48 0.09% 96.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 101 0.19% 97.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 252 0.48% 97.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.05% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 307 0.59% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 75 0.14% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 29 0.06% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 51 0.10% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 313 0.60% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 41 0.08% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 37 0.07% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 129 0.25% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 166 0.32% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::84-87 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-115 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 10 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 15 0.03% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 52334 # Writes before turning the bus around for reads -system.physmem.totQLat 9243736951 # Total ticks spent queuing -system.physmem.totMemAccLat 22230586951 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3463160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13345.81 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::176-179 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 52143 # Writes before turning the bus around for reads +system.physmem.totQLat 9222624910 # Total ticks spent queuing +system.physmem.totMemAccLat 22129768660 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3441905000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13397.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32095.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 32147.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.22 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.31 # Average write queue length when enqueuing -system.physmem.readRowHits 510166 # Number of row buffer hits during reads -system.physmem.writeRowHits 727396 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.71 # Row buffer hit rate for writes -system.physmem.avgGap 30764211.88 # Average gap between requests -system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1653765120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 902352000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2504080800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3163322160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1281472530255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29931523073250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34601889523185 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.514508 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49793449587940 # Time in different power states -system.physmem_0.memoryStateTime::REF 1728359100000 # Time in different power states +system.physmem.avgWrQLen 25.01 # Average write queue length when enqueuing +system.physmem.readRowHits 507228 # Number of row buffer hits during reads +system.physmem.writeRowHits 725589 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.79 # Row buffer hit rate for writes +system.physmem.avgGap 30909442.29 # Average gap between requests +system.physmem.pageHitRate 73.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1651557600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 901147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2518331400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3177817920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1280908967265 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29932003411500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34601830107105 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.513662 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49794254360042 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728358320000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 237560965810 # Time in different power states +system.physmem_0.memoryStateTime::ACT 236733614958 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1686439440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 920180250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2898409800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3230863200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3380670399600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1285016955840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29928413928000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34602837176130 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.532817 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49788231100713 # Time in different power states -system.physmem_1.memoryStateTime::REF 1728359100000 # Time in different power states +system.physmem_1.actEnergy 1665982080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 909018000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2851001400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3193739280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3380668873920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1282600048680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29930520006750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34602408670110 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.524840 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49791748874504 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728358320000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 242783406787 # Time in different power states +system.physmem_1.memoryStateTime::ACT 239239854996 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -337,9 +338,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -347,7 +348,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -377,73 +378,72 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 187211 # Table walker walks requested -system.cpu.dtb.walker.walksLong 187211 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 12337 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 146092 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 187194 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.213682 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 70.408839 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 187192 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.walks 186389 # Table walker walks requested +system.cpu.dtb.walker.walksLong 186389 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 11673 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 145933 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 186369 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.214628 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 70.564506 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 186367 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 187194 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 158446 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 24872.701110 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 20850.948689 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 18486.762457 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 157188 99.21% 99.21% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 4 0.00% 99.21% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 1079 0.68% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 28 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 66 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 21 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 47 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 158446 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -5153633892 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 1.304072 # Table walker pending requests distribution +system.cpu.dtb.walker.walkWaitTime::total 186369 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 157626 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24833.263548 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20845.971920 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 18169.669952 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 156391 99.22% 99.22% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 99.22% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 1058 0.67% 99.89% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 24 0.02% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 78 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 18 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 45 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 157626 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -5176298892 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 1.304609 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 1567075704 -30.41% -30.41% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 -6720709596 130.41% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -5153633892 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 146093 92.21% 92.21% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 12337 7.79% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 158430 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 187211 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walksPending::0 1576748204 -30.46% -30.46% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 -6753047096 130.46% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -5176298892 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 145934 92.59% 92.59% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 11673 7.41% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 157607 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 186389 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 187211 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 158430 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 186389 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 157607 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 158430 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 345641 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 157607 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 343996 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 157500215 # DTB read hits -system.cpu.dtb.read_misses 138721 # DTB read misses -system.cpu.dtb.write_hits 142992331 # DTB write hits -system.cpu.dtb.write_misses 48490 # DTB write misses +system.cpu.dtb.read_hits 157302470 # DTB read hits +system.cpu.dtb.read_misses 138254 # DTB read misses +system.cpu.dtb.write_hits 142797891 # DTB write hits +system.cpu.dtb.write_misses 48135 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 70937 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 71109 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 6932 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 6989 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 18784 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 157638936 # DTB read accesses -system.cpu.dtb.write_accesses 143040821 # DTB write accesses +system.cpu.dtb.read_accesses 157440724 # DTB read accesses +system.cpu.dtb.write_accesses 142846026 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 300492546 # DTB hits -system.cpu.dtb.misses 187211 # DTB misses -system.cpu.dtb.accesses 300679757 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.hits 300100361 # DTB hits +system.cpu.dtb.misses 186389 # DTB misses +system.cpu.dtb.accesses 300286750 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -473,68 +473,67 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 119486 # Table walker walks requested -system.cpu.itb.walker.walksLong 119486 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.walks 119383 # Table walker walks requested +system.cpu.itb.walker.walksLong 119383 # Table walker walks initiated with long descriptors system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 107916 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 119486 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 119486 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 119486 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 109038 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 28670.651516 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 24724.680347 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 21871.977834 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 107545 98.63% 98.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 98.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 1290 1.18% 99.82% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 34 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 71 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 41 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 42 0.04% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 109038 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksLongTerminationLevel::Level3 107813 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 119383 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 119383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 119383 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 108935 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 28686.574563 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 24766.127594 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 21816.949759 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 107446 98.63% 98.63% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 3 0.00% 98.64% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 1285 1.18% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 37 0.03% 99.85% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 72 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 42 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 32 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 108935 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 1449611704 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 1449611704 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 1449611704 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 107916 98.97% 98.97% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 107813 98.97% 98.97% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::2M 1122 1.03% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 109038 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 108935 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119486 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 119486 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 119383 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 119383 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109038 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 109038 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 228524 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 837449249 # ITB inst hits -system.cpu.itb.inst_misses 119486 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 108935 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 108935 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 228318 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 836454912 # ITB inst hits +system.cpu.itb.inst_misses 119383 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 38511 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 38509 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1009 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 50613 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 50925 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 837568735 # ITB inst accesses -system.cpu.itb.hits 837449249 # DTB hits -system.cpu.itb.misses 119486 # DTB misses -system.cpu.itb.accesses 837568735 # DTB accesses +system.cpu.itb.inst_accesses 836574295 # ITB inst accesses +system.cpu.itb.hits 836454912 # DTB hits +system.cpu.itb.misses 119383 # DTB misses +system.cpu.itb.accesses 836574295 # DTB accesses system.cpu.numPwrStateTransitions 32056 # Number of power state transitions system.cpu.pwrStateClkGateDist::samples 16028 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::mean 3133737148.696906 # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::stdev 60742072610.602715 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::mean 3133878336.314075 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::stdev 60741761061.559830 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::underflows 6738 42.04% 42.04% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::1000-5e+10 9255 57.74% 99.78% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state @@ -547,42 +546,42 @@ system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state -system.cpu.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state +system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state system.cpu.pwrStateClkGateDist::total 16028 # Distribution of time spent in the clock gated state -system.cpu.pwrStateResidencyTicks::ON 1531835245186 # Cumulative time (in ticks) in various power states -system.cpu.pwrStateResidencyTicks::CLK_GATED 50227539019314 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 103518748529 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1529545732058 # Cumulative time (in ticks) in various power states +system.cpu.pwrStateResidencyTicks::CLK_GATED 50229801974442 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 103518695413 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16028 # number of quiesce instructions executed -system.cpu.committedInsts 836933434 # Number of instructions committed -system.cpu.committedOps 983519389 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 904020212 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 901230 # Number of float alu accesses -system.cpu.num_func_calls 50188688 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 127012937 # number of instructions that are conditional controls -system.cpu.num_int_insts 904020212 # number of integer instructions -system.cpu.num_fp_insts 901230 # number of float instructions -system.cpu.num_int_register_reads 1309570840 # number of times the integer registers were read -system.cpu.num_int_register_writes 716549182 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1454726 # number of times the floating registers were read -system.cpu.num_fp_register_writes 760848 # number of times the floating registers were written -system.cpu.num_cc_register_reads 217149735 # number of times the CC registers were read -system.cpu.num_cc_register_writes 216544825 # number of times the CC registers were written -system.cpu.num_mem_refs 300471292 # number of memory refs -system.cpu.num_load_insts 157490392 # Number of load instructions -system.cpu.num_store_insts 142980900 # Number of store instructions -system.cpu.num_idle_cycles 100455078038.626068 # Number of idle cycles -system.cpu.num_busy_cycles 3063670490.373941 # Number of busy cycles -system.cpu.not_idle_fraction 0.029595 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.970405 # Percentage of idle cycles -system.cpu.Branches 186768786 # Number of branches fetched +system.cpu.committedInsts 835939132 # Number of instructions committed +system.cpu.committedOps 982366087 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 902933087 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 900158 # Number of float alu accesses +system.cpu.num_func_calls 50090187 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 126876498 # number of instructions that are conditional controls +system.cpu.num_int_insts 902933087 # number of integer instructions +system.cpu.num_fp_insts 900158 # number of float instructions +system.cpu.num_int_register_reads 1308206945 # number of times the integer registers were read +system.cpu.num_int_register_writes 715740470 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1453094 # number of times the floating registers were read +system.cpu.num_fp_register_writes 759824 # number of times the floating registers were written +system.cpu.num_cc_register_reads 216985275 # number of times the CC registers were read +system.cpu.num_cc_register_writes 216380044 # number of times the CC registers were written +system.cpu.num_mem_refs 300079118 # number of memory refs +system.cpu.num_load_insts 157292666 # Number of load instructions +system.cpu.num_store_insts 142786452 # Number of store instructions +system.cpu.num_idle_cycles 100459603948.882050 # Number of idle cycles +system.cpu.num_busy_cycles 3059091464.117941 # Number of busy cycles +system.cpu.not_idle_fraction 0.029551 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.970449 # Percentage of idle cycles +system.cpu.Branches 186526742 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 681265861 69.23% 69.23% # Class of executed instruction -system.cpu.op_class::IntMult 2131844 0.22% 69.45% # Class of executed instruction -system.cpu.op_class::IntDiv 96991 0.01% 69.46% # Class of executed instruction +system.cpu.op_class::IntAlu 680504734 69.23% 69.23% # Class of executed instruction +system.cpu.op_class::IntMult 2132093 0.22% 69.45% # Class of executed instruction +system.cpu.op_class::IntDiv 96706 0.01% 69.46% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction @@ -609,537 +608,538 @@ system.cpu.op_class::SimdFloatMisc 112297 0.01% 69.47% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu.op_class::MemRead 157490392 16.00% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 142980900 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 157292666 16.00% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 142786452 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 984078328 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9381962 # number of replacements +system.cpu.op_class::total 982924991 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9370067 # number of replacements system.cpu.dcache.tags.tagsinuse 511.942718 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 290912714 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9382474 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 31.005971 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 290532688 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9370579 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 31.004774 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 5830299500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.942718 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 397 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1211017846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1211017846 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 147435449 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 147435449 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 135766146 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 135766146 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 374114 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 374114 # number of SoftPFReq hits -system.cpu.dcache.WriteLineReq_hits::cpu.data 332621 # number of WriteLineReq hits -system.cpu.dcache.WriteLineReq_hits::total 332621 # number of WriteLineReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338150 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3338150 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3623891 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3623891 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 283534216 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 283534216 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 283908330 # number of overall hits -system.cpu.dcache.overall_hits::total 283908330 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4894991 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4894991 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1998130 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1998130 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1136451 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1136451 # number of SoftPFReq misses -system.cpu.dcache.WriteLineReq_misses::cpu.data 1221510 # number of WriteLineReq misses -system.cpu.dcache.WriteLineReq_misses::total 1221510 # number of WriteLineReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 287378 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 287378 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8114631 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8114631 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9251082 # number of overall misses -system.cpu.dcache.overall_misses::total 9251082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 84471929500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 84471929500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 70206054500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 70206054500 # number of WriteReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48228758000 # number of WriteLineReq miss cycles -system.cpu.dcache.WriteLineReq_miss_latency::total 48228758000 # number of WriteLineReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4418678000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4418678000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 202906742000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 202906742000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 202906742000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 202906742000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 152330440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 152330440 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 137764276 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 137764276 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1510565 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1510565 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::cpu.data 1554131 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.WriteLineReq_accesses::total 1554131 # number of WriteLineReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3625528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3625528 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3623892 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3623892 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 291648847 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 291648847 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 293159412 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 293159412 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032134 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032134 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014504 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.014504 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752335 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.752335 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785976 # miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_miss_rate::total 0.785976 # miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079265 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079265 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.027823 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.027823 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031556 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031556 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17256.809972 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17256.809972 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35135.879297 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35135.879297 # average WriteReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39482.900672 # average WriteLineReq miss latency -system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39482.900672 # average WriteLineReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15375.839487 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15375.839487 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25005.048535 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25005.048535 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21933.298397 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21933.298397 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 1209437211 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1209437211 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 147248395 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 147248395 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 135579268 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 135579268 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 373548 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 373548 # number of SoftPFReq hits +system.cpu.dcache.WriteLineReq_hits::cpu.data 331872 # number of WriteLineReq hits +system.cpu.dcache.WriteLineReq_hits::total 331872 # number of WriteLineReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3336329 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3336329 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3621011 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3621011 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 283159535 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 283159535 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 283533083 # number of overall hits +system.cpu.dcache.overall_hits::total 283533083 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4886658 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4886658 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1993718 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1993718 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1137538 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1137538 # number of SoftPFReq misses +system.cpu.dcache.WriteLineReq_misses::cpu.data 1221988 # number of WriteLineReq misses +system.cpu.dcache.WriteLineReq_misses::total 1221988 # number of WriteLineReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 286320 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 286320 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 8102364 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8102364 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9239902 # number of overall misses +system.cpu.dcache.overall_misses::total 9239902 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84160893500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84160893500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69982072000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69982072000 # number of WriteReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 48119896000 # number of WriteLineReq miss cycles +system.cpu.dcache.WriteLineReq_miss_latency::total 48119896000 # number of WriteLineReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4409003500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4409003500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 162000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 162000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 202262861500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 202262861500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 202262861500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 202262861500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 152135053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 152135053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 137572986 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 137572986 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1511086 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1511086 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::cpu.data 1553860 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.WriteLineReq_accesses::total 1553860 # number of WriteLineReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3622649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3622649 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3621013 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3621013 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 291261899 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 291261899 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292772985 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292772985 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032121 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032121 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014492 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.014492 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.752795 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.752795 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786421 # miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_miss_rate::total 0.786421 # miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.079036 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.079036 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.027818 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.027818 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.031560 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.031560 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17222.587196 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17222.587196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35101.289149 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35101.289149 # average WriteReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 39378.370328 # average WriteLineReq miss latency +system.cpu.dcache.WriteLineReq_avg_miss_latency::total 39378.370328 # average WriteLineReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15398.866653 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15398.866653 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 81000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 81000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24963.438016 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24963.438016 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21890.152244 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21890.152244 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 7313678 # number of writebacks -system.cpu.dcache.writebacks::total 7313678 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21981 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 21981 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21254 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21254 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 68600 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 68600 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 43235 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 43235 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 43235 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 43235 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4873010 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 4873010 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1976876 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1976876 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1134686 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1134686 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221510 # number of WriteLineReq MSHR misses -system.cpu.dcache.WriteLineReq_mshr_misses::total 1221510 # number of WriteLineReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 218778 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 218778 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 8071396 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 8071396 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9206082 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9206082 # number of overall MSHR misses +system.cpu.dcache.writebacks::writebacks 7310347 # number of writebacks +system.cpu.dcache.writebacks::total 7310347 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21149 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 21149 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21212 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21212 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69210 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 69210 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 42361 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 42361 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 42361 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 42361 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 4865509 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 4865509 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1972506 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1972506 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1135773 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1135773 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1221988 # number of WriteLineReq MSHR misses +system.cpu.dcache.WriteLineReq_mshr_misses::total 1221988 # number of WriteLineReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 217110 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 217110 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 8060003 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 8060003 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9195776 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9195776 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78281972500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 78281972500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67251605000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 67251605000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21441642000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21441642000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 47007248000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 47007248000 # number of WriteLineReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3007041000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3007041000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 192540825500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 192540825500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213982467500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 213982467500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199681500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199681500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199681500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199681500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031990 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031990 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751167 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751167 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785976 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785976 # mshr miss rate for WriteLineReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060344 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060344 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027675 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027675 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031403 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031403 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16064.398082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16064.398082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34019.131701 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34019.131701 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18896.542303 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18896.542303 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38482.900672 # average WriteLineReq mshr miss latency -system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38482.900672 # average WriteLineReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13744.713819 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13744.713819 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23854.711812 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23854.711812 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23243.597819 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23243.597819 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183955.892825 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183955.892825 # average ReadReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91969.759680 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91969.759680 # average overall mshr uncacheable latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 13331164 # number of replacements -system.cpu.icache.tags.tagsinuse 511.820795 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 824117568 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13331676 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 61.816501 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 78024875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 78024875000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67036106500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 67036106500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21307541000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21307541000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 46897908000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 46897908000 # number of WriteLineReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2989370500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2989370500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 160000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 160000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 191958889500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 191958889500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213266430500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 213266430500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6199627500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6199627500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6199627500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 6199627500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.031982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031982 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014338 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014338 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.751627 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.751627 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786421 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786421 # mshr miss rate for WriteLineReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.059931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.059931 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027673 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027673 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031409 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031409 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16036.323229 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16036.323229 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33985.248461 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33985.248461 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 18760.386979 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 18760.386979 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 38378.370328 # average WriteLineReq mshr miss latency +system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 38378.370328 # average WriteLineReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13768.921284 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13768.921284 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23816.230527 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23816.230527 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23191.781803 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23191.781803 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183954.290547 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183954.290547 # average ReadReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 91968.958611 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 91968.958611 # average overall mshr uncacheable latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 13316326 # number of replacements +system.cpu.icache.tags.tagsinuse 511.820794 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 823138069 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13316838 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 61.811826 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 49363844500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.820795 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 511.820794 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 188 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 850780930 # Number of tag accesses -system.cpu.icache.tags.data_accesses 850780930 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 824117568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 824117568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 824117568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 824117568 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 824117568 # number of overall hits -system.cpu.icache.overall_hits::total 824117568 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13331681 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13331681 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13331681 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13331681 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13331681 # number of overall misses -system.cpu.icache.overall_misses::total 13331681 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182292722500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182292722500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182292722500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182292722500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182292722500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182292722500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 837449249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 837449249 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 837449249 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 837449249 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 837449249 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 837449249 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13673.648694 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13673.648694 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13673.648694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13673.648694 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13673.648694 # average overall miss latency +system.cpu.icache.tags.tag_accesses 849771755 # Number of tag accesses +system.cpu.icache.tags.data_accesses 849771755 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 823138069 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 823138069 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 823138069 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 823138069 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 823138069 # number of overall hits +system.cpu.icache.overall_hits::total 823138069 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13316843 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13316843 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13316843 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13316843 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13316843 # number of overall misses +system.cpu.icache.overall_misses::total 13316843 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182043679500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182043679500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182043679500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182043679500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182043679500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182043679500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 836454912 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 836454912 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 836454912 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 836454912 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 836454912 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 836454912 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015921 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015921 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015921 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13670.182903 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13670.182903 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13670.182903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13670.182903 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13670.182903 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 13331164 # number of writebacks -system.cpu.icache.writebacks::total 13331164 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13331681 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13331681 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13331681 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13331681 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13331681 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13331681 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 13316326 # number of writebacks +system.cpu.icache.writebacks::total 13316326 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13316843 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13316843 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13316843 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13316843 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13316843 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13316843 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168961041500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 168961041500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168961041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 168961041500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168961041500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 168961041500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 168726836500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 168726836500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 168726836500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 168726836500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 168726836500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 168726836500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 5436787000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 5436787000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 5436787000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015919 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015919 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015919 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12673.648694 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12673.648694 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12673.648694 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12673.648694 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015921 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015921 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015921 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12670.182903 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12670.182903 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12670.182903 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12670.182903 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12670.182903 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12670.182903 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.423188 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126070.423188 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126070.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 1036266 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65255.052774 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 41658706 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1098550 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 37.921538 # Average number of references to valid blocks. +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 1029342 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65301.929117 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 41597878 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1091508 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 38.110466 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 12385503500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38127.362532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 231.236011 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 356.535935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7851.500133 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 18688.418163 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.581777 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003528 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005440 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119804 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.285163 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995713 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 257 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62027 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 257 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 38086.632918 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 236.862091 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 354.562935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7802.558346 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 18821.312827 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.581156 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.003614 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005410 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.119058 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.287190 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996428 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 232 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61934 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2434 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5507 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53647 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003922 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946457 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 372058779 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 372058779 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 313678 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242392 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 556070 # number of ReadReq hits -system.cpu.l2cache.WritebackDirty_hits::writebacks 7313678 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 7313678 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 13329610 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 13329610 # number of WritebackClean hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9057 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9057 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1592946 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1592946 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13260241 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 13260241 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5999138 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 5999138 # number of ReadSharedReq hits -system.cpu.l2cache.InvalidateReq_hits::cpu.data 739812 # number of InvalidateReq hits -system.cpu.l2cache.InvalidateReq_hits::total 739812 # number of InvalidateReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 313678 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 242392 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13260241 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7592084 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 21408395 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 313678 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 242392 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13260241 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7592084 # number of overall hits -system.cpu.l2cache.overall_hits::total 21408395 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2426 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2490 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4916 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 33285 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 33285 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 341588 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 341588 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71440 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 71440 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 227336 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 227336 # number of ReadSharedReq misses -system.cpu.l2cache.InvalidateReq_misses::cpu.data 481698 # number of InvalidateReq misses -system.cpu.l2cache.InvalidateReq_misses::total 481698 # number of InvalidateReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 2426 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2490 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 71440 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 568924 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 645280 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 2426 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2490 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 71440 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 568924 # number of overall misses -system.cpu.l2cache.overall_misses::total 645280 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 332065500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345888500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 677954000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1332961000 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 1332961000 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44822292500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 44822292500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9464687500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 9464687500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30322723500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 30322723500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 403 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5392 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53675 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945038 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 371610075 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 371610075 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 312133 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 242520 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 554653 # number of ReadReq hits +system.cpu.l2cache.WritebackDirty_hits::writebacks 7310347 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 7310347 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 13314767 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 13314767 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 8998 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 8998 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1590193 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1590193 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13245839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 13245839 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 5993599 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 5993599 # number of ReadSharedReq hits +system.cpu.l2cache.InvalidateReq_hits::cpu.data 742035 # number of InvalidateReq hits +system.cpu.l2cache.InvalidateReq_hits::total 742035 # number of InvalidateReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 312133 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 242520 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13245839 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7583792 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 21384284 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 312133 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 242520 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13245839 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7583792 # number of overall hits +system.cpu.l2cache.overall_hits::total 21384284 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2378 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4849 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 33265 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 33265 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 340050 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 340050 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 71004 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 71004 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 224793 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 224793 # number of ReadSharedReq misses +system.cpu.l2cache.InvalidateReq_misses::cpu.data 479953 # number of InvalidateReq misses +system.cpu.l2cache.InvalidateReq_misses::total 479953 # number of InvalidateReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 2378 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 2471 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 71004 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 564843 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 640696 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 2378 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 2471 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 71004 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 564843 # number of overall misses +system.cpu.l2cache.overall_misses::total 640696 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 324181000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 343851000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 668032000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1328369000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1328369000 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 157000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 44644302500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 44644302500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 9404933500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 9404933500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 29984552500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 29984552500 # number of ReadSharedReq miss cycles system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 542500 # number of InvalidateReq miss cycles system.cpu.l2cache.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 332065500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345888500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9464687500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 75145016000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 85287657500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 332065500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345888500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9464687500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 75145016000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 85287657500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 316104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244882 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 560986 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7313678 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackDirty_accesses::total 7313678 # number of WritebackDirty accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::writebacks 13329610 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 13329610 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42342 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 42342 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1934534 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1934534 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13331681 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 13331681 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6226474 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 6226474 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221510 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.InvalidateReq_accesses::total 1221510 # number of InvalidateReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 316104 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 244882 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13331681 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8161008 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 22053675 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 316104 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 244882 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13331681 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8161008 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 22053675 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007675 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010168 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.008763 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.786099 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.786099 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 324181000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 343851000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9404933500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 74628855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 84701820500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 324181000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 343851000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9404933500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 74628855000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 84701820500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 314511 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 244991 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 559502 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::writebacks 7310347 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 7310347 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 13314767 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 13314767 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 42263 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 42263 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1930243 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1930243 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13316843 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 13316843 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6218392 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 6218392 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1221988 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.InvalidateReq_accesses::total 1221988 # number of InvalidateReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 314511 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 244991 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13316843 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8148635 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 22024980 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 314511 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 244991 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13316843 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8148635 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 22024980 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.007561 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010086 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.008667 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.787095 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.787095 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176574 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.176574 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005359 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005359 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036511 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036511 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.394346 # miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_miss_rate::total 0.394346 # miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007675 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010168 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005359 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.069712 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.029260 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007675 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010168 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005359 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.069712 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.029260 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136877.782358 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138911.044177 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 137907.648495 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40046.898002 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40046.898002 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131217.409569 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131217.409569 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132484.427492 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132484.427492 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133382.849615 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133382.849615 # average ReadSharedReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.126224 # average InvalidateReq miss latency -system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.126224 # average InvalidateReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 132171.549560 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136877.782358 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138911.044177 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132484.427492 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132082.696459 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 132171.549560 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.176170 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.176170 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005332 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005332 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.036150 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.036150 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.392764 # miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_miss_rate::total 0.392764 # miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007561 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010086 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005332 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.069317 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.029090 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007561 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010086 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005332 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.069317 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.029090 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136325.063078 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 139154.593282 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 137766.962260 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39932.932512 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39932.932512 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 78500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 78500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 131287.465079 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 131287.465079 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132456.389781 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132456.389781 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 133387.394180 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 133387.394180 # average ReadSharedReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 1.130319 # average InvalidateReq miss latency +system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 1.130319 # average InvalidateReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136325.063078 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 139154.593282 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132456.389781 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 132123.182902 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 132202.823960 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136325.063078 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 139154.593282 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132456.389781 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 132123.182902 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 132202.823960 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 879823 # number of writebacks -system.cpu.l2cache.writebacks::total 879823 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2426 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2490 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4916 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33285 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 33285 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341588 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 341588 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71440 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71440 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 227336 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 227336 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 481698 # number of InvalidateReq MSHR misses -system.cpu.l2cache.InvalidateReq_mshr_misses::total 481698 # number of InvalidateReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2426 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 71440 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 568924 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 645280 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2426 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2490 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 71440 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 568924 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 645280 # number of overall MSHR misses +system.cpu.l2cache.writebacks::writebacks 876332 # number of writebacks +system.cpu.l2cache.writebacks::total 876332 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2378 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2471 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4849 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33265 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33265 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 340050 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 340050 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 71004 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 71004 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 224793 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 224793 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 479953 # number of InvalidateReq MSHR misses +system.cpu.l2cache.InvalidateReq_mshr_misses::total 479953 # number of InvalidateReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2378 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2471 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 71004 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 564843 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 640696 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2378 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2471 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 71004 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 564843 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 640696 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33702 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76827 # number of ReadReq MSHR uncacheable @@ -1148,153 +1148,154 @@ system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33708 system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67410 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110535 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 307805500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 320988500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 628794000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2261111000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2261111000 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41406412500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41406412500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8750287500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8750287500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28049107014 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28049107014 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32589969500 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32589969500 # number of InvalidateReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 307805500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 320988500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8750287500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69455519514 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78834601014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 307805500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 320988500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8750287500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69455519514 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78834601014 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 300401000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 319141000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 619542000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2260005000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2260005000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 137000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41243802500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41243802500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 8694893500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 8694893500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27736359527 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27736359527 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 32474021500 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 32474021500 # number of InvalidateReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 300401000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 319141000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8694893500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68980162027 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 78294597527 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 300401000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 319141000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8694893500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68980162027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 78294597527 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4897724500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777601500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675326000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5777547500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 10675272000 # number of ReadReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4897724500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777601500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675326000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008763 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.786099 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.786099 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5777547500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10675272000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008667 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.787095 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.787095 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176574 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005359 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036511 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036511 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.394346 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.394346 # mshr miss rate for InvalidateReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.029260 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007675 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010168 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005359 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069712 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.029260 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127907.648495 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67931.831155 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67931.831155 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121217.409569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121217.409569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122484.427492 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122484.427492 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123381.721390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123381.721390 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67656.435152 # average InvalidateReq mshr miss latency -system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67656.435152 # average InvalidateReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126877.782358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128911.044177 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122484.427492 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122082.245632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122171.152080 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.176170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.176170 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.036150 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.036150 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.392764 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.392764 # mshr miss rate for InvalidateReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.029090 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007561 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010086 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005332 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.069317 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.029090 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127766.962260 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 67939.425823 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 67939.425823 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 121287.465079 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 121287.465079 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122456.389781 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122456.389781 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 123386.224335 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 123386.224335 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 67660.836582 # average InvalidateReq mshr miss latency +system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 67660.836582 # average InvalidateReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126325.063078 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129154.593282 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122456.389781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 122122.717334 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 122202.413511 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171432.007003 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.790035 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171430.404724 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 138952.087157 # average ReadReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113570.423188 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85708.374128 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.694531 # average overall mshr uncacheable latency -system.cpu.toL2Bus.snoop_filter.tot_requests 45953712 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 23239521 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2704 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2704 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 85707.573060 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 96578.205998 # average overall mshr uncacheable latency +system.cpu.toL2Bus.snoop_filter.tot_requests 45899412 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 23211953 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1753 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2701 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2701 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadReq 981994 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 20540984 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadReq 979874 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 20515947 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 8300157 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13331164 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 2233602 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 42345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 42346 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1934534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1934534 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 13331681 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 6235371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateReq 1328174 # Transaction distribution -system.cpu.toL2Bus.trans_dist::InvalidateResp 1221510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40080776 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28367342 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601942 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 864211 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 69914271 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1706594580 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 990623790 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2528832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2701706258 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1612380 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 25039605 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.019510 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.138308 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::WritebackDirty 8293329 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 13316326 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 2221598 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 42266 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 42268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1930243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1930243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 13316843 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 6227282 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 1328652 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateResp 1221988 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40036262 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28331504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 601742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 860807 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 69830315 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1704695316 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 989618926 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1959928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2516088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2698790258 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1604803 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 65712840 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 25003730 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.019507 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.138299 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 24551092 98.05% 98.05% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488513 1.95% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 24515981 98.05% 98.05% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 487749 1.95% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 25039605 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 43904381000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 25003730 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 43858380000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1555895 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1560894 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20040646500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20018389500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 12924004979 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 12905646976 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 357060000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 356751000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 548107000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 546296000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40345 # Transaction distribution -system.iobus.trans_dist::ReadResp 40345 # Transaction distribution +system.iobus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40338 # Transaction distribution +system.iobus.trans_dist::ReadResp 40338 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1311,11 +1312,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231048 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353832 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1330,16 +1331,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334624 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492544 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42150500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42150000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1357,75 +1358,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25723500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25729000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38601000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566919864 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566926866 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147808000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115506 # number of replacements -system.iocache.tags.tagsinuse 10.446851 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115499 # number of replacements +system.iocache.tags.tagsinuse 10.446740 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115522 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13171623640000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.511150 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935701 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219447 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.652928 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 5.847996 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.598744 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.365500 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.287422 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652921 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040073 # Number of tag accesses -system.iocache.tags.data_accesses 1040073 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1040010 # Number of tag accesses +system.iocache.tags.data_accesses 1040010 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8860 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8897 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115524 # number of demand (read+write) misses -system.iocache.demand_misses::total 115564 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses +system.iocache.demand_misses::total 115557 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115524 # number of overall misses -system.iocache.overall_misses::total 115564 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1628892126 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1633962126 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115517 # number of overall misses +system.iocache.overall_misses::total 115557 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1655174117 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1660244617 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13410994738 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13410994738 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15039886864 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15045307864 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15039886864 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15045307864 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13409764249 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13409764249 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 15064938366 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 15070359866 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 15064938366 # number of overall miss cycles +system.iocache.overall_miss_latency::total 15070359866 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8860 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8897 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115524 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115564 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115524 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115564 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1439,53 +1440,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 183847.869752 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 183653.155670 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 186961.947024 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 186754.175141 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125731.218949 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125731.218949 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130190.265688 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130188.418545 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130190.265688 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32190 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125719.682826 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125719.682826 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130414.945577 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130413.171793 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130414.945577 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 33045 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3376 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.600358 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.788211 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8860 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8897 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115524 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115564 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115524 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115564 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1185892126 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1189112126 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1212524117 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1215744617 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8072604881 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8072604881 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9258497007 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9261918007 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9258497007 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9261918007 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071395398 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8071395398 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 9283919515 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 9287341015 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 9283919515 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 9287341015 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1499,88 +1500,89 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133847.869752 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 133653.155670 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136961.947024 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136754.175141 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75682.562823 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75682.562823 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80143.494053 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80145.356746 # average overall mshr miss latency -system.membus.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75671.223637 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75671.223637 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80368.426422 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80370.215694 # average overall mshr miss latency +system.membus.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76827 # Transaction distribution -system.membus.trans_dist::ReadResp 389416 # Transaction distribution +system.membus.trans_dist::ReadResp 386363 # Transaction distribution system.membus.trans_dist::WriteReq 33708 # Transaction distribution system.membus.trans_dist::WriteResp 33708 # Transaction distribution -system.membus.trans_dist::WritebackDirty 986454 # Transaction distribution -system.membus.trans_dist::CleanEvict 164302 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33853 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::WritebackDirty 982963 # Transaction distribution +system.membus.trans_dist::CleanEvict 160860 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33836 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 341030 # Transaction distribution -system.membus.trans_dist::ReadExResp 341030 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 312589 # Transaction distribution -system.membus.trans_dist::InvalidateReq 588355 # Transaction distribution +system.membus.trans_dist::ReadExReq 339489 # Transaction distribution +system.membus.trans_dist::ReadExResp 339489 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 309536 # Transaction distribution +system.membus.trans_dist::InvalidateReq 586610 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2930961 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3060653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237312 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3297965 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2913100 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3042792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 3280262 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97722208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97892034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7223872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7223872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 105115906 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3315 # Total snoops (count) -system.membus.snoop_fanout::samples 2537144 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 97205216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 97375042 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7234880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7234880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 104609922 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3136 # Total snoops (count) +system.membus.snoopTraffic 200256 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2523850 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2537144 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2523850 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2537144 # Request fanout histogram -system.membus.reqLayer0.occupancy 106903500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2523850 # Request fanout histogram +system.membus.reqLayer0.occupancy 106906000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5766500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5727500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6541365638 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 6514212892 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3628181019 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3604018785 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44825406 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44774812 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1623,28 +1625,28 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759374264500 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51759347706500 # Cumulative time (in ticks) in various power states ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal index dd5c13da3..0cb0b7645 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/system.terminal @@ -32,135 +32,135 @@ [ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000045] Console: colour dummy device 80x25
-[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000051] pid_max: default: 32768 minimum: 301
-[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000352] hw perfevents: no hardware support available
+[ 0.000044] Console: colour dummy device 80x25
+[ 0.000048] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000050] pid_max: default: 32768 minimum: 301
+[ 0.000073] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000075] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000316] hw perfevents: no hardware support available
[ 1.060136] CPU1: failed to come online
-[ 2.080266] CPU2: failed to come online
+[ 2.080267] CPU2: failed to come online
[ 3.100398] CPU3: failed to come online
[ 3.100403] Brought up 1 CPUs
[ 3.100405] SMP: Total of 1 processors activated.
-[ 3.100521] devtmpfs: initialized
-[ 3.101636] atomic64_test: passed
-[ 3.101724] regulator-dummy: no parameters
-[ 3.102567] NET: Registered protocol family 16
-[ 3.102857] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.102869] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.105189] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.105197] Serial: AMBA PL011 UART driver
-[ 3.105593] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.105667] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.106251] console [ttyAMA0] enabled
-[ 3.106398] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.106448] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.106498] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.106544] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130846] 3V3: 3300 mV
-[ 3.130933] vgaarb: loaded
-[ 3.131030] SCSI subsystem initialized
-[ 3.131104] libata version 3.00 loaded.
-[ 3.131195] usbcore: registered new interface driver usbfs
-[ 3.131222] usbcore: registered new interface driver hub
-[ 3.131280] usbcore: registered new device driver usb
-[ 3.131327] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131337] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131361] PTP clock support registered
-[ 3.131603] Switched to clocksource arch_sys_counter
-[ 3.133813] NET: Registered protocol family 2
-[ 3.133980] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.134012] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.134052] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.134106] TCP: reno registered
-[ 3.134114] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134134] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134210] NET: Registered protocol family 1
-[ 3.134289] RPC: Registered named UNIX socket transport module.
-[ 3.134300] RPC: Registered udp transport module.
-[ 3.134309] RPC: Registered tcp transport module.
-[ 3.134318] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.134332] PCI: CLS 0 bytes, default 64
-[ 3.134677] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.134913] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.138682] fuse init (API version 7.23)
-[ 3.138854] msgmni has been set to 469
-[ 3.143616] io scheduler noop registered
-[ 3.143713] io scheduler cfq registered (default)
-[ 3.144776] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.144790] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.144803] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.144817] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.144829] pci_bus 0000:00: scanning bus
-[ 3.144843] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.144859] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.144876] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144939] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.144953] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.144966] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.144978] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.144991] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.145004] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.145017] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.145077] pci_bus 0000:00: fixups for bus
-[ 3.145087] pci_bus 0000:00: bus scan returning with max=00
-[ 3.145101] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.145130] pci 0000:00:00.0: fixup irq: got 33
-[ 3.145140] pci 0000:00:00.0: assigning IRQ 33
-[ 3.145154] pci 0000:00:01.0: fixup irq: got 34
-[ 3.145164] pci 0000:00:01.0: assigning IRQ 34
-[ 3.145178] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.145193] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.145208] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.145222] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.145236] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.145249] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.145262] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.145276] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.146194] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146724] ata_piix 0000:00:01.0: version 2.13
-[ 3.146736] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.146781] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.147384] scsi0 : ata_piix
-[ 3.147568] scsi1 : ata_piix
-[ 3.147622] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.147635] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147840] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147853] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147876] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147889] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301640] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301651] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301686] ata1.00: configured for UDMA/33
-[ 3.301774] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301972] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.302008] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.302066] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.302077] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.302106] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.302309] sda: sda1
-[ 3.302514] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421965] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.421980] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.422010] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.422021] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.422052] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.422065] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.422197] usbcore: registered new interface driver usb-storage
-[ 3.422291] mousedev: PS/2 mouse device common for all mice
-[ 3.422584] usbcore: registered new interface driver usbhid
-[ 3.422595] usbhid: USB HID core driver
-[ 3.422651] TCP: cubic registered
-[ 3.422660] NET: Registered protocol family 17
- -[ 3.423338] devtmpfs: mounted
-[ 3.423462] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 3.100517] devtmpfs: initialized
+[ 3.101614] atomic64_test: passed
+[ 3.101697] regulator-dummy: no parameters
+[ 3.102519] NET: Registered protocol family 16
+[ 3.102798] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102809] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.104232] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.104240] Serial: AMBA PL011 UART driver
+[ 3.104622] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.104693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.105277] console [ttyAMA0] enabled
+[ 3.105422] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.105471] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.105522] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.105568] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.130937] 3V3: 3300 mV
+[ 3.131019] vgaarb: loaded
+[ 3.131116] SCSI subsystem initialized
+[ 3.131186] libata version 3.00 loaded.
+[ 3.131272] usbcore: registered new interface driver usbfs
+[ 3.131299] usbcore: registered new interface driver hub
+[ 3.131354] usbcore: registered new device driver usb
+[ 3.131399] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131409] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131433] PTP clock support registered
+[ 3.131670] Switched to clocksource arch_sys_counter
+[ 3.133769] NET: Registered protocol family 2
+[ 3.133932] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.133964] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.134004] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.134042] TCP: reno registered
+[ 3.134050] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134070] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134144] NET: Registered protocol family 1
+[ 3.134216] RPC: Registered named UNIX socket transport module.
+[ 3.134227] RPC: Registered udp transport module.
+[ 3.134236] RPC: Registered tcp transport module.
+[ 3.134245] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134259] PCI: CLS 0 bytes, default 64
+[ 3.134575] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134796] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138336] fuse init (API version 7.23)
+[ 3.138502] msgmni has been set to 469
+[ 3.143073] io scheduler noop registered
+[ 3.143173] io scheduler cfq registered (default)
+[ 3.144095] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.144109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.144122] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.144136] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.144147] pci_bus 0000:00: scanning bus
+[ 3.144161] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.144177] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.144195] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144258] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.144272] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.144285] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.144297] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.144310] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.144322] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.144336] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.144395] pci_bus 0000:00: fixups for bus
+[ 3.144405] pci_bus 0000:00: bus scan returning with max=00
+[ 3.144419] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.144446] pci 0000:00:00.0: fixup irq: got 33
+[ 3.144456] pci 0000:00:00.0: assigning IRQ 33
+[ 3.144470] pci 0000:00:01.0: fixup irq: got 34
+[ 3.144480] pci 0000:00:01.0: assigning IRQ 34
+[ 3.144494] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.144509] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.144524] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.144538] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.144552] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.144565] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.144578] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.144591] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.145478] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.146000] ata_piix 0000:00:01.0: version 2.13
+[ 3.146012] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.146049] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.146644] scsi0 : ata_piix
+[ 3.146827] scsi1 : ata_piix
+[ 3.146881] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.146894] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.147093] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.147106] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.147129] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.147142] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301707] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301718] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301753] ata1.00: configured for UDMA/33
+[ 3.301838] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302037] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302073] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302130] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302141] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302170] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302373] sda: sda1
+[ 3.302577] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422032] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422047] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422076] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422087] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422118] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422131] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422262] usbcore: registered new interface driver usb-storage
+[ 3.422357] mousedev: PS/2 mouse device common for all mice
+[ 3.422646] usbcore: registered new interface driver usbhid
+[ 3.422657] usbhid: USB HID core driver
+[ 3.422710] TCP: cubic registered
+[ 3.422720] NET: Registered protocol family 17
+ +[ 3.423384] devtmpfs: mounted
+[ 3.423472] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.470418] udevd[607]: starting version 182
+[ 3.470435] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.586551] random: dd urandom read with 21 bits of entropy available
+[ 3.596617] random: dd urandom read with 22 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -169,7 +169,7 @@ Mon Jan 27 08:00:00 UTC 2014 hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.791840] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+[ 3.791906] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
Sending discover...
Sending discover...
Sending discover...
|