diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2015-04-22 20:22:29 -0700 |
| commit | 0cf36d94095aedef3c51447243c5a3cc14dd5d56 (patch) | |
| tree | c0ed9e35fbbc5512f7fedf2947d4ae2702214f8e /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout | |
| parent | a70a83155bfe4c3877894c29f9dea720beb40f9c (diff) | |
| download | gem5-0cf36d94095aedef3c51447243c5a3cc14dd5d56.tar.xz | |
stats: update for previous changeset
Very small differences in IQ-specific O3 stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout')
| -rwxr-xr-x[-rw-r--r--] | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout index 622975a2a..76fd76bdb 100644..100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 29 2014 09:18:22 -gem5 started Oct 29 2014 11:58:52 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5.latest/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full +gem5 compiled Apr 22 2015 10:58:25 +gem5 started Apr 22 2015 14:18:06 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full + Selected 64-bit ARM architecture, updating default disk image... Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x563eb00 0x563eb00 - 0: system.cpu1.isa: ISA system set to: 0x563eb00 0x563eb00 - 0: system.cpu2.isa: ISA system set to: 0x563eb00 0x563eb00 + 0: system.cpu0.isa: ISA system set to: 0x47f6c80 0x47f6c80 + 0: system.cpu1.isa: ISA system set to: 0x47f6c80 0x47f6c80 + 0: system.cpu2.isa: ISA system set to: 0x47f6c80 0x47f6c80 |