diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt | 5390 |
1 files changed, 2697 insertions, 2693 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index aa5265b3e..7b0e2ea39 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,193 +1,193 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.316261 # Number of seconds simulated -sim_ticks 51316261201000 # Number of ticks simulated -final_tick 51316261201000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.316276 # Number of seconds simulated +sim_ticks 51316275690000 # Number of ticks simulated +final_tick 51316275690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 303672 # Simulator instruction rate (inst/s) -host_op_rate 356843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18193830206 # Simulator tick rate (ticks/s) -host_mem_usage 686184 # Number of bytes of host memory used -host_seconds 2820.53 # Real time elapsed on the host -sim_insts 856517636 # Number of instructions simulated -sim_ops 1006486660 # Number of ops (including micro ops) simulated +host_inst_rate 326587 # Simulator instruction rate (inst/s) +host_op_rate 383768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19561029283 # Simulator tick rate (ticks/s) +host_mem_usage 692584 # Number of bytes of host memory used +host_seconds 2623.39 # Real time elapsed on the host +sim_insts 856765339 # Number of instructions simulated +sim_ops 1006773904 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 89408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 88064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2284980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19216392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 19648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 18624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 651264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5282880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 33920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 30784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 1695808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 7120960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 74240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.itb.walker 63168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 1609856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 11459776 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 417920 # Number of bytes read from this memory -system.physmem.bytes_read::total 50157692 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2284980 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 651264 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 1695808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 1609856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6241908 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69878272 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 86656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2383476 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 19569480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 19008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 645440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5197376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 31936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 29376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 1640192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 6901376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 81152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.itb.walker 66816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 1624448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 11589312 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437504 # Number of bytes read from this memory +system.physmem.bytes_read::total 50412348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2383476 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 645440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 1640192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 1624448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6293556 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 70023744 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69898852 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1376 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 76110 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 300269 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 307 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 291 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 10176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 530 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 481 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 26497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 111265 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 1160 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.itb.walker 987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 25154 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 179059 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6530 # Number of read requests responded to by this memory -system.physmem.num_reads::total 824134 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1091848 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 70044324 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1354 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 77649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 305786 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10085 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 499 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 25628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 107834 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 1268 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.itb.walker 1044 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 25382 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 181083 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6836 # Number of read requests responded to by this memory +system.physmem.num_reads::total 828113 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1094121 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1094421 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1742 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 44527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 374470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 12691 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 102947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 661 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 33046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 138766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.itb.walker 1231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 31371 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 223317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 977423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 44527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 12691 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 33046 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 31371 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 121636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1361718 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1096694 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 381350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 439 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 12578 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 101281 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 31962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 134487 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.itb.walker 1302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 31656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 225841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 982385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46447 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 12578 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 31962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 31656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 122642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1364552 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1362119 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1361718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1742 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 44527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 374871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 12691 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 102947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 33046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 138766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.itb.walker 1231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 31371 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 223317 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2339542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 438929 # Number of read requests accepted -system.physmem.writeReqs 487711 # Number of write requests accepted -system.physmem.readBursts 438929 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 487711 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28073280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue -system.physmem.bytesWritten 31211968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28091456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 31213504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1364953 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1364552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1689 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 381751 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 12578 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 101281 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 31962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 134487 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.itb.walker 1302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 31656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 225841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2347339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 435200 # Number of read requests accepted +system.physmem.writeReqs 483804 # Number of write requests accepted +system.physmem.readBursts 435200 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 483804 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27836736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16064 # Total number of bytes read from write queue +system.physmem.bytesWritten 30961600 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27852800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 30963456 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 251 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25285 # Per bank write bursts -system.physmem.perBankRdBursts::1 29259 # Per bank write bursts -system.physmem.perBankRdBursts::2 26350 # Per bank write bursts -system.physmem.perBankRdBursts::3 25668 # Per bank write bursts -system.physmem.perBankRdBursts::4 27357 # Per bank write bursts -system.physmem.perBankRdBursts::5 30719 # Per bank write bursts -system.physmem.perBankRdBursts::6 26473 # Per bank write bursts -system.physmem.perBankRdBursts::7 28031 # Per bank write bursts -system.physmem.perBankRdBursts::8 25079 # Per bank write bursts -system.physmem.perBankRdBursts::9 30131 # Per bank write bursts -system.physmem.perBankRdBursts::10 27758 # Per bank write bursts -system.physmem.perBankRdBursts::11 30805 # Per bank write bursts -system.physmem.perBankRdBursts::12 27043 # Per bank write bursts -system.physmem.perBankRdBursts::13 27394 # Per bank write bursts -system.physmem.perBankRdBursts::14 24672 # Per bank write bursts -system.physmem.perBankRdBursts::15 26621 # Per bank write bursts -system.physmem.perBankWrBursts::0 26756 # Per bank write bursts -system.physmem.perBankWrBursts::1 29816 # Per bank write bursts -system.physmem.perBankWrBursts::2 28574 # Per bank write bursts -system.physmem.perBankWrBursts::3 30074 # Per bank write bursts -system.physmem.perBankWrBursts::4 31364 # Per bank write bursts -system.physmem.perBankWrBursts::5 33348 # Per bank write bursts -system.physmem.perBankWrBursts::6 29983 # Per bank write bursts -system.physmem.perBankWrBursts::7 32184 # Per bank write bursts -system.physmem.perBankWrBursts::8 30191 # Per bank write bursts -system.physmem.perBankWrBursts::9 34064 # Per bank write bursts -system.physmem.perBankWrBursts::10 29741 # Per bank write bursts -system.physmem.perBankWrBursts::11 31916 # Per bank write bursts -system.physmem.perBankWrBursts::12 29919 # Per bank write bursts -system.physmem.perBankWrBursts::13 30461 # Per bank write bursts -system.physmem.perBankWrBursts::14 29114 # Per bank write bursts -system.physmem.perBankWrBursts::15 30182 # Per bank write bursts +system.physmem.perBankRdBursts::0 27905 # Per bank write bursts +system.physmem.perBankRdBursts::1 28763 # Per bank write bursts +system.physmem.perBankRdBursts::2 27094 # Per bank write bursts +system.physmem.perBankRdBursts::3 24985 # Per bank write bursts +system.physmem.perBankRdBursts::4 26681 # Per bank write bursts +system.physmem.perBankRdBursts::5 30728 # Per bank write bursts +system.physmem.perBankRdBursts::6 26238 # Per bank write bursts +system.physmem.perBankRdBursts::7 28208 # Per bank write bursts +system.physmem.perBankRdBursts::8 24817 # Per bank write bursts +system.physmem.perBankRdBursts::9 29447 # Per bank write bursts +system.physmem.perBankRdBursts::10 28003 # Per bank write bursts +system.physmem.perBankRdBursts::11 29718 # Per bank write bursts +system.physmem.perBankRdBursts::12 26417 # Per bank write bursts +system.physmem.perBankRdBursts::13 26875 # Per bank write bursts +system.physmem.perBankRdBursts::14 23221 # Per bank write bursts +system.physmem.perBankRdBursts::15 25849 # Per bank write bursts +system.physmem.perBankWrBursts::0 29439 # Per bank write bursts +system.physmem.perBankWrBursts::1 30169 # Per bank write bursts +system.physmem.perBankWrBursts::2 29222 # Per bank write bursts +system.physmem.perBankWrBursts::3 30308 # Per bank write bursts +system.physmem.perBankWrBursts::4 30582 # Per bank write bursts +system.physmem.perBankWrBursts::5 32929 # Per bank write bursts +system.physmem.perBankWrBursts::6 29622 # Per bank write bursts +system.physmem.perBankWrBursts::7 32397 # Per bank write bursts +system.physmem.perBankWrBursts::8 29255 # Per bank write bursts +system.physmem.perBankWrBursts::9 32999 # Per bank write bursts +system.physmem.perBankWrBursts::10 30308 # Per bank write bursts +system.physmem.perBankWrBursts::11 31541 # Per bank write bursts +system.physmem.perBankWrBursts::12 29215 # Per bank write bursts +system.physmem.perBankWrBursts::13 29346 # Per bank write bursts +system.physmem.perBankWrBursts::14 27349 # Per bank write bursts +system.physmem.perBankWrBursts::15 29094 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 51315260920500 # Total gap between requests +system.physmem.numWrRetry 19 # Number of times write queue was full causing retry +system.physmem.totGap 51315275469000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 438929 # Read request sizes (log2) +system.physmem.readPktSize::6 435200 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 487711 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 67593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 44 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 483804 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 339047 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 67972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19489 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8325 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -199,185 +199,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 581 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 556 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 554 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 551 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 10806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 12800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 21548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 23833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 26317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 27236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 28042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 28569 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 29592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 29655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 30940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 31802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 30047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 29665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 30409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 27749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 27223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 26642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 10688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 12645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 21314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 23642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 26112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 26953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 27836 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 28305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 29478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 29464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 30830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 31587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 29857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 29451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 30076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 27393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 27014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 26345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 203 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 279155 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 212.371879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.666378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 251.561006 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 134237 48.09% 48.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 73368 26.28% 74.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25102 8.99% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12608 4.52% 87.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8433 3.02% 90.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5025 1.80% 92.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3984 1.43% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2939 1.05% 95.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13459 4.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 279155 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 26191 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.746211 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.447790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 9423 35.98% 35.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 15107 57.68% 93.66% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1332 5.09% 98.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 231 0.88% 99.63% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 66 0.25% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 23 0.09% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 3 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-143 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::144-159 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-399 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 26191 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 26191 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.620404 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.778521 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.884507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 23 0.09% 0.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 48 0.18% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 24431 93.28% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 637 2.43% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 499 1.91% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 119 0.45% 98.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 74 0.28% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 52 0.20% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 187 0.71% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 21 0.08% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 13 0.05% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 5 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 20 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 18 0.07% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 7 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrQLenPdf::46 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 59 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 275230 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 213.631363 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.345796 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.466079 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 131747 47.87% 47.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 72284 26.26% 74.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24873 9.04% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12745 4.63% 87.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8355 3.04% 90.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4904 1.78% 92.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4003 1.45% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2900 1.05% 95.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 13419 4.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 275230 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 25971 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.744908 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.064212 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-7 4094 15.76% 15.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8-15 5177 19.93% 35.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-23 12484 48.07% 83.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::24-31 2573 9.91% 93.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-39 911 3.51% 97.18% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40-47 410 1.58% 98.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-55 151 0.58% 99.34% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::56-63 87 0.33% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-71 41 0.16% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::72-79 17 0.07% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-87 14 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::88-95 7 0.03% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-103 1 0.00% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::136-143 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::144-151 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::208-215 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 25971 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 25971 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.627508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.774611 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.820731 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 27 0.10% 0.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 58 0.22% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 24184 93.12% 93.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 657 2.53% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 512 1.97% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 109 0.42% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 61 0.23% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 50 0.19% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 187 0.72% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 29 0.11% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 13 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 6 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 4 0.02% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 13 0.05% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 7 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 7 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 17 0.07% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 7 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 5 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-191 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-215 2 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-239 1 0.00% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::240-247 1 0.00% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::248-255 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-311 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::488-495 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 26191 # Writes before turning the bus around for reads -system.physmem.totQLat 8271276046 # Total ticks spent queuing -system.physmem.totMemAccLat 16495869796 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2193225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18856.42 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::256-263 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-279 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::312-319 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 25971 # Writes before turning the bus around for reads +system.physmem.totQLat 8284996307 # Total ticks spent queuing +system.physmem.totMemAccLat 16440290057 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2174745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19048.20 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37606.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37798.20 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.54 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.54 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.58 # Average write queue length when enqueuing -system.physmem.readRowHits 320460 # Number of row buffer hits during reads -system.physmem.writeRowHits 326715 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.99 # Row buffer hit rate for writes -system.physmem.avgGap 55377774.45 # Average gap between requests -system.physmem.pageHitRate 69.86 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1063933920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 578980875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1709237400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1568801520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1175120467920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 30458927805750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34952000129865 # Total energy per rank (pJ) -system.physmem_0.averagePower 665.969400 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48914934224726 # Time in different power states -system.physmem_0.memoryStateTime::REF 1693778580000 # Time in different power states +system.physmem.avgWrQLen 8.48 # Average write queue length when enqueuing +system.physmem.readRowHits 317706 # Number of row buffer hits during reads +system.physmem.writeRowHits 325786 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 67.34 # Row buffer hit rate for writes +system.physmem.avgGap 55837923.96 # Average gap between requests +system.physmem.pageHitRate 70.04 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1063034280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 578527125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1720625400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1585448640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3313031919600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1176100438995 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29681595659250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34175675653290 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.640087 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48913549174000 # Time in different power states +system.physmem_0.memoryStateTime::REF 1693779100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 115598736274 # Time in different power states +system.physmem_0.memoryStateTime::ACT 116961174250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1046477880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 569311875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1712123400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1591410240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3313030902480 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1175283684855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29689572406500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34182806317230 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.621570 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48914700007992 # Time in different power states -system.physmem_1.memoryStateTime::REF 1693778580000 # Time in different power states +system.physmem_1.actEnergy 1017704520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 553591500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1671906600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1549413360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3313031919600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1173827506995 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29683698941250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34175350983825 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.631365 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48916914851742 # Time in different power states +system.physmem_1.memoryStateTime::REF 1693779100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 115815403258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 113597968758 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -394,9 +400,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -404,7 +410,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -434,49 +440,49 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 91599 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 91599 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 91599 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 91599 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 91599 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.489246 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -194134706080 -48.92% -48.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 590938857500 148.92% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 396804151420 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 67399 85.01% 85.01% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 11889 14.99% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 79288 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91599 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 90923 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 90923 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 90923 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 90923 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 90923 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 396801198420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.489265 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -194140819580 -48.93% -48.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 590942018000 148.93% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 396801198420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 66800 85.03% 85.03% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11762 14.97% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 78562 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90923 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91599 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79288 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90923 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78562 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79288 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 170887 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78562 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 169485 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 64302418 # DTB read hits -system.cpu0.dtb.read_misses 69160 # DTB read misses -system.cpu0.dtb.write_hits 58215557 # DTB write hits -system.cpu0.dtb.write_misses 22439 # DTB write misses +system.cpu0.dtb.read_hits 64271568 # DTB read hits +system.cpu0.dtb.read_misses 68949 # DTB read misses +system.cpu0.dtb.write_hits 58335276 # DTB write hits +system.cpu0.dtb.write_misses 21974 # DTB write misses system.cpu0.dtb.flush_tlb 1189 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 41969 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 16131 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 408 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 41721 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2769 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 2805 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 7637 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 64371578 # DTB read accesses -system.cpu0.dtb.write_accesses 58237996 # DTB write accesses +system.cpu0.dtb.perms_faults 7542 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 64340517 # DTB read accesses +system.cpu0.dtb.write_accesses 58357250 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 122517975 # DTB hits -system.cpu0.dtb.misses 91599 # DTB misses -system.cpu0.dtb.accesses 122609574 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 122606844 # DTB hits +system.cpu0.dtb.misses 90923 # DTB misses +system.cpu0.dtb.accesses 122697767 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,54 +512,54 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 53904 # Table walker walks requested -system.cpu0.itb.walker.walksLong 53904 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 53904 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 53904 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 53904 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 396804151420 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.489341 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -194172707080 -48.93% -48.93% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 590976858500 148.93% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 396804151420 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 47053 95.04% 95.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2454 4.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 49507 # Table walker page sizes translated +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 54169 # Table walker walks requested +system.cpu0.itb.walker.walksLong 54169 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 54169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 54169 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 54169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 396801198420 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.489353 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -194175666580 -48.94% -48.94% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 590976865000 148.94% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 396801198420 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 47334 95.01% 95.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2486 4.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 49820 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53904 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53904 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 54169 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 54169 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49507 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49507 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 103411 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 341562377 # ITB inst hits -system.cpu0.itb.inst_misses 53904 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49820 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49820 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 103989 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 341484641 # ITB inst hits +system.cpu0.itb.inst_misses 54169 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 1189 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 16108 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 410 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29855 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 16131 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 408 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29832 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 341616281 # ITB inst accesses -system.cpu0.itb.hits 341562377 # DTB hits -system.cpu0.itb.misses 53904 # DTB misses -system.cpu0.itb.accesses 341616281 # DTB accesses -system.cpu0.numPwrStateTransitions 12142 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 6071 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 8248096077.910065 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 210376306672.099670 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 2573 42.38% 42.38% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 3474 57.22% 99.60% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 341538810 # ITB inst accesses +system.cpu0.itb.hits 341484641 # DTB hits +system.cpu0.itb.misses 54169 # DTB misses +system.cpu0.itb.accesses 341538810 # DTB accesses +system.cpu0.numPwrStateTransitions 12198 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 6099 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 8210231821.367437 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 209893503926.618408 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 2601 42.65% 42.65% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 3474 56.96% 99.61% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 5 0.08% 99.69% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 4 0.07% 99.77% # Distribution of time spent in the clock gated state @@ -563,652 +569,652 @@ system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.84 system.cpu0.pwrStateClkGateDist::8.5e+11-9e+11 1 0.02% 99.85% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 9 0.15% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 7947193303500 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 6071 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 1242069912008 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074191288992 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 412426852 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 7947193321500 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 6099 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 1242071811480 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 50074203878520 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 412415124 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16568 # number of quiesce instructions executed -system.cpu0.committedInsts 341412971 # Number of instructions committed -system.cpu0.committedOps 401608369 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 368837990 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 362244 # Number of float alu accesses -system.cpu0.num_func_calls 20461819 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 51941822 # number of instructions that are conditional controls -system.cpu0.num_int_insts 368837990 # number of integer instructions -system.cpu0.num_fp_insts 362244 # number of float instructions -system.cpu0.num_int_register_reads 539535569 # number of times the integer registers were read -system.cpu0.num_int_register_writes 292940682 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 578749 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 318148 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 89683557 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 89472336 # number of times the CC registers were written -system.cpu0.num_mem_refs 122593410 # number of memory refs -system.cpu0.num_load_insts 64360945 # Number of load instructions -system.cpu0.num_store_insts 58232465 # Number of store instructions -system.cpu0.num_idle_cycles 402405334.403935 # Number of idle cycles -system.cpu0.num_busy_cycles 10021517.596065 # Number of busy cycles +system.cpu0.kern.inst.quiesce 16566 # number of quiesce instructions executed +system.cpu0.committedInsts 341336485 # Number of instructions committed +system.cpu0.committedOps 401580232 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 368861574 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 359512 # Number of float alu accesses +system.cpu0.num_func_calls 20525784 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 51873404 # number of instructions that are conditional controls +system.cpu0.num_int_insts 368861574 # number of integer instructions +system.cpu0.num_fp_insts 359512 # number of float instructions +system.cpu0.num_int_register_reads 539079221 # number of times the integer registers were read +system.cpu0.num_int_register_writes 292860354 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 571011 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 323488 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 89499549 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 89284497 # number of times the CC registers were written +system.cpu0.num_mem_refs 122681510 # number of memory refs +system.cpu0.num_load_insts 64329809 # Number of load instructions +system.cpu0.num_store_insts 58351701 # Number of store instructions +system.cpu0.num_idle_cycles 402393876.753300 # Number of idle cycles +system.cpu0.num_busy_cycles 10021247.246700 # Number of busy cycles system.cpu0.not_idle_fraction 0.024299 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.975701 # Percentage of idle cycles -system.cpu0.Branches 76142746 # Number of branches fetched +system.cpu0.Branches 76154036 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 278290201 69.25% 69.25% # Class of executed instruction -system.cpu0.op_class::IntMult 876142 0.22% 69.47% # Class of executed instruction -system.cpu0.op_class::IntDiv 42968 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 47686 0.01% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu0.op_class::MemRead 64360945 16.02% 85.51% # Class of executed instruction -system.cpu0.op_class::MemWrite 58232465 14.49% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 278201506 69.24% 69.24% # Class of executed instruction +system.cpu0.op_class::IntMult 848038 0.21% 69.45% # Class of executed instruction +system.cpu0.op_class::IntDiv 41846 0.01% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 48432 0.01% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu0.op_class::MemRead 64329809 16.01% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 58351701 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 401850407 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 9785258 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999715 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 296102427 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9785770 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.258470 # Average number of references to valid blocks. +system.cpu0.op_class::total 401821333 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 9787095 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 296232659 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9787607 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.266097 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.924139 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.613790 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.156237 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 5.305549 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970555 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009011 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010071 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.010362 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.142011 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.386995 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.164772 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 6.305937 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969027 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.008568 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010087 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.012316 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1254458148 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1254458148 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 60043274 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 19451230 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 26515970 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 46522470 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152532944 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 55058218 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 17868348 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 23514922 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 39147049 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135588537 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 161685 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47989 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 79490 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 113267 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 402431 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128215 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43197 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu2.data 56794 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu3.data 101554 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 329760 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1440792 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 445911 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 586217 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 965735 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3438655 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1532117 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 486268 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 631716 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1115803 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3765904 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 115229707 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2284034500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3520477000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 238500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 238500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 18740019500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 34915464000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 153701625134 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 207357108634 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 18740019500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 34915464000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 153701625134 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 207357108634 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 62132591 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 20089667 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 27396682 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 50016692 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 159635632 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 55889268 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 18118115 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 24168458 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu3.data 42633464 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 140809305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 678254 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 181423 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 294530 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 444571 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1598778 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 787273 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 152230 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 213183 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 405152 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1557838 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1532762 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 486494 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 631934 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1149431 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3800621 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1532117 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 486268 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 631716 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1115814 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3765915 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 118809132 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 38360012 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 51778323 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu3.data 93055308 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 302002775 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 119487386 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 38541435 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 52072853 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu3.data 93499879 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 303601553 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033627 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031779 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.032147 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.069861 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.044493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014870 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.013785 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.027041 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.081776 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.037077 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.761616 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.735486 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.730112 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.745222 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.748288 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.837140 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.716239 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.733590 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.749343 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788322 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060003 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.083419 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.072345 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.159815 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095239 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.030128 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025997 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.032651 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu3.data 0.078279 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044872 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034280 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029337 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.036596 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu3.data 0.081450 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048576 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15561.531522 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.000981 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 14797.458490 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10662.821949 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27984.321388 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27837.128330 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27606.237163 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23258.824149 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 16650.023387 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 16809.772426 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 18936.952144 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 8300.357385 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14510.607890 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14164.501170 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12433.773735 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9725.988076 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 21681.818182 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21681.818182 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18791.941635 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20652.253559 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21100.585735 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15301.375374 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16574.246178 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18321.816341 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20182.632527 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14060.128952 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9910258 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 8881 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 889663 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 270 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.139339 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 32.892593 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 7576706 # number of writebacks -system.cpu0.dcache.writebacks::total 7576706 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2565 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 39446 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1918307 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 1960318 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 33 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 288880 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2890218 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3179131 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 17 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2227 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 2244 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 9010 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10983 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 113640 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 133633 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 2598 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 328343 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 4810752 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 5141693 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 2598 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 328343 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 4810752 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 5141693 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 635872 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 841266 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1575915 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3053053 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 249734 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 364656 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 596197 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1210587 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 133434 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 214937 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 326698 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 675069 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 109033 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 156372 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 301371 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 566776 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 31573 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 34734 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 70056 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136363 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 994639 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 1362294 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu3.data 2473483 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4830416 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1128073 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 1577231 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu3.data 2800181 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5505485 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5165 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4559 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4594 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14318 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4682 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4068 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4289 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13039 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 9847 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8627 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 8883 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27357 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9259931500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12493159000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23820252500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45573343000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6737865000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9614650500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17374860004 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33727375504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2271729000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3143350500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4907861500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10322941000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 1706369000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 2472082000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 5367328797 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 9545779797 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 413953500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 450661000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 926981000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1791595500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 227500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 17704165500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 24579891500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 46562441301 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 88846498301 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 19975894500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27723242000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51470302801 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 99169439301 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 937823500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 818983500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 848897000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2605704000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 937823500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 818983500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 848897000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2605704000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031652 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030707 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031508 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019125 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013784 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015088 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008597 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.735486 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.729763 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.734861 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.422241 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.716239 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.733511 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.743847 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.363822 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064899 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.054965 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060948 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.035879 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000010 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025929 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026310 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026581 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015995 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029269 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030289 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029948 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018134 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14562.571555 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14850.426619 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15115.188636 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14927.137852 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26980.166898 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26366.357608 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29142.816894 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27860.348330 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17025.113539 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14624.520208 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15022.624871 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15291.682776 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15650.023387 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15808.981148 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17809.705635 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16842.244197 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13110.996738 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12974.635804 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13232.000114 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13138.428313 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20681.818182 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20681.818182 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17799.589097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18043.015311 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18824.645773 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18393.135974 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17707.980335 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17577.160226 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18381.062796 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18012.843428 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181572.797677 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 179641.039702 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184783.848498 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 181987.987149 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95239.514573 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 94932.595340 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95564.223798 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95248.163176 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 15885620 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.975044 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 560402159 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 15886132 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.276187 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9934044500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.724807 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.897260 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 29.967538 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.385439 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.921338 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005659 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.058530 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu3.inst 0.014425 # Average percentage of cache occupancy +system.cpu0.dcache.tags.tag_accesses 1255111411 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1255111411 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 60046999 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 19454301 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 26463320 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu3.data 46623681 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 152588301 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 55195720 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 17791665 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 23636838 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu3.data 39052226 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 135676449 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 163106 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 47592 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 79678 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112887 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 403263 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 128728 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 43000 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu2.data 56036 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu3.data 102004 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 329768 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1435392 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 439802 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 587328 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 976810 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3439332 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1527210 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 478716 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 634274 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1126445 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3766645 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 115371447 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 37288966 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 50156194 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu3.data 85777911 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 288594518 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 115534553 # 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number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27184 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9316912500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12310511500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 24145682500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45773106500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6694367500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9409306500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17283283287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33386957287 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2351295000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3106665500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4848120000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10306080500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 1740876500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 2415825500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 5418758314 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 9575460314 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 393499000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 471106000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 934011000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1798616000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 181500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 181500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 17752156500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 24135643500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 46847724101 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 88735524101 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 20103451500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 27242309000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 51695844101 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 99041604601 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 916274500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 823963000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 848646500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2588884000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 916274500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 823963000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 848646500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2588884000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031862 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030618 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031876 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019266 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014293 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014932 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013866 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749617 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.728509 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.731933 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.423713 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725923 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.729962 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.745465 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.366282 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063517 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.057570 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060890 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036195 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026426 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.026068 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.026794 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016079 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.029997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.030029 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.030096 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018224 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14550.377857 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14706.756942 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15087.637984 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14872.272356 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25947.965441 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25945.184346 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29326.804982 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27592.823135 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16502.052848 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14509.263670 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15120.889266 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.104027 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 15285.595750 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 15944.043321 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 17750.474374 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 16778.947882 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12935.535832 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12896.413906 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13220.629034 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13071.527202 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 25928.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25928.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17538.138595 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17861.781912 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 18776.868700 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18264.283580 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17410.288753 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17403.211783 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18360.546336 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17891.617035 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 181836.574717 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 180022.503823 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 184608.766587 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182149.018504 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95385.644389 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 95079.967690 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 95225.145871 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95235.579753 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 15900081 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.975051 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 560800301 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 15900593 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.269144 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9932119500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.881688 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.899404 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 30.014484 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.179475 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.921644 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.005663 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.058622 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu3.inst 0.014022 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 292 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 592540078 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 592540078 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 336114841 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 108439877 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 66818852 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.087964 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.018004 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015388 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055352 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.087964 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.018004 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015388 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055352 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.087964 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.018004 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12447.852229 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12493.937605 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12516.556317 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12496.792702 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12447.852229 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12493.937605 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12516.556317 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12496.792702 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12447.852229 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12493.937605 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12516.556317 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12496.792702 # average overall mshr miss latency +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1238,69 +1244,65 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 31142 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 31142 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4562 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22714 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 31138 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 31138 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 31138 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 27280 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 24555.205279 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21409.224401 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 12983.742991 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 17842 65.40% 65.40% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9287 34.04% 99.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 82 0.30% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 48 0.18% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 4 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 27280 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2381232620 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.574632 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.494399 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1012901000 42.54% 42.54% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1368331620 57.46% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2381232620 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 22714 83.27% 83.27% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.73% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 27276 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31142 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 31190 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 31190 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4602 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22894 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 2 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 31188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 31188 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 31188 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 27498 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23439.468325 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 20168.956165 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13617.892423 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 27307 99.31% 99.31% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 167 0.61% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 10 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 9 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 27498 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2364440120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.573010 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.494641 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1009591500 42.70% 42.70% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1354848620 57.30% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2364440120 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 22894 83.26% 83.26% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 4602 16.74% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 27496 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31190 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31142 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27276 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31190 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27496 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27276 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 58418 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 58686 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 20762749 # DTB read hits -system.cpu1.dtb.read_misses 23873 # DTB read misses -system.cpu1.dtb.write_hits 18763804 # DTB write hits -system.cpu1.dtb.write_misses 7269 # DTB write misses +system.cpu1.dtb.read_hits 20771010 # DTB read hits +system.cpu1.dtb.read_misses 23692 # DTB read misses +system.cpu1.dtb.write_hits 18692480 # DTB write hits +system.cpu1.dtb.write_misses 7498 # DTB write misses system.cpu1.dtb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 17777 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 5140 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 17937 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 955 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1005 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 2493 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 20786622 # DTB read accesses -system.cpu1.dtb.write_accesses 18771073 # DTB write accesses +system.cpu1.dtb.perms_faults 2603 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 20794702 # DTB read accesses +system.cpu1.dtb.write_accesses 18699978 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 39526553 # DTB hits -system.cpu1.dtb.misses 31142 # DTB misses -system.cpu1.dtb.accesses 39557695 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 39463490 # DTB hits +system.cpu1.dtb.misses 31190 # DTB misses +system.cpu1.dtb.accesses 39494680 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1330,154 +1332,155 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 19936 # Table walker walks requested -system.cpu1.itb.walker.walksLong 19936 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 932 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17656 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 19936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 19936 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 19936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 18588 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 27393.103077 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24671.512984 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13247.215063 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 10003 53.81% 53.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 8429 45.35% 99.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 57 0.31% 99.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 80 0.43% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 18588 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 19592 # Table walker walks requested +system.cpu1.itb.walker.walksLong 19592 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 942 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17338 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 19592 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 19592 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 19592 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 18280 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26364.633479 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23452.518551 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 14371.838603 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 10663 58.33% 58.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 7451 40.76% 99.09% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 65 0.36% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 75 0.41% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 1 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 7 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 18280 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 17656 94.99% 94.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 932 5.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 18588 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 17338 94.85% 94.85% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 942 5.15% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 18280 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 19936 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 19936 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 19592 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 19592 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18588 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18588 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 38524 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 110162476 # ITB inst hits -system.cpu1.itb.inst_misses 19936 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18280 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 37872 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 110580623 # ITB inst hits +system.cpu1.itb.inst_misses 19592 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 5192 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 138 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 13192 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 5140 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 135 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 13235 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 110182412 # ITB inst accesses -system.cpu1.itb.hits 110162476 # DTB hits -system.cpu1.itb.misses 19936 # DTB misses -system.cpu1.itb.accesses 110182412 # DTB accesses -system.cpu1.numPwrStateTransitions 6038 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 3019 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 4031562886.362703 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 205285027256.597076 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 926 30.67% 30.67% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 69.23% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 110600215 # ITB inst accesses +system.cpu1.itb.hits 110580623 # DTB hits +system.cpu1.itb.misses 19592 # DTB misses +system.cpu1.itb.accesses 110600215 # DTB accesses +system.cpu1.numPwrStateTransitions 6016 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 3008 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 4046290699.440825 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 205659188461.921204 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 915 30.42% 30.42% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 2090 69.48% 99.90% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.03% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.97% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 1 0.03% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 11261576634501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 3019 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 39144972847071 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171288353929 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 1182097366 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 11261531014001 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 3008 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 39145033266082 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 12171242423918 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 1182100228 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 110088686 # Number of instructions committed -system.cpu1.committedOps 129237809 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 118887794 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 113577 # Number of float alu accesses -system.cpu1.num_func_calls 6597658 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 16662523 # number of instructions that are conditional controls -system.cpu1.num_int_insts 118887794 # number of integer instructions -system.cpu1.num_fp_insts 113577 # number of float instructions -system.cpu1.num_int_register_reads 170702989 # number of times the integer registers were read -system.cpu1.num_int_register_writes 94155610 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 183331 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 96228 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 28150227 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 28060459 # number of times the CC registers were written -system.cpu1.num_mem_refs 39523640 # number of memory refs -system.cpu1.num_load_insts 20761578 # Number of load instructions -system.cpu1.num_store_insts 18762062 # Number of store instructions -system.cpu1.num_idle_cycles 1155305857.273267 # Number of idle cycles -system.cpu1.num_busy_cycles 26791508.726733 # Number of busy cycles -system.cpu1.not_idle_fraction 0.022664 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.977336 # Percentage of idle cycles -system.cpu1.Branches 24572277 # Number of branches fetched +system.cpu1.committedInsts 110507936 # Number of instructions committed +system.cpu1.committedOps 129543713 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 119008832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 107333 # Number of float alu accesses +system.cpu1.num_func_calls 6516685 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 16787846 # number of instructions that are conditional controls +system.cpu1.num_int_insts 119008832 # number of integer instructions +system.cpu1.num_fp_insts 107333 # number of float instructions +system.cpu1.num_int_register_reads 172055074 # number of times the integer registers were read +system.cpu1.num_int_register_writes 94356642 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 176403 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 83340 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 28608279 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 28519816 # number of times the CC registers were written +system.cpu1.num_mem_refs 39460487 # number of memory refs +system.cpu1.num_load_insts 20769710 # Number of load instructions +system.cpu1.num_store_insts 18690777 # Number of store instructions +system.cpu1.num_idle_cycles 1155308161.927193 # Number of idle cycles +system.cpu1.num_busy_cycles 26792066.072807 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022665 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977335 # Percentage of idle cycles +system.cpu1.Branches 24662743 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 89498355 69.21% 69.21% # Class of executed instruction -system.cpu1.op_class::IntMult 266792 0.21% 69.42% # Class of executed instruction -system.cpu1.op_class::IntDiv 10604 0.01% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 12166 0.01% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::MemRead 20761578 16.06% 85.49% # Class of executed instruction -system.cpu1.op_class::MemWrite 18762062 14.51% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 89857347 69.33% 69.33% # Class of executed instruction +system.cpu1.op_class::IntMult 277190 0.21% 69.54% # Class of executed instruction +system.cpu1.op_class::IntDiv 11015 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 10320 0.01% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction +system.cpu1.op_class::MemRead 20769710 16.02% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 18690777 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 129311599 # Class of executed instruction -system.cpu2.branchPred.lookups 40882537 # Number of BP lookups -system.cpu2.branchPred.condPredicted 28404958 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 2018640 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 29949697 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 20329283 # Number of BTB hits +system.cpu1.op_class::total 129616400 # Class of executed instruction +system.cpu2.branchPred.lookups 40854703 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28349635 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 2013069 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 29873482 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 20268490 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 67.878092 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4945381 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 329320 # Number of incorrect RAS predictions. -system.cpu2.branchPred.indirectLookups 1144842 # Number of indirect predictor lookups. -system.cpu2.branchPred.indirectHits 797183 # Number of indirect target hits. -system.cpu2.branchPred.indirectMisses 347659 # Number of indirect misses. -system.cpu2.branchPredindirectMispredicted 143486 # Number of mispredicted indirect branches. -system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu2.branchPred.BTBHitPct 67.847765 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4987413 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 331344 # Number of incorrect RAS predictions. +system.cpu2.branchPred.indirectLookups 1163100 # Number of indirect predictor lookups. +system.cpu2.branchPred.indirectHits 806401 # Number of indirect target hits. +system.cpu2.branchPred.indirectMisses 356699 # Number of indirect misses. +system.cpu2.branchPredindirectMispredicted 146740 # Number of mispredicted indirect branches. +system.cpu2.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1507,66 +1510,66 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu2.dtb.walker.walks 93219 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 93219 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7034 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30340 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 93219 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 93219 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 93219 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 37374 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 25165.904104 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 22274.336205 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 12675.748220 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-32767 24476 65.49% 65.49% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12701 33.98% 99.47% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-98303 113 0.30% 99.78% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::98304-131071 53 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-294911 6 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.walker.walks 93799 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 93799 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7024 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30187 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 93799 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 93799 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 93799 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 37211 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 23608.785037 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 20477.524093 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 12702.189700 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-32767 25796 69.32% 69.32% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-65535 11234 30.19% 99.51% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-98303 97 0.26% 99.77% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::98304-131071 57 0.15% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-163839 1 0.00% 99.93% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::163840-196607 11 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 37374 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 37211 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000359000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000359000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000359000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 30340 81.18% 81.18% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 7034 18.82% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 37374 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93219 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 30187 81.12% 81.12% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 7024 18.88% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 37211 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93799 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93219 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37374 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93799 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37211 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37374 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 130593 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37211 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 131010 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 28583495 # DTB read hits -system.cpu2.dtb.read_misses 77825 # DTB read misses -system.cpu2.dtb.write_hits 25112772 # DTB write hits -system.cpu2.dtb.write_misses 15394 # DTB write misses -system.cpu2.dtb.flush_tlb 1182 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 28529245 # DTB read hits +system.cpu2.dtb.read_misses 78357 # DTB read misses +system.cpu2.dtb.write_hits 25227275 # DTB write hits +system.cpu2.dtb.write_misses 15442 # DTB write misses +system.cpu2.dtb.flush_tlb 1183 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 22760 # Number of entries that have been flushed from TLB +system.cpu2.dtb.flush_tlb_mva_asid 7123 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 191 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 22552 # Number of entries that have been flushed from TLB system.cpu2.dtb.align_faults 83 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 2252 # Number of TLB faults due to prefetch +system.cpu2.dtb.prefetch_faults 2182 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 3984 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 28661320 # DTB read accesses -system.cpu2.dtb.write_accesses 25128166 # DTB write accesses +system.cpu2.dtb.perms_faults 3958 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 28607602 # DTB read accesses +system.cpu2.dtb.write_accesses 25242717 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 53696267 # DTB hits -system.cpu2.dtb.misses 93219 # DTB misses -system.cpu2.dtb.accesses 53789486 # DTB accesses -system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu2.dtb.hits 53756520 # DTB hits +system.cpu2.dtb.misses 93799 # DTB misses +system.cpu2.dtb.accesses 53850319 # DTB accesses +system.cpu2.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1596,149 +1599,147 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu2.itb.walker.walks 27359 # Table walker walks requested -system.cpu2.itb.walker.walksLong 27359 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1819 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22616 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 27359 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 27359 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 27359 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 24435 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 28370.002046 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 25752.666599 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 13391.544423 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 12572 51.45% 51.45% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 11615 47.53% 98.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 92 0.38% 99.36% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 132 0.54% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.91% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 9 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 5 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu2.itb.walker.walks 27208 # Table walker walks requested +system.cpu2.itb.walker.walksLong 27208 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1843 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22528 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 27208 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 27208 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 27208 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 24371 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 26858.233146 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 23932.181675 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 13621.050617 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 13667 56.08% 56.08% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 10461 42.92% 99.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 87 0.36% 99.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 133 0.55% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 12 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 1 0.00% 99.97% # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walkCompletionTime::229376-262143 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 24435 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 24371 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000327000 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000327000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000327000 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 22616 92.56% 92.56% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 1819 7.44% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 24435 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 22528 92.44% 92.44% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 1843 7.56% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 24371 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27359 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27359 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27208 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27208 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24435 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24435 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 51794 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70751081 # ITB inst hits -system.cpu2.itb.inst_misses 27359 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24371 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24371 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 51579 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70683304 # ITB inst hits +system.cpu2.itb.inst_misses 27208 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1182 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1183 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 7038 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 188 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 17251 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 7123 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 191 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 16893 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 50621 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 51118 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70778440 # ITB inst accesses -system.cpu2.itb.hits 70751081 # DTB hits -system.cpu2.itb.misses 27359 # DTB misses -system.cpu2.itb.accesses 70778440 # DTB accesses -system.cpu2.numPwrStateTransitions 7068 # Number of power state transitions -system.cpu2.pwrStateClkGateDist::samples 3534 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::mean 14278760224.142614 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::stdev 128952650694.550415 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::underflows 1173 33.19% 33.19% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1000-5e+10 2324 65.76% 98.95% # Distribution of time spent in the clock gated state +system.cpu2.itb.inst_accesses 70710512 # ITB inst accesses +system.cpu2.itb.hits 70683304 # DTB hits +system.cpu2.itb.misses 27208 # DTB misses +system.cpu2.itb.accesses 70710512 # DTB accesses +system.cpu2.numPwrStateTransitions 7024 # Number of power state transitions +system.cpu2.pwrStateClkGateDist::samples 3512 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::mean 14368150694.236048 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::stdev 129350965742.418961 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::underflows 1152 32.80% 32.80% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1000-5e+10 2323 66.14% 98.95% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+10-1e+11 6 0.17% 99.12% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 3 0.08% 99.21% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::1e+11-1.5e+11 3 0.09% 99.20% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::1.5e+11-2e+11 2 0.06% 99.26% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::2e+11-2.5e+11 2 0.06% 99.32% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.38% # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.41% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::2.5e+11-3e+11 2 0.06% 99.37% # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::3e+11-3.5e+11 1 0.03% 99.40% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::4.5e+11-5e+11 1 0.03% 99.43% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::5e+11-5.5e+11 1 0.03% 99.46% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::7e+11-7.5e+11 1 0.03% 99.49% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::overflows 18 0.51% 100.00% # Distribution of time spent in the clock gated state system.cpu2.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::max_value 1988791938500 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateClkGateDist::total 3534 # Distribution of time spent in the clock gated state -system.cpu2.pwrStateResidencyTicks::ON 855122568880 # Cumulative time (in ticks) in various power states -system.cpu2.pwrStateResidencyTicks::CLK_GATED 50461138632120 # Cumulative time (in ticks) in various power states -system.cpu2.numCycles 1176514820 # number of cpu cycles simulated +system.cpu2.pwrStateClkGateDist::max_value 1988791978000 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateClkGateDist::total 3512 # Distribution of time spent in the clock gated state +system.cpu2.pwrStateResidencyTicks::ON 855330451843 # Cumulative time (in ticks) in various power states +system.cpu2.pwrStateResidencyTicks::CLK_GATED 50460945238157 # Cumulative time (in ticks) in various power states +system.cpu2.numCycles 1176516719 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 148015275 # Number of instructions committed -system.cpu2.committedOps 173576253 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 15019689 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 1599 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 5679254 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 7.948604 # CPI: cycles per instruction -system.cpu2.ipc 0.125808 # IPC: instructions per cycle +system.cpu2.committedInsts 147979887 # Number of instructions committed +system.cpu2.committedOps 173747082 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 15034502 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 1577 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 5675627 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 7.950518 # CPI: cycles per instruction +system.cpu2.ipc 0.125778 # IPC: instructions per cycle system.cpu2.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.op_class_0::IntAlu 120466035 69.40% 69.40% # Class of committed instruction -system.cpu2.op_class_0::IntMult 363809 0.21% 69.61% # Class of committed instruction -system.cpu2.op_class_0::IntDiv 14931 0.01% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMisc 14962 0.01% 69.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction -system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction -system.cpu2.op_class_0::MemRead 27697831 15.96% 85.59% # Class of committed instruction -system.cpu2.op_class_0::MemWrite 25018685 14.41% 100.00% # Class of committed instruction +system.cpu2.op_class_0::IntAlu 120575025 69.40% 69.40% # Class of committed instruction +system.cpu2.op_class_0::IntMult 357276 0.21% 69.60% # Class of committed instruction +system.cpu2.op_class_0::IntDiv 14709 0.01% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMisc 16361 0.01% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction +system.cpu2.op_class_0::MemRead 27648708 15.91% 85.53% # Class of committed instruction +system.cpu2.op_class_0::MemWrite 25135003 14.47% 100.00% # Class of committed instruction system.cpu2.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.op_class_0::total 173576253 # Class of committed instruction +system.cpu2.op_class_0::total 173747082 # Class of committed instruction system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 278505998 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 898008822 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 76056401 # Number of BP lookups -system.cpu3.branchPred.condPredicted 50755289 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 3415271 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 50793125 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 34573256 # Number of BTB hits +system.cpu2.tickCycles 278731731 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 897784988 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 76144884 # Number of BP lookups +system.cpu3.branchPred.condPredicted 50917651 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 3425676 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 51078726 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 34631446 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 68.066802 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 9840520 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 107050 # Number of incorrect RAS predictions. -system.cpu3.branchPred.indirectLookups 3054055 # Number of indirect predictor lookups. -system.cpu3.branchPred.indirectHits 1548215 # Number of indirect target hits. -system.cpu3.branchPred.indirectMisses 1505840 # Number of indirect misses. -system.cpu3.branchPredindirectMispredicted 248236 # Number of mispredicted indirect branches. -system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu3.branchPred.BTBHitPct 67.800137 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 9824308 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 106925 # Number of incorrect RAS predictions. +system.cpu3.branchPred.indirectLookups 2992006 # Number of indirect predictor lookups. +system.cpu3.branchPred.indirectHits 1537953 # Number of indirect target hits. +system.cpu3.branchPred.indirectMisses 1454053 # Number of indirect misses. +system.cpu3.branchPredindirectMispredicted 245625 # Number of mispredicted indirect branches. +system.cpu3.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1768,95 +1769,89 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu3.dtb.walker.walks 519832 # Table walker walks requested -system.cpu3.dtb.walker.walksLong 519832 # Table walker walks initiated with long descriptors -system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8563 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50762 # Level at which table walker walks with long descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 324579 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 195253 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 2247.443061 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 12961.897479 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-32767 191171 97.91% 97.91% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-65535 2882 1.48% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-98303 501 0.26% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::98304-131071 350 0.18% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::131072-163839 155 0.08% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::163840-196607 49 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::196608-229375 39 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::229376-262143 21 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::262144-294911 33 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::294912-327679 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::327680-360447 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::360448-393215 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::393216-425983 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::425984-458751 14 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 195253 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 240674 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 22283.310619 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 18185.362858 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 16504.392629 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-65535 236088 98.09% 98.09% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::65536-131071 4155 1.73% 99.82% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::131072-196607 185 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::196608-262143 125 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::262144-327679 40 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::327680-393215 50 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::393216-458751 22 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 240674 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -21483315588 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 0.617433 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-3 -22069775588 102.73% 102.73% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-7 326975000 -1.52% 101.21% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-11 109953500 -0.51% 100.70% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-15 66787000 -0.31% 100.39% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-19 27414500 -0.13% 100.26% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-23 14643500 -0.07% 100.19% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-27 14038500 -0.07% 100.12% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-31 22874000 -0.11% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::32-35 3351000 -0.02% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::36-39 112000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::40-43 25000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::44-47 22000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::48-51 17000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::52-55 205500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::56-59 41500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -21483315588 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 50762 85.57% 85.57% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::2M 8563 14.43% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 59325 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 519832 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.walker.walks 512874 # Table walker walks requested +system.cpu3.dtb.walker.walksLong 512874 # Table walker walks initiated with long descriptors +system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8606 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 51328 # Level at which table walker walks with long descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 316923 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 195951 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 2195.235033 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 13338.016362 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-65535 194716 99.37% 99.37% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-131071 870 0.44% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::131072-196607 208 0.11% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::196608-262143 62 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::327680-393215 18 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::393216-458751 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::total 195951 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 235338 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 21271.290654 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 17097.378529 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 15945.708212 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-32767 189296 80.44% 80.44% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-65535 41383 17.58% 98.02% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3580 1.52% 99.54% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::98304-131071 595 0.25% 99.79% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::131072-163839 139 0.06% 99.85% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::163840-196607 148 0.06% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::196608-229375 80 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::229376-262143 73 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::262144-294911 24 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::327680-360447 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::360448-393215 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 235338 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -21468826588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.564464 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-3 -22023506588 102.58% 102.58% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-7 315278500 -1.47% 101.12% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-11 105205000 -0.49% 100.63% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-15 64047000 -0.30% 100.33% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-19 24089000 -0.11% 100.21% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-23 11371500 -0.05% 100.16% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-27 12408500 -0.06% 100.10% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-31 18570000 -0.09% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::32-35 3540000 -0.02% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::36-39 163500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::40-43 7000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -21468826588 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 51328 85.64% 85.64% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::2M 8606 14.36% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 59934 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 512874 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 519832 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59325 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 512874 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59934 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59325 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 579157 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59934 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 572808 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 59705170 # DTB read hits -system.cpu3.dtb.read_misses 356680 # DTB read misses -system.cpu3.dtb.write_hits 46676545 # DTB write hits -system.cpu3.dtb.write_misses 163152 # DTB write misses -system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed +system.cpu3.dtb.read_hits 59857088 # DTB read hits +system.cpu3.dtb.read_misses 352696 # DTB read misses +system.cpu3.dtb.write_hits 46573459 # DTB write hits +system.cpu3.dtb.write_misses 160178 # DTB write misses +system.cpu3.dtb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.dtb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID -system.cpu3.dtb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 29163 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 78 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 4872 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_tlb_mva_asid 11696 # Number of times TLB was flushed by MVA & ASID +system.cpu3.dtb.flush_tlb_asid 295 # Number of times TLB was flushed by ASID +system.cpu3.dtb.flush_entries 29518 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 76 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 5036 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 30504 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 60061850 # DTB read accesses -system.cpu3.dtb.write_accesses 46839697 # DTB write accesses +system.cpu3.dtb.perms_faults 30761 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 60209784 # DTB read accesses +system.cpu3.dtb.write_accesses 46733637 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 106381715 # DTB hits -system.cpu3.dtb.misses 519832 # DTB misses -system.cpu3.dtb.accesses 106901547 # DTB accesses -system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.cpu3.dtb.hits 106430547 # DTB hits +system.cpu3.dtb.misses 512874 # DTB misses +system.cpu3.dtb.accesses 106943421 # DTB accesses +system.cpu3.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1886,393 +1881,401 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.cpu3.itb.walker.walks 58984 # Table walker walks requested -system.cpu3.itb.walker.walksLong 58984 # Table walker walks initiated with long descriptors -system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2019 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40730 # Level at which table walker walks with long descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 8213 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 50771 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1255.214591 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7667.557499 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-32767 50302 99.08% 99.08% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-65535 327 0.64% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-98303 93 0.18% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-131071 33 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::163840-196607 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.cpu3.itb.walker.walks 59319 # Table walker walks requested +system.cpu3.itb.walker.walksLong 59319 # Table walker walks initiated with long descriptors +system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2009 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40532 # Level at which table walker walks with long descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 8154 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 51165 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1195.836998 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 7646.415303 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-32767 50755 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-65535 251 0.49% 99.69% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-98303 94 0.18% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::98304-131071 39 0.08% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::131072-163839 13 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::163840-196607 9 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::196608-229375 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 50771 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkCompletionTime::samples 50962 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 27876.584514 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 23887.788397 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 16739.526598 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-65535 49958 98.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::65536-131071 889 1.74% 99.77% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::131072-196607 72 0.14% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::196608-262143 26 0.05% 99.97% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::262144-327679 9 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::total 50962 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -21485924088 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 1.063775 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 1402683284 -6.53% -6.53% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -22917683872 106.66% 100.14% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 26044500 -0.12% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 2758500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 237000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 36500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -21485924088 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 40730 95.28% 95.28% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::2M 2019 4.72% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 42749 # Table walker page sizes translated +system.cpu3.itb.walker.walkWaitTime::total 51165 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkCompletionTime::samples 50695 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 26787.010553 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 22469.536393 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 17840.810022 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-32767 30103 59.38% 59.38% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-65535 19510 38.49% 97.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::65536-98303 511 1.01% 98.87% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::98304-131071 427 0.84% 99.72% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::131072-163839 38 0.07% 99.79% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::163840-196607 57 0.11% 99.90% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::196608-229375 19 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::262144-294911 8 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::total 50695 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walksPending::samples -25766386884 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.899092 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.296211 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -2567658104 9.97% 9.97% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -23226705280 90.14% 100.11% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 24531500 -0.10% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 2936500 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 267500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::5 75500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::6 120000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::7 45500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -25766386884 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 40532 95.28% 95.28% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::2M 2009 4.72% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 42541 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 58984 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 58984 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59319 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59319 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42749 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42749 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 101733 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 54309249 # ITB inst hits -system.cpu3.itb.inst_misses 58984 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42541 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42541 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 101860 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 54449151 # ITB inst hits +system.cpu3.itb.inst_misses 59319 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed +system.cpu3.itb.flush_tlb 1182 # Number of times complete TLB was flushed system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu3.itb.flush_tlb_mva_asid 11749 # Number of times TLB was flushed by MVA & ASID -system.cpu3.itb.flush_tlb_asid 293 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 22226 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_tlb_mva_asid 11696 # Number of times TLB was flushed by MVA & ASID +system.cpu3.itb.flush_tlb_asid 295 # Number of times TLB was flushed by ASID +system.cpu3.itb.flush_entries 22325 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 110359 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 110276 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 54368233 # ITB inst accesses -system.cpu3.itb.hits 54309249 # DTB hits -system.cpu3.itb.misses 58984 # DTB misses -system.cpu3.itb.accesses 54368233 # DTB accesses -system.cpu3.numPwrStateTransitions 7050 # Number of power state transitions -system.cpu3.pwrStateClkGateDist::samples 3525 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::mean 48150318.502695 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::stdev 1097902153.303432 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::underflows 2138 60.65% 60.65% # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::1000-5e+10 1387 39.35% 100.00% # Distribution of time spent in the clock gated state +system.cpu3.itb.inst_accesses 54508470 # ITB inst accesses +system.cpu3.itb.hits 54449151 # DTB hits +system.cpu3.itb.misses 59319 # DTB misses +system.cpu3.itb.accesses 54508470 # DTB accesses +system.cpu3.numPwrStateTransitions 7056 # Number of power state transitions +system.cpu3.pwrStateClkGateDist::samples 3528 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::mean 48263626.625000 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::stdev 1100096495.861649 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::underflows 2141 60.69% 60.69% # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::1000-5e+10 1387 39.31% 100.00% # Distribution of time spent in the clock gated state system.cpu3.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::max_value 36013437604 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateClkGateDist::total 3525 # Distribution of time spent in the clock gated state -system.cpu3.pwrStateResidencyTicks::ON 51146531328278 # Cumulative time (in ticks) in various power states -system.cpu3.pwrStateResidencyTicks::CLK_GATED 169729872722 # Cumulative time (in ticks) in various power states -system.cpu3.numCycles 361675800 # number of cpu cycles simulated +system.cpu3.pwrStateClkGateDist::max_value 36012902604 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateClkGateDist::total 3528 # Distribution of time spent in the clock gated state +system.cpu3.pwrStateResidencyTicks::ON 51146001615267 # Cumulative time (in ticks) in various power states +system.cpu3.pwrStateResidencyTicks::CLK_GATED 170274074733 # Cumulative time (in ticks) in various power states +system.cpu3.numCycles 360624311 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 142734990 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 337553362 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 76056401 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 45961991 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 197659540 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 7720824 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 1399327 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 5628 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 1517 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 2684967 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 90171 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 3829 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 54181818 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 2125134 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 22298 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 348440253 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.132379 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.378502 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 142734409 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 337961407 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 76144884 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45993707 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 196711593 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 7739189 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 1372744 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 5006 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 1830 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 2692575 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 88196 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 3852 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 54321925 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 2128480 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 22518 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 347479672 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.136573 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.381700 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 265738138 76.27% 76.27% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 10408686 2.99% 79.25% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 10350946 2.97% 82.22% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 7718330 2.22% 84.44% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 15611358 4.48% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 5061575 1.45% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 5537323 1.59% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 4787480 1.37% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 23226417 6.67% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 264664577 76.17% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 10448751 3.01% 79.17% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 10389657 2.99% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 7726776 2.22% 84.39% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 15569597 4.48% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 5085732 1.46% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 5566487 1.60% 91.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 4803146 1.38% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 23224949 6.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 348440253 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.210289 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.933304 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 116402482 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 160353660 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 61341979 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7283918 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 3056510 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 11212857 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 815162 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 368532981 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 2520228 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 3056510 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 120624207 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 11509026 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 131064171 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 64320905 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 17863677 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 359702121 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 43833 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 968665 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 780315 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 7689356 # Number of times rename has blocked due to SQ full -system.cpu3.rename.FullRegisterEvents 2098 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 342552995 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 547002223 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 423527131 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 526597 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 286388562 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 56164428 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 8049002 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 6906783 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 40039981 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 58078564 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 48988354 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 7585006 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 8037000 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 341408601 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8081994 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 340240717 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 497823 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 47426361 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 29768333 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 191877 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 348440253 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.976468 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.690233 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 347479672 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.211147 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.937156 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 116319092 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 159338087 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 61493208 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7257195 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 3070348 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 11216097 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 810528 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 368877230 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 2502393 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 3070348 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 120537316 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 11607372 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 129961960 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 64445904 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 17854957 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 360009684 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 40582 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 995330 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 792465 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 7726817 # Number of times rename has blocked due to SQ full +system.cpu3.rename.FullRegisterEvents 2104 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 342963420 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 547080576 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 423978365 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 517857 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 286215822 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 56747593 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 7972839 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 6835897 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 39855447 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 58319848 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 48888042 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 7618365 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 8042184 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 341704043 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8022599 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 340232336 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 497337 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 47823760 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 30164946 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 192380 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 347479672 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.979143 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.691890 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 216890475 62.25% 62.25% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 53877096 15.46% 77.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 24807816 7.12% 84.83% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 17922235 5.14% 89.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 13075143 3.75% 93.72% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 9287871 2.67% 96.39% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 6359964 1.83% 98.22% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 3675651 1.05% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 2544002 0.73% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 216057167 62.18% 62.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 53646928 15.44% 77.62% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 24868918 7.16% 84.77% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 17968855 5.17% 89.95% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 13078366 3.76% 93.71% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 9279622 2.67% 96.38% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 6367435 1.83% 98.21% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 3674225 1.06% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2538156 0.73% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 348440253 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 347479672 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 1734447 26.04% 26.04% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 17043 0.26% 26.30% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 1093 0.02% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.31% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 2643216 39.68% 66.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 2264697 34.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 1739394 26.12% 26.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 17216 0.26% 26.38% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 1075 0.02% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.40% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 2643113 39.69% 66.09% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 2258125 33.91% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 231030792 67.90% 67.90% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 845869 0.25% 68.15% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 38944 0.01% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 198 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 42651 0.01% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 61002567 17.93% 86.10% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 47279686 13.90% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 5 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 230928850 67.87% 67.87% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 888251 0.26% 68.13% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 40201 0.01% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 204 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 42408 0.01% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 61160195 17.98% 86.14% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 47172222 13.86% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 340240717 # Type of FU issued -system.cpu3.iq.rate 0.940734 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 6660496 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.019576 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 1035420885 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 396967626 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 327898797 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 659121 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 337856 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 293479 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 346548979 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 352224 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 2687529 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 340232336 # Type of FU issued +system.cpu3.iq.rate 0.943454 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 6658923 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.019572 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 1034449548 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 397601121 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 327921647 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 651056 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 333937 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 289983 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 346543457 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 347797 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 2684612 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 9720232 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 11871 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 394856 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 4837016 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 9848030 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 12099 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 390855 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 4852885 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 2125891 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 3923806 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 2121686 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 3886704 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 3056510 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 7986555 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 2673304 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 349575098 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 1017291 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 58078564 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 48988354 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 6756692 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 121038 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 2506923 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 394856 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 1446513 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1609649 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 3056162 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 336167665 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 59696171 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 3560031 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 3070348 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8044361 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 2703635 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 349811697 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 1019337 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 58319848 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 48888042 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 6684338 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 123262 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 2534169 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 390855 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 1464138 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1603865 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 3068003 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 336172243 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 59848506 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 3553985 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 84503 # number of nop insts executed -system.cpu3.iew.exec_refs 106371515 # number of memory reference insts executed -system.cpu3.iew.exec_branches 62288679 # Number of branches executed -system.cpu3.iew.exec_stores 46675344 # Number of stores executed -system.cpu3.iew.exec_rate 0.929472 # Inst execution rate -system.cpu3.iew.wb_sent 329005088 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 328192276 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 162018804 # num instructions producing a value -system.cpu3.iew.wb_consumers 281033502 # num instructions consuming a value -system.cpu3.iew.wb_rate 0.907421 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.576511 # average fanout of values written-back -system.cpu3.commit.commitSquashedInsts 47454465 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7890117 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 2611241 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 340404707 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.887368 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.879512 # Number of insts commited each cycle +system.cpu3.iew.exec_nop 85055 # number of nop insts executed +system.cpu3.iew.exec_refs 106421072 # number of memory reference insts executed +system.cpu3.iew.exec_branches 62316621 # Number of branches executed +system.cpu3.iew.exec_stores 46572566 # Number of stores executed +system.cpu3.iew.exec_rate 0.932195 # Inst execution rate +system.cpu3.iew.wb_sent 329026261 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 328211630 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 162144042 # num instructions producing a value +system.cpu3.iew.wb_consumers 281134898 # num instructions consuming a value +system.cpu3.iew.wb_rate 0.910121 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.576748 # average fanout of values written-back +system.cpu3.commit.commitSquashedInsts 47849721 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7830219 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 2626302 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 339381548 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.889568 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.882377 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 230935782 67.84% 67.84% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 52807469 15.51% 83.35% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 18991951 5.58% 88.93% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8773061 2.58% 91.51% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 6429800 1.89% 93.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 3748451 1.10% 94.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 3528982 1.04% 95.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 2195360 0.64% 96.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 12993851 3.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 230141242 67.81% 67.81% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 52578609 15.49% 83.30% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 18989562 5.60% 88.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8770494 2.58% 91.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 6420925 1.89% 93.38% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 3757747 1.11% 94.48% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 3513397 1.04% 95.52% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 2195731 0.65% 96.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 13013841 3.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 340404707 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 257000704 # Number of instructions committed -system.cpu3.commit.committedOps 302064229 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 339381548 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 256941031 # Number of instructions committed +system.cpu3.commit.committedOps 301902877 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 92509669 # Number of memory references committed -system.cpu3.commit.loads 48358331 # Number of loads committed -system.cpu3.commit.membars 2078465 # Number of memory barriers committed -system.cpu3.commit.branches 57378073 # Number of branches committed -system.cpu3.commit.fp_insts 281556 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 277690269 # Number of committed integer instructions. -system.cpu3.commit.function_calls 7642177 # Number of function calls committed. +system.cpu3.commit.refs 92506974 # Number of memory references committed +system.cpu3.commit.loads 48471817 # Number of loads committed +system.cpu3.commit.membars 2097304 # Number of memory barriers committed +system.cpu3.commit.branches 57364518 # Number of branches committed +system.cpu3.commit.fp_insts 278173 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 277550130 # Number of committed integer instructions. +system.cpu3.commit.function_calls 7627094 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 208831181 69.13% 69.13% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 657786 0.22% 69.35% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 28932 0.01% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 36661 0.01% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 48358331 16.01% 85.38% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 44151338 14.62% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 208647320 69.11% 69.11% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 682317 0.23% 69.34% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 29904 0.01% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 36362 0.01% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.36% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 48471817 16.06% 85.41% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 44035157 14.59% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 302064229 # Class of committed instruction -system.cpu3.commit.bw_lim_events 12993851 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 674816220 # The number of ROB reads -system.cpu3.rob.rob_writes 707084678 # The number of ROB writes -system.cpu3.timesIdled 2433054 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 13235547 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 98724531811 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 257000704 # Number of Instructions Simulated -system.cpu3.committedOps 302064229 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.407295 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.407295 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.710583 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.710583 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 395540710 # number of integer regfile reads -system.cpu3.int_regfile_writes 235084371 # number of integer regfile writes -system.cpu3.fp_regfile_reads 573493 # number of floating regfile reads -system.cpu3.fp_regfile_writes 349924 # number of floating regfile writes -system.cpu3.cc_regfile_reads 70842645 # number of cc regfile reads -system.cpu3.cc_regfile_writes 71511543 # number of cc regfile writes -system.cpu3.misc_regfile_reads 658562640 # number of misc regfile reads -system.cpu3.misc_regfile_writes 7924534 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40262 # Transaction distribution -system.iobus.trans_dist::ReadResp 40262 # Transaction distribution +system.cpu3.commit.op_class_0::total 301902877 # Class of committed instruction +system.cpu3.commit.bw_lim_events 13013841 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 673991782 # The number of ROB reads +system.cpu3.rob.rob_writes 707616779 # The number of ROB writes +system.cpu3.timesIdled 2425895 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 13144639 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 98725614751 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 256941031 # Number of Instructions Simulated +system.cpu3.committedOps 301902877 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.403529 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.403529 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.712489 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.712489 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 395604640 # number of integer regfile reads +system.cpu3.int_regfile_writes 235195836 # number of integer regfile writes +system.cpu3.fp_regfile_reads 565870 # number of floating regfile reads +system.cpu3.fp_regfile_writes 351196 # number of floating regfile writes +system.cpu3.cc_regfile_reads 70807437 # number of cc regfile reads +system.cpu3.cc_regfile_writes 71493240 # number of cc regfile writes +system.cpu3.misc_regfile_reads 657110629 # number of misc regfile reads +system.cpu3.misc_regfile_writes 7862543 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40272 # Transaction distribution +system.iobus.trans_dist::ReadResp 40272 # Transaction distribution system.iobus.trans_dist::WriteReq 136539 # Transaction distribution system.iobus.trans_dist::WriteResp 136539 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) @@ -2289,11 +2292,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230966 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230966 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353602 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353622 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -2308,22 +2311,22 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334296 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334296 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492008 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13479500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13499000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 5500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 17500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -2335,68 +2338,68 @@ system.iobus.reqLayer16.occupancy 5000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 10717000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 10442000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 21643000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 21712500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 229106103 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 227539905 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 40091000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39848000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 47420000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 45034000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.425438 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115465 # number of replacements +system.iocache.tags.tagsinuse 10.425444 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13087296764009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544648 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.880790 # Average occupied blocks per requestor +system.iocache.tags.warmup_cycle 13087293844009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544651 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.880792 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.221541 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430049 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430050 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.651590 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039614 # Number of tag accesses -system.iocache.tags.data_accesses 1039614 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039704 # Number of tag accesses +system.iocache.tags.data_accesses 1039704 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8819 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8856 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115473 # number of demand (read+write) misses -system.iocache.demand_misses::total 115513 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115483 # number of demand (read+write) misses +system.iocache.demand_misses::total 115523 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115473 # number of overall misses -system.iocache.overall_misses::total 115513 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 148237434 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 148237434 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 5184314669 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 5184314669 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 5332552103 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 5332552103 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 5332552103 # number of overall miss cycles -system.iocache.overall_miss_latency::total 5332552103 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 115483 # number of overall misses +system.iocache.overall_misses::total 115523 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 61770218 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 61770218 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 5167926687 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 5167926687 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 5229696905 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 5229696905 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 5229696905 # number of overall miss cycles +system.iocache.overall_miss_latency::total 5229696905 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8819 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8856 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115473 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115513 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115483 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115523 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115473 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115513 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115483 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115523 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2410,861 +2413,862 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 16827.952549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 16757.566584 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48604.165126 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 48604.165126 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 46164.086319 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 46180.077620 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 46164.086319 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 2296 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 7004.220206 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 6974.956865 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 48450.523954 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 48450.523954 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 45285.426470 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 45269.746328 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 45285.426470 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 45269.746328 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 417 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 267 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 40 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.599251 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.425000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::realview.ide 43872 # number of WriteLineReq MSHR misses -system.iocache.WriteLineReq_mshr_misses::total 43872 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 44782 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 44782 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 44782 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 44782 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 102737434 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 102737434 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2987814984 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2987814984 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 3090552418 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 3090552418 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 3090552418 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 3090552418 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.103303 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.102871 # mshr miss rate for ReadReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.411310 # mshr miss rate for WriteLineReq accesses -system.iocache.WriteLineReq_mshr_miss_rate::total 0.411310 # mshr miss rate for WriteLineReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.387679 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.387814 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.387679 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 112898.279121 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 112898.279121 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68103.003829 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68103.003829 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 69013.273592 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69013.273592 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 1178177 # number of replacements -system.l2c.tags.tagsinuse 65299.544871 # Cycle average of tags in use -system.l2c.tags.total_refs 47783107 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1240954 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.505140 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36300.809857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 130.329243 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 195.620388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3095.266131 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10240.571353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 40.874592 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 51.867132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1035.336911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2451.400254 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 46.677403 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 75.693349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2509.241112 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3335.896210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 90.056966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.itb.walker 140.583636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1763.583672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 3795.736663 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.553906 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001989 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002985 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.047230 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.156259 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.015798 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.037405 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.001155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.038288 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.050902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001374 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.itb.walker 0.002145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.026910 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.057918 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996392 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 349 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62428 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 348 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 625 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2851 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5174 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53676 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005325 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.952576 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 423034153 # Number of tag accesses -system.l2c.tags.data_accesses 423034153 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 166077 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 112464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 54587 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 40813 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 152672 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 58108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 295679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 104923 # number of ReadReq hits -system.l2c.ReadReq_hits::total 985323 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7576706 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7576706 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15883082 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15883082 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 3816 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1201 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 1641 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 2839 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9497 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 631099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 192720 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 285985 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 475632 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1585436 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 5464021 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 1712423 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 3852354 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 4762402 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15791200 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 2579009 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 769324 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2.data 1050953 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3.data 1900864 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6300150 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 286592 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 87209 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu2.data 126708 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu3.data 229462 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 729971 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 166077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 112464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 5464021 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3210108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 54587 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 40813 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1712423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 962044 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 152672 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 58108 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 3852354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 1336938 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.dtb.walker 295679 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.itb.walker 104923 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 4762402 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 2376496 # number of demand (read+write) hits -system.l2c.demand_hits::total 24662109 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 166077 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 112464 # number of overall hits -system.l2c.overall_hits::cpu0.inst 5464021 # number of overall hits -system.l2c.overall_hits::cpu0.data 3210108 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 54587 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 40813 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1712423 # number of overall hits -system.l2c.overall_hits::cpu1.data 962044 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 152672 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 58108 # number of overall hits -system.l2c.overall_hits::cpu2.inst 3852354 # number of overall hits -system.l2c.overall_hits::cpu2.data 1336938 # number of overall hits -system.l2c.overall_hits::cpu3.dtb.walker 295679 # number of overall hits -system.l2c.overall_hits::cpu3.itb.walker 104923 # number of overall hits -system.l2c.overall_hits::cpu3.inst 4762402 # number of overall hits -system.l2c.overall_hits::cpu3.data 2376496 # number of overall hits -system.l2c.overall_hits::total 24662109 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1397 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1376 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 307 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 291 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 530 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 481 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.dtb.walker 1161 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.itb.walker 997 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6540 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 13913 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4659 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 5652 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 10300 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 34524 # number of UpgradeReq misses +system.iocache.ReadReq_mshr_misses::realview.ide 453 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 453 # number of ReadReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 43744 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 43744 # number of WriteLineReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 44197 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 44197 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 44197 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 44197 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 39120218 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 39120218 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2977819124 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2977819124 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 3016939342 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 3016939342 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 3016939342 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 3016939342 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.051366 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.051152 # mshr miss rate for ReadReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.410110 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 0.410110 # mshr miss rate for WriteLineReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.382714 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.382582 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.382714 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.382582 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 86358.097130 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 86358.097130 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68073.772952 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68073.772952 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68261.179311 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68261.179311 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68261.179311 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68261.179311 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 1182494 # number of replacements +system.l2c.tags.tagsinuse 65447.621193 # Cycle average of tags in use +system.l2c.tags.total_refs 49776356 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1245426 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 39.967333 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 395496000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 10450.326675 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 193.502647 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 222.666592 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3323.622390 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 21949.117178 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 56.686764 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 60.274211 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 949.191230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 6589.162943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 69.129700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 76.155286 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2308.881020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 7819.148817 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 140.556158 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.itb.walker 161.169200 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 1712.244141 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 9365.786241 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.159459 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002953 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003398 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.334917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000865 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000920 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.014484 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.100543 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001055 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.001162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.035231 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.119311 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.002145 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.itb.walker 0.002459 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.026127 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.142911 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998651 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 384 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62548 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 384 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1131 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5605 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55378 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005859 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.954407 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 420660189 # Number of tag accesses +system.l2c.tags.data_accesses 420660189 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.l2c.ReadReq_hits::cpu0.dtb.walker 148411 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 102905 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 50987 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 37863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 145669 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 53387 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78567.376900 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76493.778962 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86156.495668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 78654.645010 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169058.180058 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167139.504277 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172277.427079 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169480.164827 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88675.281812 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88326.069317 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 89096.307554 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 88701.867895 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 2714288 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1358609 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3170 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.131264 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.126485 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.144501 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.081310 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.198058 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.196303 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.191022 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.115750 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005927 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006555 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005312 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003842 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.038099 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.034659 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.035063 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021111 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.180077 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.197064 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.235847 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.099807 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.006856 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007783 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.076206 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.008524 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006555 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.074665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.004412 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.010460 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.070449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017151 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.006856 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007783 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.076206 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.008524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006555 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.074665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.004412 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.010460 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.070449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017151 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 78271.370503 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18983.402490 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 18979.299363 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 18993.907392 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18987.825716 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 47750 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 47750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71639.259480 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 72271.039815 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 90198.708570 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80746.334432 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72645.761031 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 74466.403972 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 76479.277362 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 75002.119961 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74522.093180 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 74761.883946 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 80238.463604 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 77467.290341 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18745.477595 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 19446.900432 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 20257.972444 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19806.559829 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72645.761031 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72737.176416 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 74466.403972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 73141.111182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 76479.277362 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 86366.234369 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 78876.128753 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73532.670455 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79208.754209 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72645.761031 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72737.176416 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77850.701403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 78091.503268 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 74466.403972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 73141.111182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78846.609621 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 79183.908046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 76479.277362 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 86366.234369 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 78876.128753 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169322.186942 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 167521.083679 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 172100.826626 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169640.892141 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88820.997293 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 88477.267482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 88773.283214 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 88695.776928 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2692221 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1332095 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 2857 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76739 # Transaction distribution -system.membus.trans_dist::ReadResp 446283 # Transaction distribution +system.membus.trans_dist::ReadResp 448186 # Transaction distribution system.membus.trans_dist::WriteReq 33648 # Transaction distribution system.membus.trans_dist::WriteResp 33648 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1091848 # Transaction distribution -system.membus.trans_dist::CleanEvict 200785 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35184 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1094121 # Transaction distribution +system.membus.trans_dist::CleanEvict 202838 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4443 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14271 # Transaction distribution -system.membus.trans_dist::ReadExReq 414448 # Transaction distribution -system.membus.trans_dist::ReadExResp 414448 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 369544 # Transaction distribution -system.membus.trans_dist::InvalidateReq 602468 # Transaction distribution -system.membus.trans_dist::InvalidateResp 435243 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1867 # Transaction distribution +system.membus.trans_dist::ReadExReq 416227 # Transaction distribution +system.membus.trans_dist::ReadExResp 416227 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 371447 # Transaction distribution +system.membus.trans_dist::InvalidateReq 603124 # Transaction distribution +system.membus.trans_dist::InvalidateResp 437026 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3736384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3865780 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 302176 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4167956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3707227 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3836623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 302374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 302374 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4138997 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 112845536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 113014898 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7362816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 120377714 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 603 # Total snoops (count) -system.membus.snoopTraffic 38528 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2230474 # Request fanout histogram -system.membus.snoop_fanout::mean 0.016353 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.126827 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 113227104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 113396466 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 120762482 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 546 # Total snoops (count) +system.membus.snoopTraffic 34880 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 2213347 # Request fanout histogram +system.membus.snoop_fanout::mean 0.016167 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.126119 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2194000 98.36% 98.36% # Request fanout histogram -system.membus.snoop_fanout::1 36474 1.64% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2177563 98.38% 98.38% # Request fanout histogram +system.membus.snoop_fanout::1 35784 1.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2230474 # Request fanout histogram -system.membus.reqLayer0.occupancy 45941500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2213347 # Request fanout histogram +system.membus.reqLayer0.occupancy 45757000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1601000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1572000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3279160105 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3230054159 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2368546008 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2350415750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 4606769 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 2301227 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -3307,86 +3311,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 52014816 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 26342736 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 3149 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2216 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2216 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 52031861 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 26343539 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 3136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2272 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2272 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316261201000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1497604 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23943591 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51316275690000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1497693 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23955179 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8020601 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 15885620 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2314166 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 44021 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44032 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2000482 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2000482 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 15886240 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6559913 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1231249 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1225834 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47744160 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29579701 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 811490 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1741524 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 79876875 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2033559380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1032953822 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2918064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6139128 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3075570394 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1503666 # Total snoops (count) -system.toL2Bus.snoopTraffic 65422752 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 38127714 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.016625 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.127861 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 8020839 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 15900080 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2311396 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28791 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28798 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2005082 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2005082 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 15900700 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6556911 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1231319 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1226027 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47787527 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29554737 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 797902 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1720271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 79860437 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2035409428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1033316830 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2813832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 5963920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3077504010 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1542362 # Total snoops (count) +system.toL2Bus.snoopTraffic 65849016 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 38107926 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.016628 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.127874 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 37493845 98.34% 98.34% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 633869 1.66% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 37474258 98.34% 98.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 633668 1.66% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 38127714 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 31242309916 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 38107926 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 31293825988 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 523765 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 519265 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 15589083360 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 15589080685 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 7892971168 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 7944642139 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 287709740 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 286385229 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 712482327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 714971913 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |