diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 4549 |
1 files changed, 2277 insertions, 2272 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index 1ebab8c9c..cbc921b4f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.317224 # Number of seconds simulated -sim_ticks 51317223946000 # Number of ticks simulated -final_tick 51317223946000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.317217 # Number of seconds simulated +sim_ticks 51317217215000 # Number of ticks simulated +final_tick 51317217215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175740 # Simulator instruction rate (inst/s) -host_op_rate 206507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9897363484 # Simulator tick rate (ticks/s) -host_mem_usage 694116 # Number of bytes of host memory used -host_seconds 5184.94 # Real time elapsed on the host -sim_insts 911201050 # Number of instructions simulated -sim_ops 1070728401 # Number of ops (including micro ops) simulated +host_inst_rate 222365 # Simulator instruction rate (inst/s) +host_op_rate 261300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12534471719 # Simulator tick rate (ticks/s) +host_mem_usage 700016 # Number of bytes of host memory used +host_seconds 4094.09 # Real time elapsed on the host +sim_insts 910382802 # Number of instructions simulated +sim_ops 1069785844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 175488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 146560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3612352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 27482328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 187136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 157760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3726080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 29409648 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 423552 # Number of bytes read from this memory -system.physmem.bytes_read::total 65320904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3612352 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3726080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7338432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83980672 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 183360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 154432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3744320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 27933912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 182144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 147072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3576960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29113392 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 413632 # Number of bytes read from this memory +system.physmem.bytes_read::total 65449224 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3744320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3576960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7321280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83967296 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 84001252 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 56443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 429419 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2924 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2465 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 459531 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6618 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1020652 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1312198 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83987876 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2865 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2413 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 58505 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 436475 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2846 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2298 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 55890 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 454902 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6463 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1022657 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1311989 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1314771 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 70393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 535538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 573095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1272885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 70393 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72609 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 143001 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1636501 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1314562 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3573 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 72964 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 544338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3549 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 567322 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1275385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 72964 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69703 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 142667 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1636240 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1636902 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1636501 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 70393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 535939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 573095 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8254 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2909786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1020652 # Number of read requests accepted -system.physmem.writeReqs 1314771 # Number of write requests accepted -system.physmem.readBursts 1020652 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1314771 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 65284928 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36800 # Total number of bytes read from write queue -system.physmem.bytesWritten 84000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 65320904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 84001252 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 575 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2239 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1636641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1636240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 72964 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 544739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3549 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2866 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 567322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8060 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2912027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1022657 # Number of read requests accepted +system.physmem.writeReqs 1314562 # Number of write requests accepted +system.physmem.readBursts 1022657 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1314562 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 65407680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue +system.physmem.bytesWritten 83988672 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 65449224 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 83987876 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 662 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2238 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 60738 # Per bank write bursts -system.physmem.perBankRdBursts::1 63324 # Per bank write bursts -system.physmem.perBankRdBursts::2 61558 # Per bank write bursts -system.physmem.perBankRdBursts::3 59296 # Per bank write bursts -system.physmem.perBankRdBursts::4 63003 # Per bank write bursts -system.physmem.perBankRdBursts::5 70930 # Per bank write bursts -system.physmem.perBankRdBursts::6 62473 # Per bank write bursts -system.physmem.perBankRdBursts::7 61273 # Per bank write bursts -system.physmem.perBankRdBursts::8 57204 # Per bank write bursts -system.physmem.perBankRdBursts::9 83606 # Per bank write bursts -system.physmem.perBankRdBursts::10 64602 # Per bank write bursts -system.physmem.perBankRdBursts::11 64452 # Per bank write bursts -system.physmem.perBankRdBursts::12 60809 # Per bank write bursts -system.physmem.perBankRdBursts::13 66792 # Per bank write bursts -system.physmem.perBankRdBursts::14 61061 # Per bank write bursts -system.physmem.perBankRdBursts::15 58956 # Per bank write bursts -system.physmem.perBankWrBursts::0 80045 # Per bank write bursts -system.physmem.perBankWrBursts::1 81301 # Per bank write bursts -system.physmem.perBankWrBursts::2 81272 # Per bank write bursts -system.physmem.perBankWrBursts::3 81440 # Per bank write bursts -system.physmem.perBankWrBursts::4 83523 # Per bank write bursts -system.physmem.perBankWrBursts::5 87218 # Per bank write bursts -system.physmem.perBankWrBursts::6 82653 # Per bank write bursts -system.physmem.perBankWrBursts::7 82595 # Per bank write bursts -system.physmem.perBankWrBursts::8 79330 # Per bank write bursts -system.physmem.perBankWrBursts::9 83624 # Per bank write bursts -system.physmem.perBankWrBursts::10 82850 # Per bank write bursts -system.physmem.perBankWrBursts::11 84015 # Per bank write bursts -system.physmem.perBankWrBursts::12 79570 # Per bank write bursts -system.physmem.perBankWrBursts::13 84630 # Per bank write bursts -system.physmem.perBankWrBursts::14 79832 # Per bank write bursts -system.physmem.perBankWrBursts::15 78616 # Per bank write bursts +system.physmem.perBankRdBursts::0 60981 # Per bank write bursts +system.physmem.perBankRdBursts::1 62566 # Per bank write bursts +system.physmem.perBankRdBursts::2 61229 # Per bank write bursts +system.physmem.perBankRdBursts::3 58916 # Per bank write bursts +system.physmem.perBankRdBursts::4 63354 # Per bank write bursts +system.physmem.perBankRdBursts::5 70912 # Per bank write bursts +system.physmem.perBankRdBursts::6 62699 # Per bank write bursts +system.physmem.perBankRdBursts::7 61112 # Per bank write bursts +system.physmem.perBankRdBursts::8 58244 # Per bank write bursts +system.physmem.perBankRdBursts::9 84348 # Per bank write bursts +system.physmem.perBankRdBursts::10 65094 # Per bank write bursts +system.physmem.perBankRdBursts::11 66290 # Per bank write bursts +system.physmem.perBankRdBursts::12 61782 # Per bank write bursts +system.physmem.perBankRdBursts::13 66140 # Per bank write bursts +system.physmem.perBankRdBursts::14 59027 # Per bank write bursts +system.physmem.perBankRdBursts::15 59301 # Per bank write bursts +system.physmem.perBankWrBursts::0 79428 # Per bank write bursts +system.physmem.perBankWrBursts::1 80879 # Per bank write bursts +system.physmem.perBankWrBursts::2 81341 # Per bank write bursts +system.physmem.perBankWrBursts::3 82396 # Per bank write bursts +system.physmem.perBankWrBursts::4 84257 # Per bank write bursts +system.physmem.perBankWrBursts::5 87543 # Per bank write bursts +system.physmem.perBankWrBursts::6 80825 # Per bank write bursts +system.physmem.perBankWrBursts::7 81935 # Per bank write bursts +system.physmem.perBankWrBursts::8 79231 # Per bank write bursts +system.physmem.perBankWrBursts::9 83962 # Per bank write bursts +system.physmem.perBankWrBursts::10 83023 # Per bank write bursts +system.physmem.perBankWrBursts::11 84619 # Per bank write bursts +system.physmem.perBankWrBursts::12 80226 # Per bank write bursts +system.physmem.perBankWrBursts::13 84960 # Per bank write bursts +system.physmem.perBankWrBursts::14 78537 # Per bank write bursts +system.physmem.perBankWrBursts::15 79161 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 119 # Number of times write queue was full causing retry -system.physmem.totGap 51317222751500 # Total gap between requests +system.physmem.numWrRetry 117 # Number of times write queue was full causing retry +system.physmem.totGap 51317216009000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1020637 # Read request sizes (log2) +system.physmem.readPktSize::6 1022642 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1312198 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 562832 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 301764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 103549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 46162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 658 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 477 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1311989 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 563394 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 302594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 104127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 46335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 752 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 511 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1269 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -163,176 +163,190 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 726 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 30315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 42487 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 50854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 67639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 74945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 78298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 83924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 86856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 84418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 87663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 90523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 82299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 81232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 81562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 72278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 67228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 1046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 1162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 850 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 298 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 586236 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 254.650755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 152.083309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 294.038467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256952 43.83% 43.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146727 25.03% 68.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 55530 9.47% 78.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27689 4.72% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 21119 3.60% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11926 2.03% 88.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10672 1.82% 90.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7426 1.27% 91.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 48195 8.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 586236 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 61671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 16.539767 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.609404 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 61664 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::6 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 21758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 29866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 42370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 67407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 74973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 78027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 83029 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 86506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 84131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 87193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 90592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 80936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81560 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 72513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 71387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 3626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 1044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 292 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 584051 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 255.792785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 152.875634 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.556382 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 254148 43.51% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146795 25.13% 68.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 55909 9.57% 78.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27613 4.73% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21352 3.66% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 11974 2.05% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10495 1.80% 90.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7232 1.24% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 48533 8.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 584051 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 61706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 16.562133 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 65.554683 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 61699 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 61671 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 61671 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.282515 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.526147 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.873212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-31 57372 93.03% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-63 2142 3.47% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-95 1045 1.69% 98.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-127 638 1.03% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-159 205 0.33% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-191 106 0.17% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-223 28 0.05% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-255 57 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-287 30 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-319 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-351 4 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-383 11 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-415 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-447 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-479 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-511 4 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-543 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::576-607 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::608-639 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-671 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::736-767 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-895 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1504-1535 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 61671 # Writes before turning the bus around for reads -system.physmem.totQLat 27430760765 # Total ticks spent queuing -system.physmem.totMemAccLat 46557204515 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5100385000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26890.87 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 61706 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 61706 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 21.267348 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.511616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 23.799712 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 139 0.23% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 57235 92.75% 92.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 1751 2.84% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 438 0.71% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 620 1.00% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 435 0.70% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 261 0.42% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 360 0.58% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 146 0.24% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 47 0.08% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 57 0.09% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 58 0.09% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.03% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 17 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 19 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 28 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 17 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 15 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-783 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::784-799 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-847 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::848-863 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::880-895 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 61706 # Writes before turning the bus around for reads +system.physmem.totQLat 27544031458 # Total ticks spent queuing +system.physmem.totMemAccLat 46706437708 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5109975000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26951.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45640.87 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45701.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.64 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.21 # Average write queue length when enqueuing -system.physmem.readRowHits 787981 # Number of row buffer hits during reads -system.physmem.writeRowHits 958372 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes -system.physmem.avgGap 21973416.70 # Average gap between requests -system.physmem.pageHitRate 74.87 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2249478000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1227393750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3920233200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4277104560 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1233069997860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29708691447750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34305226966560 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.493484 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49422945373021 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713594740000 # Time in different power states +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.79 # Average write queue length when enqueuing +system.physmem.readRowHits 789656 # Number of row buffer hits during reads +system.physmem.writeRowHits 960610 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.27 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.20 # Row buffer hit rate for writes +system.physmem.avgGap 21956528.68 # Average gap between requests +system.physmem.pageHitRate 74.98 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2223494280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1213216125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3913798200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4267753920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1231075762515 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29710436097000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34304920924920 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.487622 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49425844576094 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 180683706479 # Time in different power states +system.physmem_0.memoryStateTime::ACT 177772818906 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2182466160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1190829750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4036320600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4227986160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3351791311440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1230809355630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29710674459000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34304912728740 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.487361 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49426230251457 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713594740000 # Time in different power states +system.physmem_1.actEnergy 2191931280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1195994250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4057723800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4236099120 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351790802880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1231757755830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29709837865500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34305068172660 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.490491 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49424824907095 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713594480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 177398580543 # Time in different power states +system.physmem_1.memoryStateTime::ACT 178797453905 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 1408 # Number of bytes read from this memory @@ -355,30 +369,30 @@ system.realview.nvmem.bw_total::cpu0.inst 15 # T system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 27 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 43 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 134105303 # Number of BP lookups -system.cpu0.branchPred.condPredicted 90165699 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5786352 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 89882943 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 61723151 # Number of BTB hits +system.cpu0.branchPred.lookups 134591179 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90304193 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5810526 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90589543 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 61837798 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 68.670594 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17198111 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 190210 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 5005537 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 2645934 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 2359603 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 409587 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 68.261519 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17370059 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190077 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5078772 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2686505 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2392267 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 411015 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,95 +422,89 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 899770 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 899770 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17075 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93436 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 556454 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 343316 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2623.475166 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 14944.534863 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 334883 97.54% 97.54% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 5615 1.64% 99.18% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 1161 0.34% 99.52% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 826 0.24% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 305 0.09% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 149 0.04% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 96 0.03% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 57 0.02% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 86 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 45 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 18 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::425984-458751 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 343316 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 426919 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23051.464095 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18844.709714 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16480.973938 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 417565 97.81% 97.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8400 1.97% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 455 0.11% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 392 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 913460 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 913460 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17456 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94858 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 564703 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 348757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2510.769676 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 14687.468261 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 346035 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1894 0.54% 99.76% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 459 0.13% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 149 0.04% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 127 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 27 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 61 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 348757 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 428972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 22512.397080 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18206.266840 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16738.101214 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 419694 97.84% 97.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 8206 1.91% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 548 0.13% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 418 0.10% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::262144-327679 68 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 426919 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 352898234664 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.139794 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.715758 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 351858805164 99.71% 99.71% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 566388500 0.16% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 206550000 0.06% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 120953500 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 47115000 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 25743000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 26226000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 38984000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6924500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 487500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 24000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 352898234664 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 93436 84.55% 84.55% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17075 15.45% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 110511 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 899770 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 428972 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 361724793256 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.150757 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.705483 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 360695140256 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 568723500 0.16% 99.87% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 203544500 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 117776000 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 46114500 0.01% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 23872000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 26539000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 36172500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 6478000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 375000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 12500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 361724793256 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 94859 84.46% 84.46% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17456 15.54% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 112315 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 913460 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 899770 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110511 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 913460 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 112315 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110511 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1010281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 112315 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1025775 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105998610 # DTB read hits -system.cpu0.dtb.read_misses 619021 # DTB read misses -system.cpu0.dtb.write_hits 82262350 # DTB write hits -system.cpu0.dtb.write_misses 280749 # DTB write misses -system.cpu0.dtb.flush_tlb 1081 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 106460809 # DTB read hits +system.cpu0.dtb.read_misses 623704 # DTB read misses +system.cpu0.dtb.write_hits 82932208 # DTB write hits +system.cpu0.dtb.write_misses 289756 # DTB write misses +system.cpu0.dtb.flush_tlb 1080 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 21954 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 55918 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 189 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9571 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 55225 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9182 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 57075 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 106617631 # DTB read accesses -system.cpu0.dtb.write_accesses 82543099 # DTB write accesses +system.cpu0.dtb.perms_faults 56785 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 107084513 # DTB read accesses +system.cpu0.dtb.write_accesses 83221964 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 188260960 # DTB hits -system.cpu0.dtb.misses 899770 # DTB misses -system.cpu0.dtb.accesses 189160730 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 189393017 # DTB hits +system.cpu0.dtb.misses 913460 # DTB misses +system.cpu0.dtb.accesses 190306477 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,859 +534,861 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 102467 # Table walker walks requested -system.cpu0.itb.walker.walksLong 102467 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2998 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69670 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14196 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 88271 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1375.933206 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8810.022108 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 87313 98.91% 98.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 590 0.67% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 225 0.25% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 97 0.11% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 16 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 88271 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 86864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28386.103564 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24197.471815 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17986.515042 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 84889 97.73% 97.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1706 1.96% 99.69% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 161 0.19% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 62 0.07% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 31 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 102224 # Table walker walks requested +system.cpu0.itb.walker.walksLong 102224 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2961 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69807 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 13996 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 88228 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1371.061341 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 8977.114896 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 87329 98.98% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 530 0.60% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 216 0.24% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 99 0.11% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 20 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 88228 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 86764 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 27719.480430 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23267.563993 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18820.928470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 84648 97.56% 97.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 1819 2.10% 99.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 174 0.20% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.08% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 30 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 86864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 606302699128 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.904496 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.294288 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 57963600068 9.56% 9.56% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 548286629060 90.43% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 47140500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4566000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 270000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 89500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 606302699128 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 69670 95.87% 95.87% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2998 4.13% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72668 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 86764 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 597945449536 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.915932 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.277880 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 50325346976 8.42% 8.42% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 547568596060 91.58% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 46828000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 4056500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 391500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 54500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 126500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::7 49500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 597945449536 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 69807 95.93% 95.93% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2961 4.07% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72768 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102467 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102467 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 102224 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 102224 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72668 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72668 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 175135 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94697092 # ITB inst hits -system.cpu0.itb.inst_misses 102467 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72768 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72768 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 174992 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 95313688 # ITB inst hits +system.cpu0.itb.inst_misses 102224 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1081 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1080 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 22329 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 21954 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 534 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41669 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 40789 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 188921 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 189995 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94799559 # ITB inst accesses -system.cpu0.itb.hits 94697092 # DTB hits -system.cpu0.itb.misses 102467 # DTB misses -system.cpu0.itb.accesses 94799559 # DTB accesses -system.cpu0.numPwrStateTransitions 15974 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 7987 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 2945663211.345562 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 55329339473.705994 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3525 44.13% 44.13% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4444 55.64% 99.77% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.03% 99.80% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 2 0.03% 99.82% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.03% 99.85% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 95415912 # ITB inst accesses +system.cpu0.itb.hits 95313688 # DTB hits +system.cpu0.itb.misses 102224 # DTB misses +system.cpu0.itb.accesses 95415912 # DTB accesses +system.cpu0.numPwrStateTransitions 16182 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8091 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 3359442146.645409 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 64779765350.946983 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3624 44.79% 44.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4450 55.00% 99.79% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.80% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.04% 99.84% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 1988782294428 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 7987 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 27790211876983 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 23527012069017 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 671968082 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 1988782283928 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8091 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 24135970806492 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 27181246408508 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 673796045 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 245522731 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 595240198 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 134105303 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81567196 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 387351290 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13225502 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2523731 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 22012 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 3023 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 4782962 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 167694 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 2395 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94491838 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3604496 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 39400 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 646988319 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.075576 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.327336 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 248201376 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 597842349 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 134591179 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81894362 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 386081151 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13278647 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2497741 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21664 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3050 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4790854 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 168722 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2591 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 95107499 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3628886 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 39039 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 648406203 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.078367 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.330450 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 500985180 77.43% 77.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18129867 2.80% 80.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18167874 2.81% 83.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13357518 2.06% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28640593 4.43% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 8987633 1.39% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9763680 1.51% 92.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8383348 1.30% 93.73% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40572626 6.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 501760932 77.38% 77.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18256203 2.82% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18220690 2.81% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13435350 2.07% 85.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 28609960 4.41% 89.49% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9048805 1.40% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9824320 1.52% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8413306 1.30% 93.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40836637 6.30% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 646988319 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.199571 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.885816 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 199030326 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 322925985 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105893213 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13875278 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5261155 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19621820 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1370848 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 649217042 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4232345 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5261155 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 206721651 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 22515587 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 261202094 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 111943526 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 39341608 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 633848526 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 79662 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1830943 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1627304 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 19580203 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3993 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 606139321 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 975790571 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 747374109 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 852582 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 509962376 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 96176945 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15656160 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13698263 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 77451785 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102163876 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 86418656 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13880040 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14667641 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 600742993 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15759066 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 601574255 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 855603 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 81711782 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 51353600 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 357908 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 646988319 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.929807 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.657116 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 648406203 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.199751 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.887275 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 201305382 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 321428647 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 106579942 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13809088 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5281102 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19732890 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1377081 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 652345167 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4243358 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5281102 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 208974593 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22808368 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259762289 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 112590129 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 38987372 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 636948284 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 76415 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1870283 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1736148 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 19269388 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3866 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 608166873 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 978325960 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 751087221 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 834633 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 511551111 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96615757 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15505583 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13521940 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 76964594 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 102747908 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 87125063 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13952178 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14707468 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 603971660 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15594199 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 604455425 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 868037 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 82226578 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 51472860 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 368538 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 648406203 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.932217 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.660002 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 411195381 63.56% 63.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 99990691 15.45% 79.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43358439 6.70% 85.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31042131 4.80% 90.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23015507 3.56% 94.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16185943 2.50% 96.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 11141665 1.72% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6569936 1.02% 99.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4488626 0.69% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 412086930 63.55% 63.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 99690109 15.37% 78.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43563237 6.72% 85.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31279787 4.82% 90.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 23126821 3.57% 94.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16303260 2.51% 96.55% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11232229 1.73% 98.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6608117 1.02% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4515713 0.70% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 646988319 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 648406203 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 2994179 25.40% 25.40% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22123 0.19% 25.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2181 0.02% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4797008 40.69% 66.30% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3972728 33.70% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3047764 25.70% 25.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 24416 0.21% 25.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 3438 0.03% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4792960 40.42% 66.35% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3990225 33.65% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408493998 67.90% 67.90% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1413538 0.23% 68.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 65279 0.01% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 146 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 55915 0.01% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 108222779 17.99% 86.15% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 83322549 13.85% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 49 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 410215443 67.87% 67.87% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1414052 0.23% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 66288 0.01% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 164 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 69960 0.01% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108687129 17.98% 86.10% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 84002340 13.90% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 601574255 # Type of FU issued -system.cpu0.iq.rate 0.895242 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11788219 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019596 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1861718464 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 698381981 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 579322691 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1062187 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 541590 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 470908 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 612794722 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 567701 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4798771 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 604455425 # Type of FU issued +system.cpu0.iq.rate 0.897090 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11858803 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019619 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1868979076 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 701958936 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 582265082 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1064817 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 542988 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 473036 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 615746479 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 567700 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4852034 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16823750 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20061 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 720899 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8636995 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16874429 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20604 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 721236 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8753871 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 4014042 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 7828481 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 4029020 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 7690355 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5261155 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14418671 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6592888 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 616647515 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1731555 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102163876 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 86418656 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13404445 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 244099 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6259110 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 720899 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2467872 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2697760 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5165632 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 594649792 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105987908 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6038347 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5281102 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14719425 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6525674 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 619711534 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1741377 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 102747908 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 87125063 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13231258 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 247990 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6185988 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 721236 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2486586 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2703924 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5190510 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 597504652 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 106449995 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6051495 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 145456 # number of nop insts executed -system.cpu0.iew.exec_refs 188253040 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110177692 # Number of branches executed -system.cpu0.iew.exec_stores 82265132 # Number of stores executed -system.cpu0.iew.exec_rate 0.884938 # Inst execution rate -system.cpu0.iew.wb_sent 581218511 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 579793599 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286101590 # num instructions producing a value -system.cpu0.iew.wb_consumers 497649201 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.862829 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.574906 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 81765486 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15401158 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4434486 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 633109401 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.844704 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.839642 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 145675 # number of nop insts executed +system.cpu0.iew.exec_refs 189385273 # number of memory reference insts executed +system.cpu0.iew.exec_branches 110604743 # Number of branches executed +system.cpu0.iew.exec_stores 82935278 # Number of stores executed +system.cpu0.iew.exec_rate 0.886774 # Inst execution rate +system.cpu0.iew.wb_sent 584170266 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 582738118 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 287532720 # num instructions producing a value +system.cpu0.iew.wb_consumers 500025728 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.864858 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575036 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 82281412 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15225661 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4452035 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 634456144 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.846929 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.842512 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 436470478 68.94% 68.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97716674 15.43% 84.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32967148 5.21% 89.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15484157 2.45% 92.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10846506 1.71% 93.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6530507 1.03% 94.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6073156 0.96% 95.73% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3956859 0.62% 96.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 23063916 3.64% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 437517078 68.96% 68.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 97256113 15.33% 84.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33197387 5.23% 89.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15688308 2.47% 91.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10938676 1.72% 93.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6579950 1.04% 94.75% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6141511 0.97% 95.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3977023 0.63% 96.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 23160098 3.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 633109401 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 455072762 # Number of instructions committed -system.cpu0.commit.committedOps 534790277 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 634456144 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 457096110 # Number of instructions committed +system.cpu0.commit.committedOps 537339276 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 163121787 # Number of memory references committed -system.cpu0.commit.loads 85340126 # Number of loads committed -system.cpu0.commit.membars 3736581 # Number of memory barriers committed -system.cpu0.commit.branches 101711661 # Number of branches committed -system.cpu0.commit.fp_insts 451530 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 490677146 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13330927 # Number of function calls committed. +system.cpu0.commit.refs 164244670 # Number of memory references committed +system.cpu0.commit.loads 85873478 # Number of loads committed +system.cpu0.commit.membars 3759461 # Number of memory barriers committed +system.cpu0.commit.branches 102099172 # Number of branches committed +system.cpu0.commit.fp_insts 454376 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 493297626 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13466186 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 370465668 69.27% 69.27% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1106577 0.21% 69.48% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 48950 0.01% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 47295 0.01% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 85340126 15.96% 85.46% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77781661 14.54% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 371876704 69.21% 69.21% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1107747 0.21% 69.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 49726 0.01% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 60429 0.01% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 85873478 15.98% 85.41% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 78371192 14.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 534790277 # Class of committed instruction -system.cpu0.commit.bw_lim_events 23063916 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1222566942 # The number of ROB reads -system.cpu0.rob.rob_writes 1247016110 # The number of ROB writes -system.cpu0.timesIdled 4124153 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 24979763 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 47054019698 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 455072762 # Number of Instructions Simulated -system.cpu0.committedOps 534790277 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.476617 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.476617 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.677224 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.677224 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 700310786 # number of integer regfile reads -system.cpu0.int_regfile_writes 414023994 # number of integer regfile writes -system.cpu0.fp_regfile_reads 859135 # number of floating regfile reads -system.cpu0.fp_regfile_writes 476716 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127822251 # number of cc regfile reads -system.cpu0.cc_regfile_writes 129020802 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1207381115 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15553504 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10794591 # number of replacements +system.cpu0.commit.op_class_0::total 537339276 # Class of committed instruction +system.cpu0.commit.bw_lim_events 23160098 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 1226917419 # The number of ROB reads +system.cpu0.rob.rob_writes 1253216154 # The number of ROB writes +system.cpu0.timesIdled 4189702 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 25389842 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 54362488365 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 457096110 # Number of Instructions Simulated +system.cpu0.committedOps 537339276 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.474080 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.474080 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.678389 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.678389 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 703759932 # number of integer regfile reads +system.cpu0.int_regfile_writes 416323236 # number of integer regfile writes +system.cpu0.fp_regfile_reads 842814 # number of floating regfile reads +system.cpu0.fp_regfile_writes 524896 # number of floating regfile writes +system.cpu0.cc_regfile_reads 127590054 # number of cc regfile reads +system.cpu0.cc_regfile_writes 128777466 # number of cc regfile writes +system.cpu0.misc_regfile_reads 1210356696 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15381690 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10779491 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.983410 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 308312311 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10795103 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.560386 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 308062266 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10780003 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.577197 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 1667914500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.025597 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.957813 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566456 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433511 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 303.491043 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 208.492367 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.592756 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.407212 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1361016734 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1361016734 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 81465542 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 81638403 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 163103945 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68252369 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 68428120 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 136680489 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200713 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 207163 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 407876 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171912 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 153997 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 325909 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1802432 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1798763 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3601195 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2076413 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2068312 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4144725 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149889823 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 150220520 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 300110343 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150090536 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 150427683 # number of overall hits -system.cpu0.dcache.overall_hits::total 300518219 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6267923 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6604970 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12872893 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6633530 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6545682 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13179212 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 651993 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 686156 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1338149 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 638733 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 602965 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1241698 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 328325 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 330976 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 659301 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 8 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13540186 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 13753617 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 27293803 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 14192179 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 14439773 # number of overall misses -system.cpu0.dcache.overall_misses::total 28631952 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 95137339500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 103283573000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 198420912500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 235524203196 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 229624162852 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 465148366048 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 14948853955 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13357374592 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 28306228547 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4139762000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4347889500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 8487651500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 110000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 214000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 324000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 345610396651 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 346265110444 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 691875507095 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 345610396651 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 346265110444 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 691875507095 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87733465 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88243373 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 175976838 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74885899 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 74973802 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 149859701 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 852706 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 893319 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1746025 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 810645 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 756962 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1567607 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2130757 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2129739 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4260496 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2076421 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2068317 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4144738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163430009 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 163974137 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 327404146 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164282715 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 164867456 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 329150171 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071443 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074849 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.073151 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.088582 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087306 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087944 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764616 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.768097 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766397 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.787932 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.796559 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792098 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.154088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155407 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154747 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082850 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.083877 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.083364 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086389 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.087584 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086988 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15178.447390 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15637.250888 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15413.855495 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35505.108622 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35080.250286 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35294.095432 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23403.916746 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22152.819139 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22796.387324 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12608.732201 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13136.570325 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12873.712462 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13750 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 42800 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24923.076923 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25524.789442 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25176.294385 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25349.179339 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24352.172887 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23979.955256 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 24164.454701 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 50137821 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 53336 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3624490 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 999 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.833069 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 53.389389 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 8255712 # number of writebacks -system.cpu0.dcache.writebacks::total 8255712 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3390240 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3655769 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7046009 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5522660 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5441791 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10964451 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3462 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3529 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 6991 # 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number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5826884 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1110870 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1103891 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2214761 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 642919 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 670026 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1312945 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 635271 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 599436 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234707 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125907 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 127277 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253184 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 8 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4623824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 4652528 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 9276352 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5266743 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 5322554 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 10589297 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 18054 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15626 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.tags.tag_accesses 1359846782 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1359846782 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 81913095 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 81085676 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 162998771 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 68945283 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 67608016 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 136553299 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 203242 # 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number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1339099 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 645837 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 595706 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1241543 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 333547 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 322838 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 656385 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 13 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13493339 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 13747615 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 27240954 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14133905 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 14446148 # number of overall misses +system.cpu0.dcache.overall_misses::total 28580053 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 98901247500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 99537012000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 198438259500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 227853900939 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 237216026267 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 465069927206 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 15046942422 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 13204575493 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 28251517915 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4379004500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4078607000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 8457611500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 179500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 254000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 433500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 341802090861 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 349957613760 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 691759704621 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 341802090861 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 349957613760 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 691759704621 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88246426 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 87601496 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 175847922 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 75459454 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 74244105 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 149703559 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 843808 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 903460 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1747268 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 818080 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 749534 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1567614 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2140850 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2116477 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4257327 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2085829 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2057173 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4143002 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 164523960 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 162595135 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 327119095 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 165367768 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 163498595 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 328866363 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.071769 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.074380 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.073070 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086327 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.089382 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087842 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.759137 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.773175 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766396 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.789455 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.794768 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.791995 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.155801 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.152536 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.154178 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000006 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000005 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082014 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.084551 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.083275 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085470 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.088356 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086905 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15615.992201 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15276.206525 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15443.686474 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34978.188466 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35746.359982 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35365.835140 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 23298.359218 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 22166.262373 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 22755.166688 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13128.598069 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12633.602612 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12885.138295 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13807.692308 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 31750 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20642.857143 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25331.171985 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25455.878257 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25394.107145 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 24183.132040 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24224.977742 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24204.283478 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 50179402 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 52249 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3620965 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1011 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.858019 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 51.680514 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 8246145 # number of writebacks +system.cpu0.dcache.writebacks::total 8246145 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3422225 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3613055 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 7035280 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5423611 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5531095 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10954706 # 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number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17996972 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2911106 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2902765 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5813871 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1090560 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1104994 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2195554 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 631874 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 682564 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1314438 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 642255 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 592302 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1234557 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 129122 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 123894 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253016 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 13 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4643921 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 4600061 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 9243982 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5275795 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 5282625 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 10558420 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17861 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15819 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19503 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14194 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18882 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 14815 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 37557 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 29820 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 36743 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 30634 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44005676000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 46542154500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90547830500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40688703147 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39847716140 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 80536419287 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10144598500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12204187000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22348785500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14171149455 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12627536592 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26798686047 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1695865500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1763125500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3458991000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 102000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 209000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 311000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 98865528602 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 99017407232 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 197882935834 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109010127102 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111221594232 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 220231721334 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3418077000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2846181000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264258000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3418077000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2846181000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264258000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032800 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033421 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033112 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014834 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014724 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014779 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753975 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.750041 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.751962 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.783661 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.791897 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787638 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059090 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059762 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059426 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028292 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028374 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028333 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032059 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032284 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032172 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15292.051279 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15781.275844 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15539.665883 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36627.781061 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36097.509754 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36363.480884 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15778.968268 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18214.497646 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17021.874869 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22307.250693 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21065.696074 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21704.490253 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13469.191546 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13852.663875 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13661.965211 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 41800 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23923.076923 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21381.767256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21282.495717 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21331.977898 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20697.825412 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20896.282918 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20797.577151 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 189325.191093 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182143.926789 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185993.408551 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91010.384216 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95445.372233 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92973.240126 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 16455853 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.958473 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 172258590 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16456365 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.467597 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12245675500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.034812 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.923660 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535224 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464695 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45537932500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44832999500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 90370932000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39266250291 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 40577595959 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79843846250 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10081360000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12415038000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 22496398000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 14258396422 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 12486057493 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26744453915 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1802187500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1654747000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3456934500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 166500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 246000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 412500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99062579213 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 97896652952 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 196959232165 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 109143939213 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 110311690952 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 219455630165 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3399664500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2864633000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6264297500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3399664500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2864633000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6264297500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032988 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033136 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033062 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014452 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014883 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014666 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.748836 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.755500 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752282 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.785076 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.790227 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787539 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060313 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058538 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059431 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000005 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028226 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028292 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028259 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031903 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032310 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032106 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15642.828705 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15444.929059 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15544.020843 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36005.584554 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36722.005693 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36366.150070 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15954.699829 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18188.826249 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17114.841476 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 22200.522257 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 21080.559399 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 21663.198957 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13957.245861 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13356.151226 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13662.908670 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 30750 # 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number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104688612913 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 206449544840 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 101760931927 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104688612913 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 206449544840 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 101760931927 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104688612913 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 206449544840 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103166162413 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 103212304918 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 206378467331 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103166162413 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 103212304918 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 206378467331 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103166162413 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 103212304918 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 206378467331 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 974276500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 641521000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1615797500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 974276500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 641521000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 1615797500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086630 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.086630 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086009 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.087244 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.086630 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12545.099403 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12522.710055 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12566.939486 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12545.099403 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086717 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.086717 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086531 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.086905 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.086717 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12544.157875 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12544.157875 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12537.425603 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12550.894366 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12544.157875 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 78292.349065 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 78330.639974 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78234.268293 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 78292.349065 # average overall mshr uncacheable latency -system.cpu1.branchPred.lookups 134713045 # Number of BP lookups -system.cpu1.branchPred.condPredicted 90294354 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5910949 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 91937142 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 61863845 # Number of BTB hits +system.cpu1.branchPred.lookups 133897441 # Number of BP lookups +system.cpu1.branchPred.condPredicted 89938186 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5869763 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91159166 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 61608831 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.289284 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17423003 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 191945 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 5099062 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 2694305 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 2404757 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 414905 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 67.583803 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17197784 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 191914 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 5022071 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2642299 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2379772 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 413417 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1408,89 +1418,93 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 940458 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 940458 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17835 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93375 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 588116 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 352342 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2605.512542 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 15403.554578 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-65535 349554 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-131071 1910 0.54% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-196607 467 0.13% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-262143 147 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-327679 145 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::458752-524287 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-589823 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 352342 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 440653 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22932.098499 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18696.328712 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16830.741238 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 430922 97.79% 97.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 8564 1.94% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 599 0.14% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 434 0.10% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 89 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 36 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 440653 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 323076797592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.107209 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.744323 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 321987662592 99.66% 99.66% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 587014500 0.18% 99.84% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 213123500 0.07% 99.91% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 130553500 0.04% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 52805000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 28221000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 26598000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 43358000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 6987500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 426000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 21000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 10000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 323076797592 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 93376 83.96% 83.96% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17835 16.04% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 111211 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 940458 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 900943 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 900943 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17588 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92135 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 552674 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 348269 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2521.581019 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 15048.371457 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 345488 99.20% 99.20% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1911 0.55% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 471 0.14% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 142 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 66 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 348269 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 416714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 22183.198789 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17895.949159 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 17072.754814 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 407840 97.87% 97.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7849 1.88% 99.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 499 0.12% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 336 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 108 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 13 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 416714 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 309953543704 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.014716 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.659727 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 308957195204 99.68% 99.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 543608000 0.18% 99.85% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 198540500 0.06% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 120617500 0.04% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 43978000 0.01% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 24203000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 22128500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 36223000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 6651000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 321500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 20000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 8000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::52-55 5500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::56-59 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::60-63 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 309953543704 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92135 83.97% 83.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17588 16.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 109723 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 900943 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 940458 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 900943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 109723 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111211 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1051669 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 109723 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1010666 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 107105213 # DTB read hits -system.cpu1.dtb.read_misses 647862 # DTB read misses -system.cpu1.dtb.write_hits 82338491 # DTB write hits -system.cpu1.dtb.write_misses 292596 # DTB write misses -system.cpu1.dtb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 106418453 # DTB read hits +system.cpu1.dtb.read_misses 624156 # DTB read misses +system.cpu1.dtb.write_hits 81533380 # DTB write hits +system.cpu1.dtb.write_misses 276787 # DTB write misses +system.cpu1.dtb.flush_tlb 1086 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 22079 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 54922 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 184 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9726 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 55782 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 176 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9564 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55049 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 107753075 # DTB read accesses -system.cpu1.dtb.write_accesses 82631087 # DTB write accesses +system.cpu1.dtb.perms_faults 55148 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 107042609 # DTB read accesses +system.cpu1.dtb.write_accesses 81810167 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 189443704 # DTB hits -system.cpu1.dtb.misses 940458 # DTB misses -system.cpu1.dtb.accesses 190384162 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 187951833 # DTB hits +system.cpu1.dtb.misses 900943 # DTB misses +system.cpu1.dtb.accesses 188852776 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1520,410 +1534,404 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 101953 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101953 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3135 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69070 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14166 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 87787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1451.501931 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 9077.444806 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 86783 98.86% 98.86% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 614 0.70% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 230 0.26% 99.82% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 110 0.13% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 22 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 102336 # Table walker walks requested +system.cpu1.itb.walker.walksLong 102336 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3041 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69360 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14089 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 88247 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1349.994901 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8816.342326 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 87374 99.01% 99.01% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 501 0.57% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 211 0.24% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 117 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 87787 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 86371 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28729.370969 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 24395.132531 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 18742.067885 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47141 54.58% 54.58% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 37044 42.89% 97.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 924 1.07% 98.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 961 1.11% 99.65% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 89 0.10% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 90 0.10% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.07% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 13 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 86371 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 610837012424 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.919047 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.273178 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 49510897620 8.11% 8.11% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 561270328804 91.89% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 50540500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 4377500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 769000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 99000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 610837012424 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69070 95.66% 95.66% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 3135 4.34% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72205 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 88247 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86490 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27376.708290 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22843.157676 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 18954.672615 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 84456 97.65% 97.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1746 2.02% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 174 0.20% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 67 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 29 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 9 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86490 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 610599891424 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.922621 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.267613 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 47307697252 7.75% 7.75% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 563239770172 92.24% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 45620000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5915500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 874500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 14000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 610599891424 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 69360 95.80% 95.80% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3041 4.20% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72401 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101953 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101953 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 102336 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 102336 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72205 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72205 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 174158 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95706620 # ITB inst hits -system.cpu1.itb.inst_misses 101953 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72401 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72401 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174737 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 94847182 # ITB inst hits +system.cpu1.itb.inst_misses 102336 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1087 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1086 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21707 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 22079 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 541 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 39902 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 41108 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 192638 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 191650 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95808573 # ITB inst accesses -system.cpu1.itb.hits 95706620 # DTB hits -system.cpu1.itb.misses 101953 # DTB misses -system.cpu1.itb.accesses 95808573 # DTB accesses -system.cpu1.numPwrStateTransitions 16900 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8450 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 3209165135.406272 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 63386513065.949989 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3583 42.40% 42.40% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4849 57.38% 99.79% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 3 0.04% 99.82% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 94949518 # ITB inst accesses +system.cpu1.itb.hits 94847182 # DTB hits +system.cpu1.itb.misses 102336 # DTB misses +system.cpu1.itb.accesses 94949518 # DTB accesses +system.cpu1.numPwrStateTransitions 16690 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8345 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 2811784025.136968 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 54125884171.976646 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3484 41.75% 41.75% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4842 58.02% 99.77% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.82% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 3 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::overflows 8 0.10% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 1988782300428 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8450 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 24199778551817 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 27117445394183 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 673200080 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 1988782282928 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8345 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 27852879525232 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 23464337689768 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 669110072 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 250326293 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 598056519 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 134713045 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 81981153 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 383149579 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13468488 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2515216 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 21179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 3210 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 4838435 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 163101 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 2842 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95493345 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3679546 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 39276 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647753829 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.079477 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.330780 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 247318637 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 594168769 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133897441 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 81448914 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 382780415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13369418 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2469656 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2942 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4831905 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 160199 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 2485 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 94635082 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3655757 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39111 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 644272699 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.077858 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.328781 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 500909169 77.33% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18369194 2.84% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18392289 2.84% 83.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13444419 2.08% 85.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28522776 4.40% 89.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 9079206 1.40% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9809102 1.51% 92.40% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8415106 1.30% 93.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 40812568 6.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 498403789 77.36% 77.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18180113 2.82% 80.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18298329 2.84% 83.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13344455 2.07% 85.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28485052 4.42% 89.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9005401 1.40% 90.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9710824 1.51% 92.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8365736 1.30% 93.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40479000 6.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647753829 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.200108 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.888379 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 203038997 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 318780583 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106758002 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13823689 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5350357 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19769330 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1403755 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 652115787 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4334955 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5350357 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 210763548 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 23644830 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 256196843 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 112721527 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 39074336 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 636556128 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 84527 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2214646 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1724456 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19278197 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3720 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 608321142 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 977030287 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 750414618 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 813643 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 510669806 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 97651331 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15437965 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13428690 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 76999253 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 102745060 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 86542127 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13847171 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14669306 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 603448531 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15520984 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 604287606 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 888730 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 83031386 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52028805 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 367516 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647753829 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.932897 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.658052 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 644272699 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200113 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.887999 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 200592206 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 318637226 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105865940 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13861849 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5313208 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 19620033 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1391095 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 647812132 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4304218 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5313208 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 208315491 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 23091878 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 256219950 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 111868936 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39460643 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 632346200 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 89809 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 2171113 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1552755 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19722377 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3888 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 605326116 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 973029596 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 745395954 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 835166 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 508286647 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97039469 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15581908 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13599233 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 77351395 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 101957824 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 85683722 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13730276 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14508656 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 599162654 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15675959 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 600368831 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 870257 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 82392045 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 51705579 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 355230 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 644272699 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.931855 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.655757 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 411149730 63.47% 63.47% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 99844018 15.41% 78.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43674585 6.74% 85.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31388880 4.85% 90.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23216755 3.58% 94.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 16246972 2.51% 96.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 11234988 1.73% 98.30% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6567238 1.01% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4430663 0.68% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 408550840 63.41% 63.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 100016688 15.52% 78.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 43398898 6.74% 85.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31119922 4.83% 90.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23055723 3.58% 94.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16110351 2.50% 96.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11122843 1.73% 98.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6496596 1.01% 99.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4400838 0.68% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647753829 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 644272699 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3092955 25.56% 25.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 25896 0.21% 25.78% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 3078 0.03% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4978648 41.15% 66.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3998858 33.05% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3033866 25.31% 25.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 23473 0.20% 25.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 1799 0.02% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4963680 41.42% 66.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3962195 33.06% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 54 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 409873437 67.83% 67.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1473632 0.24% 68.07% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 67911 0.01% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 190 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 71982 0.01% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 109389956 18.10% 86.20% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 83410380 13.80% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 407511218 67.88% 67.88% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1473925 0.25% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 66979 0.01% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 186 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 58109 0.01% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 108674321 18.10% 86.24% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 82583972 13.76% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 604287606 # Type of FU issued -system.cpu1.iq.rate 0.897634 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 12099435 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020023 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1868279780 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 702174546 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 581222842 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1037426 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 531508 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 461103 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 615834413 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 552574 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4729905 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 600368831 # Type of FU issued +system.cpu1.iq.rate 0.897265 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11985013 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019963 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1856828451 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 697391618 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 577348747 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1037180 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 532278 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 459183 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 611800062 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 553725 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4645881 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 17106229 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 20767 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 716806 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8739633 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16996855 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20011 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 704534 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8628630 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3947805 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8490514 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3900409 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 8595303 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5350357 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15089845 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 6765703 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 619117650 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1756443 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 102745060 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 86542127 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13138616 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 241917 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6436383 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 716806 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2534366 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2735696 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 5270062 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 597242145 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 107094882 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6118047 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5313208 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14601213 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6790244 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 614987274 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1737370 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 101957824 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 85683722 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 13306309 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 234327 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6472536 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 704534 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2511910 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2724374 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5236284 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 593397792 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 106407717 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6082445 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 148135 # number of nop insts executed -system.cpu1.iew.exec_refs 189434078 # number of memory reference insts executed -system.cpu1.iew.exec_branches 110489810 # Number of branches executed -system.cpu1.iew.exec_stores 82339196 # Number of stores executed -system.cpu1.iew.exec_rate 0.887169 # Inst execution rate -system.cpu1.iew.wb_sent 583107932 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 581683945 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 287154690 # num instructions producing a value -system.cpu1.iew.wb_consumers 498859903 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.864058 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575622 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 83090114 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15153468 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4526792 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 633652727 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.845792 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.838559 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 148661 # number of nop insts executed +system.cpu1.iew.exec_refs 187941905 # number of memory reference insts executed +system.cpu1.iew.exec_branches 109851293 # Number of branches executed +system.cpu1.iew.exec_stores 81534188 # Number of stores executed +system.cpu1.iew.exec_rate 0.886846 # Inst execution rate +system.cpu1.iew.wb_sent 579236319 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 577807930 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 285288573 # num instructions producing a value +system.cpu1.iew.wb_consumers 495728954 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.863547 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.575493 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 82442886 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 15320729 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4497993 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 630278595 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.844780 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835584 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 436801872 68.93% 68.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 97306167 15.36% 84.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33196725 5.24% 89.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 15570610 2.46% 91.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11096620 1.75% 93.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6694600 1.06% 94.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 6152090 0.97% 95.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3917687 0.62% 96.38% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22916356 3.62% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433887749 68.84% 68.84% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 97721864 15.50% 84.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 32952593 5.23% 89.57% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15389192 2.44% 92.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10994625 1.74% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6638239 1.05% 94.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6092126 0.97% 95.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3888165 0.62% 96.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22714042 3.60% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 633652727 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 456128288 # Number of instructions committed -system.cpu1.commit.committedOps 535938124 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 630278595 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 453286692 # Number of instructions committed +system.cpu1.commit.committedOps 532446568 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 163441324 # Number of memory references committed -system.cpu1.commit.loads 85638830 # Number of loads committed -system.cpu1.commit.membars 3762780 # Number of memory barriers committed -system.cpu1.commit.branches 101898340 # Number of branches committed -system.cpu1.commit.fp_insts 443284 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 491997101 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13483818 # Number of function calls committed. +system.cpu1.commit.refs 162016061 # Number of memory references committed +system.cpu1.commit.loads 84960969 # Number of loads committed +system.cpu1.commit.membars 3734725 # Number of memory barriers committed +system.cpu1.commit.branches 101308962 # Number of branches committed +system.cpu1.commit.fp_insts 440790 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 488486887 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13305521 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 371242424 69.27% 69.27% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1140857 0.21% 69.48% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 50916 0.01% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 62561 0.01% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 85638830 15.98% 85.48% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 77802494 14.52% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 369191199 69.34% 69.34% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1139544 0.21% 69.55% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 50295 0.01% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.56% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 49427 0.01% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.57% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 84960969 15.96% 85.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 77055092 14.47% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 535938124 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22916356 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1225792229 # The number of ROB reads -system.cpu1.rob.rob_writes 1252182686 # The number of ROB writes -system.cpu1.timesIdled 4237640 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 25446251 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 54234885938 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 456128288 # Number of Instructions Simulated -system.cpu1.committedOps 535938124 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.475901 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.475901 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.677552 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.677552 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 703163553 # number of integer regfile reads -system.cpu1.int_regfile_writes 415853151 # number of integer regfile writes -system.cpu1.fp_regfile_reads 819685 # number of floating regfile reads -system.cpu1.fp_regfile_writes 527216 # number of floating regfile writes -system.cpu1.cc_regfile_reads 127646217 # number of cc regfile reads -system.cpu1.cc_regfile_writes 128772606 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1207600226 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15276931 # number of misc regfile writes -system.iobus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40295 # Transaction distribution -system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.cpu1.commit.op_class_0::total 532446568 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22714042 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 1218446611 # The number of ROB reads +system.cpu1.rob.rob_writes 1243796841 # The number of ROB writes +system.cpu1.timesIdled 4173884 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 24837373 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46928670537 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 453286692 # Number of Instructions Simulated +system.cpu1.committedOps 532446568 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.476130 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.476130 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.677447 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.677447 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 698541221 # number of integer regfile reads +system.cpu1.int_regfile_writes 412892879 # number of integer regfile writes +system.cpu1.fp_regfile_reads 836436 # number of floating regfile reads +system.cpu1.fp_regfile_writes 478776 # number of floating regfile writes +system.cpu1.cc_regfile_reads 127759728 # number of cc regfile reads +system.cpu1.cc_regfile_writes 128888879 # number of cc regfile writes +system.cpu1.misc_regfile_reads 1201368002 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15442226 # number of misc regfile writes +system.iobus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40306 # Transaction distribution +system.iobus.trans_dist::ReadResp 40306 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1940,11 +1948,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230948 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230970 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353754 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1959,18 +1967,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334312 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492144 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47814500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47813000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 345500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 348500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1982,79 +1990,79 @@ system.iobus.reqLayer14.occupancy 9500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25714000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25706500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 40142500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568747115 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568865504 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147708000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147730000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.425592 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115466 # number of replacements +system.iocache.tags.tagsinuse 10.425537 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115482 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13089208185000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544364 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.881227 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221523 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430077 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651599 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13089208816000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.904041 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.521495 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.369003 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.282593 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651596 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039623 # Number of tag accesses -system.iocache.tags.data_accesses 1039623 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039722 # Number of tag accesses +system.iocache.tags.data_accesses 1039722 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8810 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8847 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8821 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8858 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115474 # number of demand (read+write) misses -system.iocache.demand_misses::total 115514 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115485 # number of demand (read+write) misses +system.iocache.demand_misses::total 115525 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115474 # number of overall misses -system.iocache.overall_misses::total 115514 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5085500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1644992106 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1650077606 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115485 # number of overall misses +system.iocache.overall_misses::total 115525 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5166000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1639680634 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1644846634 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12805896509 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12805896509 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5436500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14450888615 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14456325115 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5436500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14450888615 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14456325115 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12789916870 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12789916870 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5517000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14429597504 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14435114504 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5517000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14429597504 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14435114504 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8810 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8847 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8821 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8858 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115474 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115514 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115485 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115525 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115474 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115514 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115485 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115525 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2068,53 +2076,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137445.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 186718.740749 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 186512.671640 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 139621.621622 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 185883.758531 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 185690.520885 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120058.281229 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120058.281229 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 125144.089709 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 125147.818576 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135912.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 125144.089709 # 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Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4278.290194 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 23306.302204 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 255.590373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 270.257283 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2928.362959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 24620.242304 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.141058 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003571 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004303 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.065282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.355626 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5073 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54349 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.959473 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 452419027 # Number of tag accesses -system.l2c.tags.data_accesses 452419027 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.l2c.ReadReq_hits::cpu0.dtb.walker 530836 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 183475 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 545490 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 182908 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1442709 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8255712 # 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number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8280218 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4366494 # number of demand (read+write) hits -system.l2c.demand_hits::total 26474941 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 530836 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 183475 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8081848 # number of overall hits -system.l2c.overall_hits::cpu0.data 4303672 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 545490 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 182908 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8280218 # number of overall hits -system.l2c.overall_hits::cpu1.data 4366494 # number of overall hits -system.l2c.overall_hits::total 26474941 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2747 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2312 # 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number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 7138997999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005139 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.007171 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2666808000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 7139023499 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005377 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013564 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005409 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.013117 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.007381 # mshr miss rate for ReadReq accesses system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.782486 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784945 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783715 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.153846 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.266360 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012326 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.090839 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005332 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.013295 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006009 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.095347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036211 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79480.672502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # 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average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 92209.119710 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76171.553698 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80764.461337 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 82677.046081 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81839.627062 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20804.352231 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20903.544980 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20848.855624 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79973.799127 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76247.904832 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88468.255214 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78926.984952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80245.841785 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76104.413936 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 88572.896818 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87260.977881 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 91994.532955 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 92522.282420 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 92263.003062 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 76215.948734 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 80613.042243 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 83179.567594 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 81929.786467 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20807.504530 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20901.302761 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20849.371468 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87968.507633 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 89180.270785 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 87325.160425 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78403.491449 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80889.556983 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76403.188850 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87968.507633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78283.557273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79847.693647 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76035.170180 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 89180.270785 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 87325.160425 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176820.593774 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177835.619506 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169639.415077 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131429.691796 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168582.590556 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131430.161254 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62829.433912 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84999.307719 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86446.996707 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 62734.268293 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 88892.873910 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.151497 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 3206101 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1605959 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3062 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87053.861722 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 81111.441220 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 3173701 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1572230 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3254 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 54318 # Transaction distribution -system.membus.trans_dist::ReadResp 484167 # Transaction distribution +system.membus.trans_dist::ReadResp 484946 # Transaction distribution system.membus.trans_dist::WriteReq 33697 # Transaction distribution system.membus.trans_dist::WriteResp 33697 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1312198 # Transaction distribution -system.membus.trans_dist::CleanEvict 224447 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37872 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1311989 # Transaction distribution +system.membus.trans_dist::CleanEvict 225778 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4711 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 573072 # Transaction distribution -system.membus.trans_dist::ReadExResp 573072 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 429849 # Transaction distribution -system.membus.trans_dist::InvalidateReq 628542 # Transaction distribution +system.membus.trans_dist::ReadExReq 574465 # Transaction distribution +system.membus.trans_dist::ReadExResp 574465 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 430628 # Transaction distribution +system.membus.trans_dist::InvalidateReq 626011 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4014812 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4144458 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4382045 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3984552 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4114198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237454 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4351652 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142074284 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 142246058 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7247872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7247872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 149493930 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2896 # Total snoops (count) -system.membus.snoopTraffic 184832 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 1757355 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019576 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.138538 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 142199148 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 142370922 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7237952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7237952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 149608874 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3063 # Total snoops (count) +system.membus.snoopTraffic 195520 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1723835 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019089 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.136837 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1722953 98.04% 98.04% # Request fanout histogram -system.membus.snoop_fanout::1 34402 1.96% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1690929 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::1 32906 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1757355 # Request fanout histogram -system.membus.reqLayer0.occupancy 114108500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1723835 # Request fanout histogram +system.membus.reqLayer0.occupancy 114103500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5404000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5424500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8771663634 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8729629317 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5453450415 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5464439160 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44589202 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44651356 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2777,89 +2782,89 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 55371072 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 28119352 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4995 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 55313500 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 28081340 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 5055 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 1866 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 1866 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317223946000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 2053309 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25890690 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51317217215000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 2056199 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25877432 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9461280 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16455852 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2755609 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 47371 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 47384 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2180359 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2180359 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16456589 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7382467 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1266004 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1234707 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49409857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32615082 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 883766 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2568418 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 85477123 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107688320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1140469546 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2969568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8655976 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3259783410 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2003011 # Total snoops (count) -system.toL2Bus.snoopTraffic 81599088 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 30844610 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026862 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.161680 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 9451504 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16451372 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2751395 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31429 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 31450 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2177126 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2177126 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16452157 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7370941 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1264166 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1234557 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49396440 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32537915 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 866839 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2547134 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 85348328 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2107113280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1138900522 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2824688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8472048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3257310538 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2046689 # Total snoops (count) +system.toL2Bus.snoopTraffic 81942376 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 30811624 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026814 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.161540 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 30016066 97.31% 97.31% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 828544 2.69% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29985433 97.32% 97.32% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 826191 2.68% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30844610 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 53049239176 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 30811624 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 53009049492 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1413407 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1413410 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24732629203 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24725297607 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 15040354777 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 15008598618 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 512966184 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 514146176 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1489584962 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1491177210 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16437 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16436 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |