diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3 | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 4433 |
1 files changed, 2225 insertions, 2208 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index e1c1def32..272e9258d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.284914 # Number of seconds simulated -sim_ticks 51284914333000 # Number of ticks simulated -final_tick 51284914333000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.761757 # Number of seconds simulated +sim_ticks 51761756862000 # Number of ticks simulated +final_tick 51761756862000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 235872 # Simulator instruction rate (inst/s) -host_op_rate 277167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13557886882 # Simulator tick rate (ticks/s) -host_mem_usage 696464 # Number of bytes of host memory used -host_seconds 3782.66 # Real time elapsed on the host -sim_insts 892223547 # Number of instructions simulated -sim_ops 1048428696 # Number of ops (including micro ops) simulated +host_inst_rate 265912 # Simulator instruction rate (inst/s) +host_op_rate 283734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5899295346 # Simulator tick rate (ticks/s) +host_mem_usage 696216 # Number of bytes of host memory used +host_seconds 8774.23 # Real time elapsed on the host +sim_insts 2333170820 # Number of instructions simulated +sim_ops 2489548001 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 145024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 130496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3660544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 27123808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 158784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 143040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3643072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 26095080 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 424512 # Number of bytes read from this memory -system.physmem.bytes_read::total 61524360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3660544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3643072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7303616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79842048 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 151872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 131712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3595840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25977120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 153216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 139456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3729408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 26080296 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 414272 # Number of bytes read from this memory +system.physmem.bytes_read::total 60373192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3595840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3729408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7325248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78844864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 79862628 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2266 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 57196 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 423818 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2481 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 407740 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6633 # Number of read requests responded to by this memory -system.physmem.num_reads::total 961331 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1247532 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78865444 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2058 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 56185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 405901 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2394 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2179 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58272 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 407509 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6473 # Number of read requests responded to by this memory +system.physmem.num_reads::total 943344 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1231951 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1250105 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2828 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1234524 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2934 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 2545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 71377 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 528885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 71036 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 508826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1199658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 71377 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 71036 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 142413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1556833 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 501859 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2960 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 503853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1166367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69469 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72049 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 141519 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1523226 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1557234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1556833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1523624 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1523226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2934 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 71377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 528885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 71036 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 509227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2756892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 961331 # Number of read requests accepted -system.physmem.writeReqs 1250105 # Number of write requests accepted -system.physmem.readBursts 961331 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1250105 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61479104 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 46080 # Total number of bytes read from write queue -system.physmem.bytesWritten 79862656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61524360 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 79862628 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 720 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu0.inst 69469 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 501859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 504250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8003 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2689991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 943344 # Number of read requests accepted +system.physmem.writeReqs 1234524 # Number of write requests accepted +system.physmem.readBursts 943344 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1234524 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60330432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 43584 # Total number of bytes read from write queue +system.physmem.bytesWritten 78865536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 60373192 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78865444 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 681 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54441 # Per bank write bursts -system.physmem.perBankRdBursts::1 61427 # Per bank write bursts -system.physmem.perBankRdBursts::2 55898 # Per bank write bursts -system.physmem.perBankRdBursts::3 54692 # Per bank write bursts -system.physmem.perBankRdBursts::4 58805 # Per bank write bursts -system.physmem.perBankRdBursts::5 68407 # Per bank write bursts -system.physmem.perBankRdBursts::6 58313 # Per bank write bursts -system.physmem.perBankRdBursts::7 55590 # Per bank write bursts -system.physmem.perBankRdBursts::8 55296 # Per bank write bursts -system.physmem.perBankRdBursts::9 81756 # Per bank write bursts -system.physmem.perBankRdBursts::10 60407 # Per bank write bursts -system.physmem.perBankRdBursts::11 65146 # Per bank write bursts -system.physmem.perBankRdBursts::12 55694 # Per bank write bursts -system.physmem.perBankRdBursts::13 60470 # Per bank write bursts -system.physmem.perBankRdBursts::14 57025 # Per bank write bursts -system.physmem.perBankRdBursts::15 57244 # Per bank write bursts -system.physmem.perBankWrBursts::0 74045 # Per bank write bursts -system.physmem.perBankWrBursts::1 78136 # Per bank write bursts -system.physmem.perBankWrBursts::2 75823 # Per bank write bursts -system.physmem.perBankWrBursts::3 77240 # Per bank write bursts -system.physmem.perBankWrBursts::4 78053 # Per bank write bursts -system.physmem.perBankWrBursts::5 84172 # Per bank write bursts -system.physmem.perBankWrBursts::6 76930 # Per bank write bursts -system.physmem.perBankWrBursts::7 76507 # Per bank write bursts -system.physmem.perBankWrBursts::8 76285 # Per bank write bursts -system.physmem.perBankWrBursts::9 81372 # Per bank write bursts -system.physmem.perBankWrBursts::10 77794 # Per bank write bursts -system.physmem.perBankWrBursts::11 82580 # Per bank write bursts -system.physmem.perBankWrBursts::12 74509 # Per bank write bursts -system.physmem.perBankWrBursts::13 79277 # Per bank write bursts -system.physmem.perBankWrBursts::14 77656 # Per bank write bursts -system.physmem.perBankWrBursts::15 77475 # Per bank write bursts +system.physmem.perBankRdBursts::0 54550 # Per bank write bursts +system.physmem.perBankRdBursts::1 62293 # Per bank write bursts +system.physmem.perBankRdBursts::2 54512 # Per bank write bursts +system.physmem.perBankRdBursts::3 54260 # Per bank write bursts +system.physmem.perBankRdBursts::4 56553 # Per bank write bursts +system.physmem.perBankRdBursts::5 67360 # Per bank write bursts +system.physmem.perBankRdBursts::6 57276 # Per bank write bursts +system.physmem.perBankRdBursts::7 56002 # Per bank write bursts +system.physmem.perBankRdBursts::8 51757 # Per bank write bursts +system.physmem.perBankRdBursts::9 79766 # Per bank write bursts +system.physmem.perBankRdBursts::10 59095 # Per bank write bursts +system.physmem.perBankRdBursts::11 64327 # Per bank write bursts +system.physmem.perBankRdBursts::12 57398 # Per bank write bursts +system.physmem.perBankRdBursts::13 60635 # Per bank write bursts +system.physmem.perBankRdBursts::14 53657 # Per bank write bursts +system.physmem.perBankRdBursts::15 53222 # Per bank write bursts +system.physmem.perBankWrBursts::0 73571 # Per bank write bursts +system.physmem.perBankWrBursts::1 79159 # Per bank write bursts +system.physmem.perBankWrBursts::2 74534 # Per bank write bursts +system.physmem.perBankWrBursts::3 76045 # Per bank write bursts +system.physmem.perBankWrBursts::4 77226 # Per bank write bursts +system.physmem.perBankWrBursts::5 85193 # Per bank write bursts +system.physmem.perBankWrBursts::6 75384 # Per bank write bursts +system.physmem.perBankWrBursts::7 76786 # Per bank write bursts +system.physmem.perBankWrBursts::8 72797 # Per bank write bursts +system.physmem.perBankWrBursts::9 79168 # Per bank write bursts +system.physmem.perBankWrBursts::10 77101 # Per bank write bursts +system.physmem.perBankWrBursts::11 81604 # Per bank write bursts +system.physmem.perBankWrBursts::12 76385 # Per bank write bursts +system.physmem.perBankWrBursts::13 80183 # Per bank write bursts +system.physmem.perBankWrBursts::14 73603 # Per bank write bursts +system.physmem.perBankWrBursts::15 73535 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 33 # Number of times write queue was full causing retry -system.physmem.totGap 51284913090000 # Total gap between requests +system.physmem.numWrRetry 35 # Number of times write queue was full causing retry +system.physmem.totGap 51761755618000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 961316 # Read request sizes (log2) +system.physmem.readPktSize::6 943329 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1247532 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 543719 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 274396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 94312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 42532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 135 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1231951 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 533668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 268938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 92505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 42053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 700 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 555 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 1175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 721 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 118 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 87 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -165,172 +165,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 28650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 34467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 48429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 67048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 70774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 72215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 72774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 82935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 89855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 76735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 77015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 82497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 72294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 70858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 68160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 96 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 561177 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 251.866630 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 150.815130 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 291.463467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 247728 44.14% 44.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 140365 25.01% 69.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53282 9.49% 78.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 26503 4.72% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 19913 3.55% 86.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11301 2.01% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10454 1.86% 90.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6842 1.22% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 44789 7.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 561177 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 64799 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.824287 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 53.599336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 64791 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 28091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 34078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 47379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 52985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 65862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 69793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 71135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 82317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 75479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 88731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 75996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 76486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 81843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 71355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 67349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 3609 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 94 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 547235 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 254.361625 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 151.756737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 294.209115 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 240904 44.02% 44.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 136237 24.90% 68.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52010 9.50% 78.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 25504 4.66% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19543 3.57% 86.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10827 1.98% 88.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10251 1.87% 90.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6912 1.26% 91.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 45047 8.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 547235 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 63900 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.751831 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 54.006816 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 63893 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2560-3071 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-5119 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7680-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-9727 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 64799 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 64799 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.257303 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.378904 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.471332 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 63900 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 63900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.284413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.392697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 8.437503 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-7 96 0.15% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 63 0.10% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 55368 85.45% 85.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6790 10.48% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 705 1.09% 97.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 466 0.72% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 493 0.76% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 108 0.17% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 328 0.51% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 159 0.25% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 155 0.24% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 74 0.12% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 54483 85.26% 85.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 6734 10.54% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 692 1.08% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 454 0.71% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 539 0.84% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 107 0.17% 98.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 351 0.55% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 150 0.23% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 153 0.24% 99.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::88-95 9 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 3 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.00% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 2 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-111 6 0.01% 99.92% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::112-119 5 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 16 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 10 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 7 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 11 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 15 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-167 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-175 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 5 0.01% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::328-335 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 64799 # Writes before turning the bus around for reads -system.physmem.totQLat 25248874155 # Total ticks spent queuing -system.physmem.totMemAccLat 43260330405 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4803055000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26284.18 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 63900 # Writes before turning the bus around for reads +system.physmem.totQLat 25011662426 # Total ticks spent queuing +system.physmem.totMemAccLat 42686593676 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4713315000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26532.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45034.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.20 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45282.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.17 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.54 # Average write queue length when enqueuing -system.physmem.readRowHits 736430 # Number of row buffer hits during reads -system.physmem.writeRowHits 910858 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.66 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.99 # Row buffer hit rate for writes -system.physmem.avgGap 23190774.27 # Average gap between requests -system.physmem.pageHitRate 74.59 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2124654840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1159285875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3647069400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4023470880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3349681296000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1235871193320 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29686851168000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34283358138315 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.488160 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49386595452825 # Time in different power states -system.physmem_0.memoryStateTime::REF 1712515740000 # Time in different power states +system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing +system.physmem.avgWrQLen 9.19 # Average write queue length when enqueuing +system.physmem.readRowHits 724331 # Number of row buffer hits during reads +system.physmem.writeRowHits 903369 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.31 # Row buffer hit rate for writes +system.physmem.avgGap 23767168.45 # Average gap between requests +system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2099502720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1145562000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3609886800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4003979040 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3380826018960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1247139310140 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29963069496750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34601893756410 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.483818 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49846129273502 # Time in different power states +system.physmem_0.memoryStateTime::REF 1728438660000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 185803070925 # Time in different power states +system.physmem_0.memoryStateTime::ACT 187184326498 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2117843280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1155569250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3845696400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4062623040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3349681296000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1240883143470 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29682454712250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34284200883690 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.504593 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49379236035062 # Time in different power states -system.physmem_1.memoryStateTime::REF 1712515740000 # Time in different power states +system.physmem_1.actEnergy 2037593880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1111782375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3742837800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3981156480 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3380826018960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1247115577050 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29963090307000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34601905273545 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.484040 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49846127379717 # Time in different power states +system.physmem_1.memoryStateTime::REF 1728438660000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 193162474938 # Time in different power states +system.physmem_1.memoryStateTime::ACT 187190202783 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -346,29 +347,33 @@ system.realview.nvmem.num_reads::total 38 # Nu system.realview.nvmem.bw_read::cpu0.inst 21 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 20 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 42 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 41 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 21 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 20 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 41 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 21 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 20 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 42 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 41 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131222767 # Number of BP lookups -system.cpu0.branchPred.condPredicted 88895341 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5715566 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 88848195 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 63996903 # Number of BTB hits +system.cpu0.branchPred.lookups 441769882 # Number of BP lookups +system.cpu0.branchPred.condPredicted 346318853 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5806285 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 315736094 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 267112052 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.029491 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17247708 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 186935 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 84.599784 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17170317 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 190049 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 5021410 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 2619937 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 2401473 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 415468 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -399,89 +404,93 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 901787 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 901787 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17510 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90865 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 558240 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 343547 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2647.495103 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 15829.601271 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-65535 340846 99.21% 99.21% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-131071 1379 0.40% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-196607 917 0.27% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-262143 154 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-327679 149 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-393215 34 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-458751 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-524287 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 343547 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 423455 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 23285.712768 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18859.753792 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 19582.519957 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 414421 97.87% 97.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6698 1.58% 99.45% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1655 0.39% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 334 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 125 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 53 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 17 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 892710 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 892710 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17744 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 89453 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 550305 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 342405 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2673.589755 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 15902.851063 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 339616 99.19% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1452 0.42% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 967 0.28% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 143 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 137 0.04% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 33 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 35 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 342405 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 416567 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23523.175143 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 18877.823931 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 19885.199602 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 406963 97.69% 97.69% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7350 1.76% 99.46% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1585 0.38% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 137 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 275 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 156 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 65 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 27 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 423455 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 376351808512 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.148701 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.701209 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 375305951012 99.72% 99.72% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 568976500 0.15% 99.87% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 204601500 0.05% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 126494000 0.03% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 49142500 0.01% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 26958000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 28402000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 34222000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 6583500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 370000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 35500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::44-47 29500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 42000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 376351808512 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90865 83.84% 83.84% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17510 16.16% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 108375 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 901787 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 416567 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 844595026420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.078472 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.490568 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 843548733920 99.88% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 573107500 0.07% 99.94% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 199238500 0.02% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 117034000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 49115000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 33953000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 28746000 0.00% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 36613000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 8069500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 361500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::44-47 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::48-51 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::56-59 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::60-63 2000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 844595026420 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 89453 83.45% 83.45% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 17744 16.55% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107197 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 892710 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 901787 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108375 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 892710 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107197 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108375 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1010162 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107197 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 999907 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 104844993 # DTB read hits -system.cpu0.dtb.read_misses 617686 # DTB read misses -system.cpu0.dtb.write_hits 81833158 # DTB write hits -system.cpu0.dtb.write_misses 284101 # DTB write misses -system.cpu0.dtb.flush_tlb 1099 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 311659377 # DTB read hits +system.cpu0.dtb.read_misses 618746 # DTB read misses +system.cpu0.dtb.write_hits 81669046 # DTB write hits +system.cpu0.dtb.write_misses 273964 # DTB write misses +system.cpu0.dtb.flush_tlb 1566 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21489 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 548 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56009 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 176 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9405 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 21904 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 550 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56873 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9024 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 58104 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105462679 # DTB read accesses -system.cpu0.dtb.write_accesses 82117259 # DTB write accesses +system.cpu0.dtb.perms_faults 58972 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 312278123 # DTB read accesses +system.cpu0.dtb.write_accesses 81943010 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 186678151 # DTB hits -system.cpu0.dtb.misses 901787 # DTB misses -system.cpu0.dtb.accesses 187579938 # DTB accesses +system.cpu0.dtb.hits 393328423 # DTB hits +system.cpu0.dtb.misses 892710 # DTB misses +system.cpu0.dtb.accesses 394221133 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,831 +520,832 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 105051 # Table walker walks requested -system.cpu0.itb.walker.walksLong 105051 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3103 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71842 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14498 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 90553 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1891.361965 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 11942.072265 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 89471 98.81% 98.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 577 0.64% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 86 0.09% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 126 0.14% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 214 0.24% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 41 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 90553 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 89443 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 29726.837204 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 24825.436238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 23450.909148 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 87272 97.57% 97.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 672 0.75% 98.32% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 1265 1.41% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 85 0.10% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 111 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 21 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 100670 # Table walker walks requested +system.cpu0.itb.walker.walksLong 100670 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3435 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68577 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 13827 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 86843 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1681.770551 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 11901.774457 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 85828 98.83% 98.83% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 525 0.60% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 54 0.06% 99.50% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 177 0.20% 99.70% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 176 0.20% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 42 0.05% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 17 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 86843 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 85839 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 29252.396929 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 24357.820404 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 23461.302389 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 83908 97.75% 97.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 516 0.60% 98.35% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 1196 1.39% 99.74% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.09% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 102 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 89443 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 402102979288 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.378343 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -152052427072 -37.81% -37.81% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 554084756860 137.80% 99.98% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 62143500 0.02% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 7613500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 640000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 190500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 62000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 402102979288 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 71842 95.86% 95.86% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3103 4.14% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 74945 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 85839 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 638425660712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.889219 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.314244 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 70792067924 11.09% 11.09% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 567575291288 88.90% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 51231500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6018000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 857500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 106500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 88000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 638425660712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 68577 95.23% 95.23% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 3435 4.77% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72012 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105051 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105051 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 100670 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 100670 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74945 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74945 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 179996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 94456447 # ITB inst hits -system.cpu0.itb.inst_misses 105051 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72012 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72012 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 172682 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 300349481 # ITB inst hits +system.cpu0.itb.inst_misses 100670 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1099 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1566 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21489 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 548 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 41420 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21904 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 550 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 41410 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 203143 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 188775 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 94561498 # ITB inst accesses -system.cpu0.itb.hits 94456447 # DTB hits -system.cpu0.itb.misses 105051 # DTB misses -system.cpu0.itb.accesses 94561498 # DTB accesses -system.cpu0.numCycles 688838520 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 300450151 # ITB inst accesses +system.cpu0.itb.hits 300349481 # DTB hits +system.cpu0.itb.misses 100670 # DTB misses +system.cpu0.itb.accesses 300450151 # DTB accesses +system.cpu0.numCycles 1153591288 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 245587927 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 584587978 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 131222767 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 81244611 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 399140958 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13083080 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2697287 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 23591 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 4020 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5373314 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 168933 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 3234 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 94235768 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3541356 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 41927 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 659540531 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.038718 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.291266 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 452660277 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 1310968350 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 441769882 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 286902306 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 657569557 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13257965 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2520501 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 22487 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 4210 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 4808989 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 163286 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 3813 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 300145403 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3627233 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 38474 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 1124381714 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.254786 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.113096 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 515133348 78.10% 78.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18089863 2.74% 80.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18214710 2.76% 83.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13345415 2.02% 85.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28172960 4.27% 89.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9014281 1.37% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9743812 1.48% 92.75% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8313958 1.26% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 39512184 5.99% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 722021873 64.22% 64.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 121051325 10.77% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18164334 1.62% 76.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13282328 1.18% 77.78% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 182681747 16.25% 94.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 8985206 0.80% 94.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9665427 0.86% 95.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8249650 0.73% 96.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 40279824 3.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 659540531 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.190499 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.848658 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 199724344 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 336015345 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 105250676 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13405220 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5142823 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19593113 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1418693 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 638893412 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4361205 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5142823 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 207245201 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 27037727 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 261836460 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 110999671 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 47276188 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 624046996 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 101675 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2286594 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1931238 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 27774354 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 3807 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 596597233 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 959951672 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 737729971 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 774177 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 503848315 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 92748918 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15071360 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13097285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 74895654 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 100276299 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 85965913 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13583222 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14599367 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 592457087 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15151612 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 594148769 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 834633 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 77960575 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 49583395 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 368092 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 659540531 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.900853 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.637513 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 1124381714 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.382952 # Number of branch fetches per cycle +system.cpu0.fetch.rate 1.136424 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 405971329 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 336686919 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 362849881 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13601656 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5263930 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 71142613 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1385162 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 1364494980 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4266008 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5263930 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 413565658 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 26498073 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 263444659 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 368730385 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 46870910 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 1349255091 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 116974 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2261616 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1896807 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 27181012 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3751 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 1320809578 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1942299251 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1409770765 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 775838 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 1225247186 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 95562392 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15257380 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13270852 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 75639942 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 307378259 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 85793639 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13768177 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14589388 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 1316697465 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15319190 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 1317684473 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 854895 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 81379212 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 50931090 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 359979 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 1124381714 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 1.171919 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.498403 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 427069171 64.75% 64.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 97668979 14.81% 79.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 43298472 6.56% 86.13% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 30774138 4.67% 90.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 22917395 3.47% 94.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16090465 2.44% 96.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10921608 1.66% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6493545 0.98% 99.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4306758 0.65% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 479017696 42.60% 42.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 355860200 31.65% 74.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 94607581 8.41% 82.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 82377744 7.33% 89.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 74414845 6.62% 96.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16123062 1.43% 98.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11093083 0.99% 99.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6457333 0.57% 99.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4430170 0.39% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 659540531 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 1124381714 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3033811 25.57% 25.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 25491 0.21% 25.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 3073 0.03% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 1 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4852849 40.90% 66.71% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3949019 33.29% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 3027806 25.46% 25.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 21993 0.18% 25.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 1913 0.02% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4879295 41.03% 66.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3961438 33.31% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 26 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 402837369 67.80% 67.80% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1388159 0.23% 68.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 66027 0.01% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 24 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 5 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.05% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 70383 0.01% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 106898292 17.99% 86.05% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82888484 13.95% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 919558912 69.79% 69.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1403204 0.11% 69.89% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 63552 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 184 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 53817 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.90% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 313882941 23.82% 93.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82721833 6.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 594148769 # Type of FU issued -system.cpu0.iq.rate 0.862537 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11864244 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019968 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1859480838 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 685772005 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 572455649 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1056108 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 523485 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 471348 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 605449446 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 563541 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4712997 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 1317684473 # Type of FU issued +system.cpu0.iq.rate 1.142246 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11892445 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.009025 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 3771522724 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 1413606609 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 1295090800 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 975276 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 499965 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 431562 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 1329056054 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 520834 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4724292 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 15710215 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 20540 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 737635 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 8733080 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16714956 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 20317 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 722500 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 8583352 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3961996 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8114796 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3995442 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8184292 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5142823 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15863683 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 9219529 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 607741320 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1739282 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 100276299 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 85965913 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 12807299 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 229576 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 8904673 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 737635 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2585247 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2254078 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 4839325 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 587599487 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 104834587 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 5659877 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5263930 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15793558 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 8769722 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 1332158998 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1730842 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 307378259 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 85793639 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12984237 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 229560 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 8457997 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 722500 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2474503 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2706494 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5180997 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 1310764150 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 311649701 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 6040737 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 132621 # number of nop insts executed -system.cpu0.iew.exec_refs 186666893 # number of memory reference insts executed -system.cpu0.iew.exec_branches 108670121 # Number of branches executed -system.cpu0.iew.exec_stores 81832306 # Number of stores executed -system.cpu0.iew.exec_rate 0.853029 # Inst execution rate -system.cpu0.iew.wb_sent 574140659 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 572926997 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 282868675 # num instructions producing a value -system.cpu0.iew.wb_consumers 490940827 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.831729 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576177 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 78001898 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14783520 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4316576 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 646201132 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.819634 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.819531 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 142343 # number of nop insts executed +system.cpu0.iew.exec_refs 393318158 # number of memory reference insts executed +system.cpu0.iew.exec_branches 417986859 # Number of branches executed +system.cpu0.iew.exec_stores 81668457 # Number of stores executed +system.cpu0.iew.exec_rate 1.136247 # Inst execution rate +system.cpu0.iew.wb_sent 1296930060 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 1295522362 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 592614892 # num instructions producing a value +system.cpu0.iew.wb_consumers 1110609614 # num instructions consuming a value +system.cpu0.iew.wb_rate 1.123034 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.533594 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 81425087 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14959211 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4440844 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 1110541032 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 1.126151 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.560922 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 452584963 70.04% 70.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 95102471 14.72% 84.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 32986108 5.10% 89.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15275406 2.36% 92.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10838243 1.68% 93.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6597010 1.02% 94.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6118779 0.95% 95.87% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 3888693 0.60% 96.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22809459 3.53% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 504262189 45.41% 45.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 302033951 27.20% 72.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 135703334 12.22% 84.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 118428443 10.66% 95.49% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10778674 0.97% 96.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6605089 0.59% 97.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6100457 0.55% 97.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3862548 0.35% 97.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22766347 2.05% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 646201132 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 450421520 # Number of instructions committed -system.cpu0.commit.committedOps 529648124 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 1110541032 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 1171621966 # Number of instructions committed +system.cpu0.commit.committedOps 1250637443 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 161798917 # Number of memory references committed -system.cpu0.commit.loads 84566084 # Number of loads committed -system.cpu0.commit.membars 3697077 # Number of memory barriers committed -system.cpu0.commit.branches 100455887 # Number of branches committed -system.cpu0.commit.fp_insts 452989 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 486555488 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13358896 # Number of function calls committed. +system.cpu0.commit.refs 367873590 # Number of memory references committed +system.cpu0.commit.loads 290663303 # Number of loads committed +system.cpu0.commit.membars 3675290 # Number of memory barriers committed +system.cpu0.commit.branches 409547032 # Number of branches committed +system.cpu0.commit.fp_insts 413703 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 1052721176 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13293497 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 366654710 69.23% 69.23% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1084981 0.20% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 49052 0.01% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 60464 0.01% 69.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 84566084 15.97% 85.42% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 77232833 14.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 881582024 70.49% 70.49% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1088872 0.09% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 47670 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.58% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 45287 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.59% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 290663303 23.24% 93.83% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77210287 6.17% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 529648124 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22809459 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 1227111262 # The number of ROB reads -system.cpu0.rob.rob_writes 1228659759 # The number of ROB writes -system.cpu0.timesIdled 4168425 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 29297989 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 52558178888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 450421520 # Number of Instructions Simulated -system.cpu0.committedOps 529648124 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.529320 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.529320 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.653885 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.653885 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 692871015 # number of integer regfile reads -system.cpu0.int_regfile_writes 409283768 # number of integer regfile writes -system.cpu0.fp_regfile_reads 840073 # number of floating regfile reads -system.cpu0.fp_regfile_writes 520676 # number of floating regfile writes -system.cpu0.cc_regfile_reads 125256927 # number of cc regfile reads -system.cpu0.cc_regfile_writes 126444735 # number of cc regfile writes -system.cpu0.misc_regfile_reads 1205784103 # number of misc regfile reads -system.cpu0.misc_regfile_writes 14898501 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10501142 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.972965 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 301139944 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10501654 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.675478 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 1250637443 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22766347 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 2415886012 # The number of ROB reads +system.cpu0.rob.rob_writes 2677991243 # The number of ROB writes +system.cpu0.timesIdled 4174406 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 29209574 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 53218608185 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 1171621966 # Number of Instructions Simulated +system.cpu0.committedOps 1250637443 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.984610 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.984610 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.015630 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.015630 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 1363459198 # number of integer regfile reads +system.cpu0.int_regfile_writes 822633893 # number of integer regfile writes +system.cpu0.fp_regfile_reads 827834 # number of floating regfile reads +system.cpu0.fp_regfile_writes 497604 # number of floating regfile writes +system.cpu0.cc_regfile_reads 434759871 # number of cc regfile reads +system.cpu0.cc_regfile_writes 435903549 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2497252569 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15072789 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10543122 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.973214 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 714246594 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10543634 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 67.741975 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 283.786006 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 228.186958 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.554270 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.445678 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 297.299431 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 214.673783 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.580663 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.419285 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999948 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 31 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 328 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1328578657 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1328578657 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 80009056 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 78798981 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 158808037 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68012932 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 65999758 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 134012690 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208369 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 195084 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403453 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 179648 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 145985 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 325633 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1753394 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1750601 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3503995 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2032610 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2004742 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4037352 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 148021988 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 144798739 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 292820727 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 148230357 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 144993823 # number of overall hits -system.cpu0.dcache.overall_hits::total 293224180 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6357220 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6148463 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 12505683 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6421340 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6320780 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 12742120 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 669394 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 622164 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1291558 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 582632 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 655096 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1237728 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 338660 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 312329 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 650989 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 12778560 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 12469243 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 25247803 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13447954 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13091407 # number of overall misses -system.cpu0.dcache.overall_misses::total 26539361 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 113432290500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111261752500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 224694043000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 290110885686 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 282708053542 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 572818939228 # number of WriteReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23410744708 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 29897786698 # number of WriteLineReq miss cycles -system.cpu0.dcache.WriteLineReq_miss_latency::total 53308531406 # number of WriteLineReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4664047500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4362445500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 9026493000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 83000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 193500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 276500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 403543176186 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 393969806042 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 797512982228 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 403543176186 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 393969806042 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 797512982228 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 86366276 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 84947444 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 171313720 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74434272 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 72320538 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 146754810 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 877763 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 817248 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1695011 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 762280 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 801081 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.WriteLineReq_accesses::total 1563361 # number of WriteLineReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2092054 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2062930 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4154984 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2032616 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2004746 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4037362 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 160800548 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 157267982 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 318068530 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 161678311 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 158085230 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 319763541 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073608 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.072380 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.072999 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086269 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.087400 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.086826 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762614 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.761292 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.761976 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.764328 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.817765 # miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_miss_rate::total 0.791710 # miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.161879 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.151401 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.156677 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.tags.tag_accesses 2981506473 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 2981506473 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 286698087 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 284974964 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 571673051 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67938381 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 66316619 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 134255000 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207203 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 195617 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 402820 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177871 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 146629 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 324500 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1740566 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1760771 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3501337 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2018486 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2021987 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4040473 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 354636468 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 351291583 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 705928051 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 354843671 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 351487200 # number of overall hits +system.cpu0.dcache.overall_hits::total 706330871 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6383220 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6242093 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 12625313 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6497631 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6239975 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 12737606 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 683741 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 608697 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1292438 # number of SoftPFReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu0.data 573671 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::cpu1.data 664585 # number of WriteLineReq misses +system.cpu0.dcache.WriteLineReq_misses::total 1238256 # number of WriteLineReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 331614 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 318292 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 649906 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 12880851 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 12482068 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 25362919 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 13564592 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 13090765 # number of overall misses +system.cpu0.dcache.overall_misses::total 26655357 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110753552000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 111947542000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 222701094000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 287335391122 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 284659105303 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 571994496425 # number of WriteReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 22737846434 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 30047699861 # number of WriteLineReq miss cycles +system.cpu0.dcache.WriteLineReq_miss_latency::total 52785546295 # number of WriteLineReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4579227500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4402893000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 8982120500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 138500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 96000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 234500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 398088943122 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 396606647303 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 794695590425 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 398088943122 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 396606647303 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 794695590425 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 293081307 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 291217057 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 584298364 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74436012 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 72556594 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 146992606 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 890944 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 804314 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1695258 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 751542 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 811214 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.WriteLineReq_accesses::total 1562756 # number of WriteLineReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072180 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2079063 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4151243 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2018491 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2021989 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4040480 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 367517319 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 363773651 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 731290970 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 368408263 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 364577965 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 732986228 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021780 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.021435 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.021608 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.087291 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.086001 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.086655 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767434 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.756790 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762384 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763325 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.819247 # miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_miss_rate::total 0.792354 # miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.160031 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.153094 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.156557 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.079468 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.079287 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.079379 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.083177 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.082812 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.082997 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17843.065129 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 18095.864365 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17967.354762 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45179.181555 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44726.766877 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44954.759430 # average WriteReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 40181.014273 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45638.786831 # average WriteLineReq miss latency -system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 43069.665877 # average WriteLineReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13772.064903 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13967.468599 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13865.814937 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13833.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 48375 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27650 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31579.706648 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31595.326680 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31587.420982 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30007.774877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30093.771131 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 30050.195339 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 71174656 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 115654 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3519123 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 1158 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20.225112 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 99.873921 # average number of cycles each access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.035048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.034313 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034682 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036819 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.035907 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.036365 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17350.733956 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17934.295756 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 17639.253300 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44221.561846 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45618.629130 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44905.965566 # average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 39635.690899 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45212.726530 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 42628.944495 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13808.908852 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13832.873588 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13820.645601 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27700 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 48000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 33500 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 30905.484670 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 31774.113657 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 31332.970406 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 29347.653296 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 30296.674587 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 29813.729016 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 70477710 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 116225 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3519959 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 20.022310 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 103.036348 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8028297 # number of writebacks -system.cpu0.dcache.writebacks::total 8028297 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3497981 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3358538 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 6856519 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5336387 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5255605 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10591992 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3609 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3341 # number of WriteLineReq MSHR hits -system.cpu0.dcache.WriteLineReq_mshr_hits::total 6950 # number of WriteLineReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 208459 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 191873 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 400332 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 8834368 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 8614143 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 17448511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 8834368 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 8614143 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 17448511 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2859239 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2789925 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5649164 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1084953 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1065175 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2150128 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 653985 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 613153 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1267138 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 579023 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 651755 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::total 1230778 # number of WriteLineReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 130201 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 120456 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 250657 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 3944192 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 3855100 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 7799292 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4598177 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 4468253 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 9066430 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16605 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17073 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15032 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18664 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31637 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35737 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49619026500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49901360000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 99520386500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 51614124513 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 50207961574 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101822086087 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14084347500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11245248000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25329595500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 22590719708 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 29035857698 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51626577406 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1881542500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1747721000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3629263500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 77000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 189500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 266500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101233151013 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100109321574 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 201342472587 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115317498513 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111354569574 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 226672068087 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3087653000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3143213500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6230866500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2916803000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3290991498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6207794498 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6004456000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6434204998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12438660998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033106 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032843 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032976 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014576 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014729 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014651 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.745059 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.750266 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.747569 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759594 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.813594 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787264 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062236 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058391 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060327 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.writebacks::writebacks 8078087 # number of writebacks +system.cpu0.dcache.writebacks::total 8078087 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3526105 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3409163 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6935268 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5405186 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5181209 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10586395 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 3376 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::cpu1.data 3483 # number of WriteLineReq MSHR hits +system.cpu0.dcache.WriteLineReq_mshr_hits::total 6859 # number of WriteLineReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 204163 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 196814 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 400977 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8931291 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8590372 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 17521663 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8931291 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8590372 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17521663 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2857115 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2832930 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5690045 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1092445 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1058766 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2151211 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 668680 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 599708 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1268388 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 570295 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 661102 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1231397 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 127451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 121478 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 248929 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3949560 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3891696 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7841256 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4618240 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4491404 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9109644 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16758 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16944 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33702 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15500 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18208 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32258 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35152 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67410 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48892925500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 49984550000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 98877475500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 50989234756 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 50617210449 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 101606445205 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13305949000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 11256900000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 24562849000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 21948256934 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 29156940361 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 51105197295 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1850360000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1748512000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3598872000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 133500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 94000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99882160256 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 100601760449 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 200483920705 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 113188109256 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 111858660449 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 225046769705 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3097490500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3134623000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232113500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2979818500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3228691491 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6208509991 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6077309000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6363314491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12440623491 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.009749 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.009728 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009738 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014676 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014592 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014635 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750530 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.745614 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.748198 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758833 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.814954 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.787965 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061506 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058429 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024528 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024513 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024521 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028440 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028265 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028354 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17353.927566 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17886.272928 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17616.834367 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47572.682423 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47135.880559 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47356.290457 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21536.193491 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18340.035847 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19989.610840 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 39015.237232 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44550.264590 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41946.295275 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14451.060284 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14509.206681 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14479.003180 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 12833.333333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 47375 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26650 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25666.385159 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25968.021990 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25815.480762 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25078.960317 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24921.276744 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25001.248351 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185947.184583 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184104.346043 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185012.960983 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 194039.582225 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176328.305722 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184229.418863 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189792.205329 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 180043.232448 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184621.085255 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.010747 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.010698 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.010722 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.012536 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.012319 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.012428 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 17112.690774 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17644.117574 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17377.274784 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46674.418168 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 47807.740756 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47232.207908 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19898.829036 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18770.635042 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19365.406327 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38485.795832 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44103.542813 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 41501.804288 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14518.206997 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14393.651525 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14457.423603 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26700 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 47000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 32500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25289.439901 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25850.364584 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25567.832590 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24508.927482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24905.054288 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24704.233196 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184836.525838 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 184998.996695 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.209602 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 192246.354839 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 177322.687335 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184185.059659 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 188396.955794 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 181022.829170 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184551.602003 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16001570 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932596 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 169345332 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16002082 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.582706 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19421691500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.339337 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.593260 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541678 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.458190 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16336648 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.932732 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 580722956 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16337160 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 35.546139 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19421278500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 279.802291 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 232.130441 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.546489 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.453380 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 202579626 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 202579626 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 85484031 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 83861301 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 169345332 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 85484031 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 83861301 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 169345332 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 85484031 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 83861301 # number of overall hits -system.cpu0.icache.overall_hits::total 169345332 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8738579 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8493502 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17232081 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8738579 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8493502 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17232081 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8738579 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8493502 # number of overall misses -system.cpu0.icache.overall_misses::total 17232081 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 117560688351 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 115310089841 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 232870778192 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 117560688351 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 115310089841 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 232870778192 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 117560688351 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 115310089841 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 232870778192 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 94222610 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 92354803 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 186577413 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 94222610 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 92354803 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 186577413 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 94222610 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 92354803 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 186577413 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.092744 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091966 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.092359 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.092744 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091966 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.092359 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.092744 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091966 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.092359 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13453.066952 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.271583 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13513.793151 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13453.066952 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.271583 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13513.793151 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13453.066952 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.271583 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13513.793151 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 123875 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 614644224 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 614644224 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 291297674 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 289425282 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 580722956 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 291297674 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 289425282 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 580722956 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 291297674 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 289425282 # number of overall hits +system.cpu0.icache.overall_hits::total 580722956 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8834570 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8749295 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17583865 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8834570 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8749295 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17583865 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8834570 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8749295 # number of overall misses +system.cpu0.icache.overall_misses::total 17583865 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 118633487353 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 118783272350 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 237416759703 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 118633487353 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 118783272350 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 237416759703 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 118633487353 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 118783272350 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 237416759703 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 300132244 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 298174577 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 598306821 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 300132244 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 298174577 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 598306821 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 300132244 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 298174577 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 598306821 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029436 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.029343 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029389 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029436 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.029343 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029389 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029436 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.029343 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029389 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13428.326150 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13576.324990 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13501.966701 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13428.326150 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13576.324990 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13501.966701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13428.326150 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13576.324990 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13501.966701 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 128000 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 8516 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 8615 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.546148 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.857806 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 16001570 # number of writebacks -system.cpu0.icache.writebacks::total 16001570 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 623725 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 606143 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1229868 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 623725 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 606143 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1229868 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 623725 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 606143 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1229868 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8114854 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7887359 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16002213 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8114854 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 7887359 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16002213 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8114854 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 7887359 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16002213 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 16336648 # number of writebacks +system.cpu0.icache.writebacks::total 16336648 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 624990 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 621471 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1246461 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 624990 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 621471 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1246461 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 624990 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 621471 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1246461 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8209580 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8127824 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16337404 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8209580 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8127824 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16337404 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8209580 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8127824 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16337404 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103804344898 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 101735391889 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 205539736787 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103804344898 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 101735391889 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 205539736787 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103804344898 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 101735391889 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 205539736787 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104820770896 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 104795182400 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 209615953296 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104820770896 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 104795182400 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 209615953296 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104820770896 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 104795182400 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 209615953296 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960890000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636383000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675493000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960890000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636383000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086124 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085403 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085767 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086124 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085403 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085767 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086124 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085403 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085767 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12791.893101 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12898.536999 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12844.457000 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12791.893101 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12898.536999 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12844.457000 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12791.893101 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12898.536999 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12844.457000 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027353 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027259 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027306 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027353 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.027259 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027306 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027353 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.027259 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027306 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12768.103959 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12893.387258 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12830.432136 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12768.103959 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12893.387258 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12830.432136 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12768.103959 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12893.387258 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12830.432136 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127694.613969 # average ReadReq mshr uncacheable latency @@ -1343,15 +1353,19 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 127705.259146 system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127676.056338 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127694.613969 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 129319671 # Number of BP lookups -system.cpu1.branchPred.condPredicted 87966891 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5641555 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87944289 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 63362458 # Number of BTB hits +system.cpu1.branchPred.lookups 439037695 # Number of BP lookups +system.cpu1.branchPred.condPredicted 344630545 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5789779 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 303336917 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 265424368 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 72.048406 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16739508 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 187311 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 87.501505 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 16925953 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188094 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 4924647 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 2613751 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 2310896 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 404882 # Number of mispredicted indirect branches. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1381,89 +1395,87 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 895803 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 895803 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16863 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90438 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 556335 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 339468 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2716.724404 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 17179.301997 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-131071 338161 99.61% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-262143 1033 0.30% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-393215 187 0.06% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-524287 66 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::524288-655359 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::655360-786431 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::786432-917503 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 339468 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 421969 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 23447.781709 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18889.456511 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 20397.447622 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 412488 97.75% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6847 1.62% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1883 0.45% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 119 0.03% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 376 0.09% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 119 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 93 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 421969 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 329421639756 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.099906 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.712348 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 328385721256 99.69% 99.69% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 558806000 0.17% 99.86% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 205948500 0.06% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 123798000 0.04% 99.96% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 49482000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 27267000 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 29508000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 34215500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 6315000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 466000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 60500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::44-47 19000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::48-51 33000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 329421639756 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 90439 84.28% 84.28% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 16863 15.72% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 107302 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 895803 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 918796 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 918796 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17982 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92529 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 574433 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 344363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2764.463662 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 16303.117040 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 341501 99.17% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1458 0.42% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 968 0.28% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 172 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 169 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 30 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 39 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 344363 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 435626 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23794.009081 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19218.933550 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 19692.719928 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 425832 97.75% 97.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 7550 1.73% 99.48% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1569 0.36% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 124 0.03% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 287 0.07% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 141 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 90 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 14 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 435626 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 784789358776 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.079913 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.520502 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 783688095276 99.86% 99.86% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 587470000 0.07% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 214780500 0.03% 99.96% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 128162000 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 51938500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 36138500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 30357500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 44039000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 7811000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 500500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 27000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 22000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 784789358776 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 92530 83.73% 83.73% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17982 16.27% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 110512 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918796 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 895803 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 107302 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918796 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 110512 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 107302 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 1003105 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 110512 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1029308 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 102542814 # DTB read hits -system.cpu1.dtb.read_misses 610673 # DTB read misses -system.cpu1.dtb.write_hits 79662745 # DTB write hits -system.cpu1.dtb.write_misses 285130 # DTB write misses -system.cpu1.dtb.flush_tlb 1093 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 308677787 # DTB read hits +system.cpu1.dtb.read_misses 638033 # DTB read misses +system.cpu1.dtb.write_hits 79810213 # DTB write hits +system.cpu1.dtb.write_misses 280763 # DTB write misses +system.cpu1.dtb.flush_tlb 1558 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21297 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 54160 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 170 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9133 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 20842 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 54702 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 8626 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55274 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 103153487 # DTB read accesses -system.cpu1.dtb.write_accesses 79947875 # DTB write accesses +system.cpu1.dtb.perms_faults 52744 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 309315820 # DTB read accesses +system.cpu1.dtb.write_accesses 80090976 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 182205559 # DTB hits -system.cpu1.dtb.misses 895803 # DTB misses -system.cpu1.dtb.accesses 183101362 # DTB accesses +system.cpu1.dtb.hits 388488000 # DTB hits +system.cpu1.dtb.misses 918796 # DTB misses +system.cpu1.dtb.accesses 389406796 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1493,383 +1505,382 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 104787 # Table walker walks requested -system.cpu1.itb.walker.walksLong 104787 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2997 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70975 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 14401 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 90386 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1987.890824 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 12865.387454 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-65535 89845 99.40% 99.40% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-131071 221 0.24% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-196607 266 0.29% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-327679 17 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-393215 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 90386 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 88373 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 30169.316420 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25114.673173 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 23994.465704 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 86083 97.41% 97.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 728 0.82% 98.23% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 1319 1.49% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 85 0.10% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 120 0.14% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 16 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 88373 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 612887048792 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.894295 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.308036 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 64872157396 10.58% 10.58% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 547942164396 89.40% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 62720500 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 7937000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 1056500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 430500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 357000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::8 210500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 612887048792 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 70975 95.95% 95.95% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2997 4.05% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 73972 # Table walker page sizes translated +system.cpu1.itb.walker.walks 101960 # Table walker walks requested +system.cpu1.itb.walker.walksLong 101960 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 3266 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68775 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14205 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 87755 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1682.627770 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 11960.911223 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-65535 87281 99.46% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-131071 225 0.26% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-196607 206 0.23% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-262143 30 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 87755 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 86246 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29588.885282 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 24514.620158 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 24839.457997 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 84146 97.57% 97.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 550 0.64% 98.20% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 1295 1.50% 99.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 109 0.13% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 30 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 19 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 86246 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 630168052620 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.901316 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.298682 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 62259907956 9.88% 9.88% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 567845557664 90.11% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 54142000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 7434500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 754500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 241500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 630168052620 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 68775 95.47% 95.47% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 3266 4.53% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72041 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104787 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104787 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101960 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101960 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73972 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73972 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 178759 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 92590548 # ITB inst hits -system.cpu1.itb.inst_misses 104787 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 174001 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 298391001 # ITB inst hits +system.cpu1.itb.inst_misses 101960 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1093 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1558 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21297 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40602 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20842 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40396 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205634 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 187550 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 92695335 # ITB inst accesses -system.cpu1.itb.hits 92590548 # DTB hits -system.cpu1.itb.misses 104787 # DTB misses -system.cpu1.itb.accesses 92695335 # DTB accesses -system.cpu1.numCycles 681850895 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 298492961 # ITB inst accesses +system.cpu1.itb.hits 298391001 # DTB hits +system.cpu1.itb.misses 101960 # DTB misses +system.cpu1.itb.accesses 298492961 # DTB accesses +system.cpu1.numCycles 1146540967 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 239388954 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 575024708 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 129319671 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 80101966 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 399222814 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 12867675 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2725843 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 25092 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 3697 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5482930 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 182777 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 3937 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 92362358 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3459969 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 41770 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 653469609 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.029599 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.281240 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 449143632 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 1300356824 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 439037695 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 284964072 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 654346336 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13178215 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2532163 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 23392 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 4389 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 4759392 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 175720 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 3551 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 298182140 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3594914 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 39494 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 1117577293 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.251423 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.109409 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 511473047 78.27% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 17746068 2.72% 80.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 17876069 2.74% 83.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13147863 2.01% 85.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28062649 4.29% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8778442 1.34% 91.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9526239 1.46% 92.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8304050 1.27% 94.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 38555182 5.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 718189985 64.26% 64.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 120476918 10.78% 75.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 17851977 1.60% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13155756 1.18% 77.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 181640077 16.25% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 8775776 0.79% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9591150 0.86% 95.71% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8236988 0.74% 96.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 39658666 3.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 653469609 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.189660 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.843329 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 194540645 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 337340525 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 103135857 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 13376974 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5073310 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19204285 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1379859 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 627304700 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4258915 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5073310 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 201998899 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 27311844 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 261169019 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 108909949 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 49003878 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 612618911 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 137031 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1952354 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1962506 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 29516744 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 3823 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 587164162 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 946758307 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 724795926 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 781641 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 494885886 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 92278271 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15082252 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13144529 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 75005032 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 98707880 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 83757072 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13358555 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14229040 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 581184996 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15164742 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 582092616 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 825653 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 77569161 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 49788978 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 351791 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 653469609 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.890772 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.626680 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 1117577293 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.382924 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.134156 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 403258788 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 335088582 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 360694363 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13294705 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5232856 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 70476298 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1375606 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 1352424044 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4253100 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5232856 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 410740551 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 28469825 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 258278982 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 366370165 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 48476952 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 1337170119 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 127982 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1950398 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1918017 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 29294510 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3829 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 1310108256 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 1925124078 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 1396779335 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 887250 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 1214507358 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 95600893 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14870121 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12952577 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 74043380 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 305276022 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 83874418 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13450040 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14282158 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 1304947133 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14993052 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 1304763464 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 862160 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 81029622 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 50869342 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 350473 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 1117577293 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.167493 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.494205 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 424481416 64.96% 64.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 97055692 14.85% 79.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 42445288 6.50% 86.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 30251514 4.63% 90.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 22439866 3.43% 94.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15693652 2.40% 96.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10715111 1.64% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6223144 0.95% 99.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4163926 0.64% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 477542007 42.73% 42.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 353173077 31.60% 74.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 93863937 8.40% 82.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 81886889 7.33% 90.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 73787788 6.60% 96.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 15804378 1.41% 98.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 10888709 0.97% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6347514 0.57% 99.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4282994 0.38% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 653469609 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 1117577293 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2929813 25.60% 25.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 22943 0.20% 25.80% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2467 0.02% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.82% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4683520 40.92% 66.74% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3806309 33.26% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2956708 25.80% 25.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 26444 0.23% 26.03% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 3429 0.03% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.06% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4659115 40.65% 66.71% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3815684 33.29% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 87 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 395178561 67.89% 67.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1472120 0.25% 68.14% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66548 0.01% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 83 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 18 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 58655 0.01% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 104607338 17.97% 86.13% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 80709157 13.87% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 86 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 911406413 69.85% 69.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1450716 0.11% 69.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 68809 0.01% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 242 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 16 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 74568 0.01% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.97% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 310913309 23.83% 93.80% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 80849259 6.20% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 582092616 # Type of FU issued -system.cpu1.iq.rate 0.853695 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11445052 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019662 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1828886082 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 674065927 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 561183745 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1039464 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 516201 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 461714 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 592981793 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 555788 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4619757 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 1304763464 # Type of FU issued +system.cpu1.iq.rate 1.138000 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11461380 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.008784 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 3738310574 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 1401077508 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 1283063938 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1117187 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 574367 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 497584 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 1315629411 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 595347 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4624780 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 15740565 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 19881 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 674311 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 8622171 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16729306 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 20042 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 692952 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 8476645 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3783711 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 7638228 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 3812143 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7452647 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5073310 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 16098431 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 8955476 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 596484662 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1704911 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 98707880 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 83757072 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 12853261 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 236300 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 8632331 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 674311 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2559005 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2239379 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4798384 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 575610941 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 102532690 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5599160 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5232856 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 16688704 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 9539057 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 1320087759 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1712091 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 305276022 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 83874418 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12664409 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 233480 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9218245 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 692952 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2475150 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2684103 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5159253 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 1297880089 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 308665532 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 5977092 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 134924 # number of nop insts executed -system.cpu1.iew.exec_refs 182199156 # number of memory reference insts executed -system.cpu1.iew.exec_branches 106955524 # Number of branches executed -system.cpu1.iew.exec_stores 79666466 # Number of stores executed -system.cpu1.iew.exec_rate 0.844189 # Inst execution rate -system.cpu1.iew.wb_sent 562846195 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 561645459 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 277406088 # num instructions producing a value -system.cpu1.iew.wb_consumers 482095859 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.823707 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575417 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 77620005 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 14812951 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4280755 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 640233275 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.810299 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.807739 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 147574 # number of nop insts executed +system.cpu1.iew.exec_refs 388478968 # number of memory reference insts executed +system.cpu1.iew.exec_branches 415337436 # Number of branches executed +system.cpu1.iew.exec_stores 79813436 # Number of stores executed +system.cpu1.iew.exec_rate 1.131996 # Inst execution rate +system.cpu1.iew.wb_sent 1284971111 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 1283561522 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 586897530 # num instructions producing a value +system.cpu1.iew.wb_consumers 1100487939 # num instructions consuming a value +system.cpu1.iew.wb_rate 1.119508 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.533307 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 81091096 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14642579 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4433138 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 1103802352 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.122403 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.555476 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 449273024 70.17% 70.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 94745433 14.80% 84.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 32328499 5.05% 90.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 14864939 2.32% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10716802 1.67% 94.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6304065 0.98% 95.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5887950 0.92% 95.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3832413 0.60% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22280150 3.48% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 502258397 45.50% 45.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 299485709 27.13% 72.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 134986499 12.23% 84.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 117786431 10.67% 95.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10837119 0.98% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6401807 0.58% 97.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5917729 0.54% 97.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3800615 0.34% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22328046 2.02% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 640233275 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 441802027 # Number of instructions committed -system.cpu1.commit.committedOps 518780572 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 1103802352 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 1161548854 # Number of instructions committed +system.cpu1.commit.committedOps 1238910558 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 158102215 # Number of memory references committed -system.cpu1.commit.loads 82967314 # Number of loads committed -system.cpu1.commit.membars 3638779 # Number of memory barriers committed -system.cpu1.commit.branches 98771468 # Number of branches committed -system.cpu1.commit.fp_insts 442327 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 475908422 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12958317 # Number of function calls committed. +system.cpu1.commit.refs 363944488 # Number of memory references committed +system.cpu1.commit.loads 288546715 # Number of loads committed +system.cpu1.commit.membars 3671917 # Number of memory barriers committed +system.cpu1.commit.branches 406943707 # Number of branches committed +system.cpu1.commit.fp_insts 477645 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 1042234207 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13083843 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 359445517 69.29% 69.29% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1133059 0.22% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49873 0.01% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 49866 0.01% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 82967314 15.99% 85.52% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 75134901 14.48% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 873720787 70.52% 70.52% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1128470 0.09% 70.61% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 51728 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 65043 0.01% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.62% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 288546715 23.29% 93.91% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 75397773 6.09% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 518780572 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22280150 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 1210397617 # The number of ROB reads -system.cpu1.rob.rob_writes 1206057669 # The number of ROB writes -system.cpu1.timesIdled 4036845 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 28381286 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 48640587426 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 441802027 # Number of Instructions Simulated -system.cpu1.committedOps 518780572 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.543340 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.543340 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.647945 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.647945 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 679308932 # number of integer regfile reads -system.cpu1.int_regfile_writes 400707036 # number of integer regfile writes -system.cpu1.fp_regfile_reads 840716 # number of floating regfile reads -system.cpu1.fp_regfile_writes 480942 # number of floating regfile writes -system.cpu1.cc_regfile_reads 124429179 # number of cc regfile reads -system.cpu1.cc_regfile_writes 125518608 # number of cc regfile writes -system.cpu1.misc_regfile_reads 1192080281 # number of misc regfile reads -system.cpu1.misc_regfile_writes 14931224 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40297 # Transaction distribution -system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.cpu1.commit.op_class_0::total 1238910558 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22328046 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 2397538789 # The number of ROB reads +system.cpu1.rob.rob_writes 2653800851 # The number of ROB writes +system.cpu1.timesIdled 4140984 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 28963674 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 48004396286 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 1161548854 # Number of Instructions Simulated +system.cpu1.committedOps 1238910558 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.987079 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.987079 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.013090 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.013090 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 1349751752 # number of integer regfile reads +system.cpu1.int_regfile_writes 814694732 # number of integer regfile writes +system.cpu1.fp_regfile_reads 925132 # number of floating regfile reads +system.cpu1.fp_regfile_writes 580436 # number of floating regfile writes +system.cpu1.cc_regfile_reads 432060294 # number of cc regfile reads +system.cpu1.cc_regfile_writes 433189790 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2477616684 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14758914 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40289 # Transaction distribution +system.iobus.trans_dist::ReadResp 40289 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1886,11 +1897,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1905,100 +1916,100 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 47817000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 47809000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 346500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 351500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25488000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25705000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 40144000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 567038102 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 566925706 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147712000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147696000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115457 # number of replacements -system.iocache.tags.tagsinuse 10.419652 # Cycle average of tags in use +system.iocache.tags.replacements 115449 # number of replacements +system.iocache.tags.tagsinuse 10.471056 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13096643979000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.546599 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.873052 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221662 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429566 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651228 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13096638509000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.513940 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.957116 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219621 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434820 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.654441 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039641 # Number of tag accesses -system.iocache.tags.data_accesses 1039641 # Number of data accesses +system.iocache.tags.tag_accesses 1039569 # Number of tag accesses +system.iocache.tags.data_accesses 1039569 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8804 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8841 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses -system.iocache.demand_misses::total 8852 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8804 # number of demand (read+write) misses +system.iocache.demand_misses::total 8844 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8812 # number of overall misses -system.iocache.overall_misses::total 8852 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1695101545 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1700187545 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 8804 # number of overall misses +system.iocache.overall_misses::total 8844 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5070000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1671055077 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1676125077 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13413700557 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13413700557 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1695101545 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1700538545 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1695101545 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1700538545 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 13413972629 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 13413972629 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5421000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1671055077 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1676476077 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5421000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1671055077 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1676476077 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8804 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8841 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8804 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8844 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8804 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8844 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2012,55 +2023,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 192362.862574 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 192133.296983 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137027.027027 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 189806.346774 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 189585.462844 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125756.586637 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125756.586637 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 192362.862574 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 192107.833823 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 192362.862574 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 192107.833823 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34986 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125759.137375 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125759.137375 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 189806.346774 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 189560.840909 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135525 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 189806.346774 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 189560.840909 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 34335 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3424 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 10.146752 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 10.027745 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8804 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8841 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8804 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8844 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1254501545 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1257737545 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8804 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8844 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1230855077 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1234075077 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8075439072 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8075439072 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1254501545 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1257938545 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1254501545 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1257938545 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8075705812 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 8075705812 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3421000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1230855077 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1234276077 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3421000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1230855077 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1234276077 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2074,309 +2085,311 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142362.862574 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 142133.296983 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87027.027027 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 139806.346774 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 139585.462844 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75709.134028 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75709.134028 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 142362.862574 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 142107.833823 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 142362.862574 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 142107.833823 # average overall mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75711.634778 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75711.634778 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 139806.346774 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 139560.840909 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85525 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 139806.346774 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 139560.840909 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1354167 # number of replacements -system.l2c.tags.tagsinuse 65271.664072 # Cycle average of tags in use -system.l2c.tags.total_refs 49616884 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1417173 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 35.011169 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 4319323500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35375.234634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 164.760345 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 244.127977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3171.033439 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 12870.716892 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 164.761556 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 248.464431 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4106.850597 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 8925.714203 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.539783 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002514 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003725 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048386 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.196392 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002514 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.062666 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.136196 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995967 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 327 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62679 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 323 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 526 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2739 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5047 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54263 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004990 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.956406 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 440318185 # Number of tag accesses -system.l2c.tags.data_accesses 440318185 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 529920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 190466 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 530762 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 192283 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1443431 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 8028297 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 8028297 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 15998256 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 15998256 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 5110 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4875 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9985 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 8 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 801378 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 790864 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1592242 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 8070693 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 7837834 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 15908527 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3479192 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 3366612 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 6845804 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 362766 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 356171 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 718937 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 529920 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 190466 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8070693 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4280570 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 530762 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 192283 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7837834 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4157476 # number of demand (read+write) hits -system.l2c.demand_hits::total 25790004 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 529920 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 190466 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8070693 # number of overall hits -system.l2c.overall_hits::cpu0.data 4280570 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 530762 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 192283 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7837834 # number of overall hits -system.l2c.overall_hits::cpu1.data 4157476 # number of overall hits -system.l2c.overall_hits::total 25790004 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2274 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2066 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2491 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2269 # number of ReadReq misses -system.l2c.ReadReq_misses::total 9100 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18272 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17946 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36218 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses +system.l2c.tags.replacements 1328339 # number of replacements +system.l2c.tags.tagsinuse 65287.407442 # Cycle average of tags in use +system.l2c.tags.total_refs 50375413 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1391222 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 36.209471 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 4319218500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35575.639274 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 158.468154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 240.943849 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3221.018830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 11891.666425 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 181.118375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 261.193191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3949.386858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9807.972486 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.542841 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002418 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003677 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.049149 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.181452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002764 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003985 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.060263 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.149658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996207 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 365 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62518 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 365 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 534 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2786 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5034 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54062 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005569 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.953949 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 446176670 # Number of tag accesses +system.l2c.tags.data_accesses 446176670 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 522071 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 180522 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 538718 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 182834 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1424145 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 8078087 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 8078087 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 16333029 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 16333029 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 5039 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4982 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10021 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 814588 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 782344 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1596932 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 8166281 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 8076794 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 16243075 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3501095 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3399507 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6900602 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 361869 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 365570 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 727439 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 522071 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 180522 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 8166281 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4315683 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 538718 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 182834 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 8076794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4181851 # number of demand (read+write) hits +system.l2c.demand_hits::total 26164754 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 522071 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 180522 # number of overall hits +system.l2c.overall_hits::cpu0.inst 8166281 # number of overall hits +system.l2c.overall_hits::cpu0.data 4315683 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 538718 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 182834 # number of overall hits +system.l2c.overall_hits::cpu1.inst 8076794 # number of overall hits +system.l2c.overall_hits::cpu1.data 4181851 # number of overall hits +system.l2c.overall_hits::total 26164754 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2382 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2080 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2398 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2211 # number of ReadReq misses +system.l2c.ReadReq_misses::total 9071 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 18406 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 17899 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36305 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 266335 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 257652 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 523987 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 44093 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 49428 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 93521 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 158093 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 150761 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 308854 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 216257 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 295584 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 511841 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2274 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2066 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 44093 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 424428 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2491 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2269 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 49428 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 408413 # number of demand (read+write) misses -system.l2c.demand_misses::total 935462 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2274 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2066 # number of overall misses -system.l2c.overall_misses::cpu0.inst 44093 # number of overall misses -system.l2c.overall_misses::cpu0.data 424428 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2491 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2269 # number of overall misses -system.l2c.overall_misses::cpu1.inst 49428 # number of overall misses -system.l2c.overall_misses::cpu1.data 408413 # number of overall misses -system.l2c.overall_misses::total 935462 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 314659500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 284252000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 344205000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 314739500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1257856000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 725402000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 698413500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1423815500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 160500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_misses::cpu0.data 260481 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 259931 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 520412 # number of ReadExReq misses +system.l2c.ReadCleanReq_misses::cpu0.inst 43082 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 50777 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 93859 # number of ReadCleanReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 146082 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 148220 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 294302 # number of ReadSharedReq misses +system.l2c.InvalidateReq_misses::cpu0.data 208426 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::cpu1.data 295532 # number of InvalidateReq misses +system.l2c.InvalidateReq_misses::total 503958 # number of InvalidateReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2382 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2080 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 43082 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 406563 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2398 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2211 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 50777 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 408151 # number of demand (read+write) misses +system.l2c.demand_misses::total 917644 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2382 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2080 # number of overall misses +system.l2c.overall_misses::cpu0.inst 43082 # number of overall misses +system.l2c.overall_misses::cpu0.data 406563 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2398 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2211 # number of overall misses +system.l2c.overall_misses::cpu1.inst 50777 # number of overall misses +system.l2c.overall_misses::cpu1.data 408151 # number of overall misses +system.l2c.overall_misses::total 917644 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 328467000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 287802500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 333096500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 309339500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1258705500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 720994000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 707940000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 1428934000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 81000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 40057274000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 38799660500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 78856934500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 5970085500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6712322000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 12682407500 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 22392015000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 21109966000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 43501981000 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 6555000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 7491000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 14046000 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 314659500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 284252000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5970085500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 62449289000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 344205000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 314739500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 6712322000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 59909626500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 136299179000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 314659500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 284252000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5970085500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 62449289000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 344205000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 314739500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 6712322000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 59909626500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 136299179000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 532194 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 192532 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 533253 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 194552 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1452531 # number of ReadReq accesses(hits+misses) -system.l2c.WritebackDirty_accesses::writebacks 8028297 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 8028297 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackClean_accesses::writebacks 15998256 # number of WritebackClean accesses(hits+misses) -system.l2c.WritebackClean_accesses::total 15998256 # number of WritebackClean accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 23382 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 22821 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46203 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 10 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1067713 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1048516 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2116229 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu0.inst 8114786 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::cpu1.inst 7887262 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadCleanReq_accesses::total 16002048 # number of ReadCleanReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0.data 3637285 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1.data 3517373 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 7154658 # number of ReadSharedReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu0.data 579023 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::cpu1.data 651755 # number of InvalidateReq accesses(hits+misses) -system.l2c.InvalidateReq_accesses::total 1230778 # number of InvalidateReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 532194 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 192532 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 8114786 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4704998 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 533253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 194552 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7887262 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4565889 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 26725466 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 532194 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 192532 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 8114786 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4704998 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 533253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 194552 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7887262 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 4565889 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 26725466 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.010731 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.006265 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.781456 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.786381 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.783888 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_latency::cpu0.data 39260568000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 39326078500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 78586646500 # number of ReadExReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu0.inst 5834073500 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6880458998 # number of ReadCleanReq miss cycles +system.l2c.ReadCleanReq_miss_latency::total 12714532498 # number of ReadCleanReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 20593358000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 20805919500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 41399277500 # number of ReadSharedReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu0.data 4602500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::cpu1.data 4134500 # number of InvalidateReq miss cycles +system.l2c.InvalidateReq_miss_latency::total 8737000 # number of InvalidateReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 328467000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 287802500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5834073500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 59853926000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 333096500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 309339500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6880458998 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 60131998000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 133959161998 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 328467000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 287802500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5834073500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 59853926000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 333096500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 309339500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6880458998 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 60131998000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 133959161998 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 524453 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 182602 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 541116 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 185045 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1433216 # number of ReadReq accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 8078087 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 8078087 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 16333029 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 16333029 # number of WritebackClean accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 23445 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 22881 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 46326 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1075069 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1042275 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2117344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu0.inst 8209363 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::cpu1.inst 8127571 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadCleanReq_accesses::total 16336934 # number of ReadCleanReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 3647177 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 3547727 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 7194904 # number of ReadSharedReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu0.data 570295 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::cpu1.data 661102 # number of InvalidateReq accesses(hits+misses) +system.l2c.InvalidateReq_accesses::total 1231397 # number of InvalidateReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 524453 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 182602 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 8209363 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4722246 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 541116 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 185045 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8127571 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 4590002 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 27082398 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 524453 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 182602 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 8209363 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4722246 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 541116 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 185045 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8127571 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 4590002 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 27082398 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004542 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011391 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004432 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011948 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.006329 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785071 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782265 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.783685 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.200000 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.500000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.249444 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.245730 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.247604 # miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005434 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.006267 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.005844 # miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.043465 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.042862 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.043168 # miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_miss_rate::cpu0.data 0.373486 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::cpu1.data 0.453520 # miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_miss_rate::total 0.415868 # miss rate for InvalidateReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004273 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.010731 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.005434 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.090208 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.011663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006267 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.089449 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.035003 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004273 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.010731 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.005434 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.090208 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.011663 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006267 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.089449 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.035003 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 138372.691293 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 137585.672798 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138179.446006 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 138712.869105 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 138225.934066 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39700.197023 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 38917.502508 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 39312.372301 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 80250 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.242292 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.249388 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.245785 # miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.005248 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.006248 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.005745 # miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.040053 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.041779 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.040904 # miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_miss_rate::cpu0.data 0.365471 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::cpu1.data 0.447029 # miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_miss_rate::total 0.409257 # miss rate for InvalidateReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004542 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.011391 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.005248 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.086095 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004432 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.011948 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.006248 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.088922 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.033883 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004542 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.011391 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.005248 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.086095 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004432 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.011948 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.006248 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.088922 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.033883 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 137895.465995 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 138366.586538 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 138905.963303 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 139909.317051 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 138761.492669 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 39171.683147 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 39551.930275 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 39359.151632 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 81000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150401.839788 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 150589.401596 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 150494.066647 # average ReadExReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135397.580115 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135799.991907 # average ReadCleanReq miss latency -system.l2c.ReadCleanReq_avg_miss_latency::total 135610.264005 # average ReadCleanReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 141638.244578 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140022.724710 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 140849.660357 # average ReadSharedReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 30.311158 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 25.343050 # average InvalidateReq miss latency -system.l2c.InvalidateReq_avg_miss_latency::total 27.442116 # average InvalidateReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 138372.691293 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 137585.672798 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 135397.580115 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 147137.533339 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138179.446006 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138712.869105 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 135799.991907 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 146688.833362 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 145702.528804 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 138372.691293 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 137585.672798 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 135397.580115 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 147137.533339 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138179.446006 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138712.869105 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 135799.991907 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 146688.833362 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 145702.528804 # average overall miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 150723.346424 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 151294.299256 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 151008.521133 # average ReadExReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 135417.889142 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 135503.456250 # average ReadCleanReq miss latency +system.l2c.ReadCleanReq_avg_miss_latency::total 135464.180292 # average ReadCleanReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 140971.221643 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 140371.876265 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 140669.371938 # average ReadSharedReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 22.082178 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 13.990025 # average InvalidateReq miss latency +system.l2c.InvalidateReq_avg_miss_latency::total 17.336762 # average InvalidateReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137895.465995 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 138366.586538 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 135417.889142 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 147219.314104 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 138905.963303 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 139909.317051 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 135503.456250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 147327.822301 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 145981.624680 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137895.465995 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 138366.586538 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 135417.889142 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 147219.314104 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 138905.963303 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 139909.317051 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 135503.456250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 147327.822301 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 145981.624680 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2385,290 +2398,294 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1140902 # number of writebacks -system.l2c.writebacks::total 1140902 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 27 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 34 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 1125321 # number of writebacks +system.l2c.writebacks::total 1125321 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 32 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0.data 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.dtb.walker 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.itb.walker 27 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.dtb.walker 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.itb.walker 34 # number of demand (read+write) MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu0.data 6 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.data 16 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.dtb.walker 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.itb.walker 22 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.itb.walker 32 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.dtb.walker 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.itb.walker 27 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.dtb.walker 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.itb.walker 34 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.dtb.walker 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.itb.walker 22 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.itb.walker 32 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 101 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2266 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2039 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2481 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2235 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 9021 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::cpu1.data 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 90 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2373 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2058 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2394 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2179 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 9004 # number of ReadReq MSHR misses system.l2c.CleanEvict_mshr_misses::writebacks 2 # number of CleanEvict MSHR misses system.l2c.CleanEvict_mshr_misses::total 2 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 18272 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 17946 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 36218 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 18406 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 17899 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 36305 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 266335 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 257652 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 523987 # number of ReadExReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 44093 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 49427 # number of ReadCleanReq MSHR misses -system.l2c.ReadCleanReq_mshr_misses::total 93520 # number of ReadCleanReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0.data 158089 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1.data 150744 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 308833 # number of ReadSharedReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu0.data 216257 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::cpu1.data 295584 # number of InvalidateReq MSHR misses -system.l2c.InvalidateReq_mshr_misses::total 511841 # number of InvalidateReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2266 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2039 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 44093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 424424 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2481 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2235 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 49427 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 408396 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 935361 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2266 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2039 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 44093 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 424424 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2481 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2235 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 49427 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 408396 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 935361 # number of overall MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 260481 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 259931 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 520412 # number of ReadExReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 43082 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 50776 # number of ReadCleanReq MSHR misses +system.l2c.ReadCleanReq_mshr_misses::total 93858 # number of ReadCleanReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 146076 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 148204 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 294280 # number of ReadSharedReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu0.data 208426 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::cpu1.data 295532 # number of InvalidateReq MSHR misses +system.l2c.InvalidateReq_mshr_misses::total 503958 # number of InvalidateReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2373 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2058 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 43082 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 406557 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2394 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2179 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 50776 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 408135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 917554 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2373 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2058 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 43082 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 406557 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2394 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2179 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 50776 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 408135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 917554 # number of overall MSHR misses system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16605 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16758 # number of ReadReq MSHR uncacheable system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17073 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 54324 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15032 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 18664 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 16944 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 54348 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15500 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 18208 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 33708 # number of WriteReq MSHR uncacheable system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31637 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32258 # number of overall MSHR uncacheable misses system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35737 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 88020 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 290796504 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 260515002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 318070508 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 288489001 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1157871015 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1242470500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1220178000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2462648500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35152 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 88056 # number of overall MSHR uncacheable misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 303466501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 264543501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 308615007 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 283810502 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1160435511 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1251234000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1216921000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2468155000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 71000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 69500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 37393350389 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 36222649202 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 73615999591 # number of ReadExReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 5529095637 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6217965628 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadCleanReq_mshr_miss_latency::total 11747061265 # number of ReadCleanReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 20810520351 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 19600298350 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 40410818701 # number of ReadSharedReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 15116458000 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 20642114500 # number of InvalidateReq MSHR miss cycles -system.l2c.InvalidateReq_mshr_miss_latency::total 35758572500 # number of InvalidateReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 290796504 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 260515002 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 5529095637 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 58203870740 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 318070508 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 288489001 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 6217965628 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 55822947552 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 126931750572 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 290796504 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 260515002 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 5529095637 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 58203870740 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 318070508 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 288489001 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 6217965628 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 55822947552 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 126931750572 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 36655262703 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 36726203379 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 73381466082 # number of ReadExReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 5403192134 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 6372607642 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadCleanReq_mshr_miss_latency::total 11775799776 # number of ReadCleanReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19131795349 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 19321739325 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 38453534674 # number of ReadSharedReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 14581285500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 20639326500 # number of InvalidateReq MSHR miss cycles +system.l2c.InvalidateReq_mshr_miss_latency::total 35220612000 # number of InvalidateReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 303466501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 264543501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 5403192134 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 55787058052 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 308615007 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 283810502 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 6372607642 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 56047942704 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 124771236043 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 303466501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 264543501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 5403192134 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 55787058052 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 308615007 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 283810502 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 6372607642 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 56047942704 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 124771236043 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1472133000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2880017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2887938500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 844117498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2929717500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8125985498 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2743870000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3074757500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5818627500 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2922748500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8126937498 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2801523500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3017706998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5819230498 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1472133000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5623887500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5689462000 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 844117498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6004475000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13944612998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004258 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004653 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011488 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006211 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5940455498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13946167996 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004525 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011270 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004424 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011776 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006282 # mshr miss rate for ReadReq accesses system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.781456 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.786381 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783888 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785071 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.782265 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783685 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.200000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.249444 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.245730 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.247604 # mshr miss rate for ReadExReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005434 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006267 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005844 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.043463 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.042857 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.043165 # mshr miss rate for ReadSharedReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.373486 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.453520 # mshr miss rate for InvalidateReq accesses -system.l2c.InvalidateReq_mshr_miss_rate::total 0.415868 # mshr miss rate for InvalidateReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004258 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005434 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.090207 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004653 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011488 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006267 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.089445 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034999 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004258 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005434 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.090207 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004653 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011488 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006267 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.089445 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034999 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 128352.845028 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67998.604422 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67991.641591 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67995.154343 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70250 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.242292 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249388 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.245785 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005248 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006247 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005745 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.040052 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.041774 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040901 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.365471 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.447029 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.409257 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004525 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011270 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005248 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.086094 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004424 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011776 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006247 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.088918 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033880 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004525 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011270 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005248 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.086094 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004424 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011776 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006247 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.088918 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033880 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 128879.999000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 67979.680539 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 67988.211632 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 67983.886517 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 71000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 69500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140399.686068 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 140587.494768 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 140492.034327 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125396.222462 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125800.991927 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125610.150396 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 131638.003599 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130023.737927 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130850.066868 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69900.433281 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69835.019825 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69862.657544 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125396.222462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137136.143903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125800.991927 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136688.281844 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 135703.488356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128330.319506 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 127766.062776 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125396.222462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137136.143903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128202.542523 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129077.852796 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125800.991927 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136688.281844 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 135703.488356 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 140721.444954 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 141292.125137 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 141006.483482 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125416.464742 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125504.325705 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125463.996420 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130971.517217 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130372.589977 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130669.888113 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69959.052613 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69837.873733 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69887.990666 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125416.464742 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 137218.294242 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125504.325705 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137326.969517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 135982.444677 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127883.059840 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128543.975219 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125416.464742 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 137218.294242 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128911.865915 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130248.050482 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125504.325705 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137326.969517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 135982.444677 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173442.788317 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172331.931018 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171599.455280 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149583.710662 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182535.258116 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164742.686455 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172680.065883 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172494.599858 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 149535.171451 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 180743.451613 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 165735.226164 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 172636.480895 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112205.259146 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177762.983216 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 176373.674747 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112160.177784 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168018.440272 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 158425.505544 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 168993.385810 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 158378.395521 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 54324 # Transaction distribution -system.membus.trans_dist::ReadResp 474547 # Transaction distribution -system.membus.trans_dist::WriteReq 33696 # Transaction distribution -system.membus.trans_dist::WriteResp 33696 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1247532 # Transaction distribution -system.membus.trans_dist::CleanEvict 221010 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37031 # Transaction distribution +system.membus.trans_dist::ReadReq 54348 # Transaction distribution +system.membus.trans_dist::ReadResp 460331 # Transaction distribution +system.membus.trans_dist::WriteReq 33708 # Transaction distribution +system.membus.trans_dist::WriteResp 33708 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1231951 # Transaction distribution +system.membus.trans_dist::CleanEvict 210742 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37070 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 523357 # Transaction distribution -system.membus.trans_dist::ReadExResp 523357 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 420223 # Transaction distribution -system.membus.trans_dist::InvalidateReq 618325 # Transaction distribution +system.membus.trans_dist::ReadExReq 519762 # Transaction distribution +system.membus.trans_dist::ReadExResp 519762 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 405983 # Transaction distribution +system.membus.trans_dist::InvalidateReq 610510 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3816979 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3946617 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237606 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237606 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4184223 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6930 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3747708 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3877418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237430 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4114848 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134138156 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 134309854 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7248832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7248832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 141558686 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2885 # Total snoops (count) -system.membus.snoop_fanout::samples 3155536 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13860 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 132000044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 132171886 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7238592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7238592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 139410478 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3037 # Total snoops (count) +system.membus.snoop_fanout::samples 3104114 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3155536 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3104114 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3155536 # Request fanout histogram -system.membus.reqLayer0.occupancy 113887000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3104114 # Request fanout histogram +system.membus.reqLayer0.occupancy 114095000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5512000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5418502 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8359087618 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8237516188 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 5141778971 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5046734585 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44612371 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44568865 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2685,11 +2702,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2722,61 +2739,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 53860854 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 27356918 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 4389 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2115 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2115 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 54620375 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 27739287 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 4920 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2097 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 2036938 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25194555 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9275862 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 16001570 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2694937 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46206 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46216 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2116229 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2116229 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 16002213 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 7163507 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1337442 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1230778 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48047123 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31732395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 915561 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2519584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 83214663 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2049552896 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1107385822 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3096672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8523576 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 3168558966 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 2116170 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 30205961 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.026968 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.161993 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2026549 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25559589 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33708 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33708 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9310073 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 16336648 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2676872 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46329 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46336 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2117344 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2117344 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 16337404 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 7203745 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1338061 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1231397 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 49052277 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31858634 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 875155 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2530262 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 84316328 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 2092430528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1113218798 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2941176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8524552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 3217115054 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 2099522 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 30547038 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.026857 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.161665 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 29391361 97.30% 97.30% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 814592 2.70% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 29726637 97.31% 97.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 820401 2.69% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 30205961 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 51608527894 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 30547038 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 52365395385 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1422395 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1392915 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 24050258287 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24553415616 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14601873318 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14664140678 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 528950493 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 507934109 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1457147305 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1467755168 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16352 # number of quiesce instructions executed |