diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3 | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt | 4414 |
1 files changed, 2192 insertions, 2222 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index 726dee18b..6fc6c48c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.358448 # Number of seconds simulated -sim_ticks 51358448410500 # Number of ticks simulated -final_tick 51358448410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.318118 # Number of seconds simulated +sim_ticks 51318118168000 # Number of ticks simulated +final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129809 # Simulator instruction rate (inst/s) -host_op_rate 152542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7366025588 # Simulator tick rate (ticks/s) -host_mem_usage 732256 # Number of bytes of host memory used -host_seconds 6972.34 # Real time elapsed on the host -sim_insts 905073903 # Number of instructions simulated -sim_ops 1063573170 # Number of ops (including micro ops) simulated +host_inst_rate 134411 # Simulator instruction rate (inst/s) +host_op_rate 157933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7593762336 # Simulator tick rate (ticks/s) +host_mem_usage 732664 # Number of bytes of host memory used +host_seconds 6757.93 # Real time elapsed on the host +sim_insts 908340493 # Number of instructions simulated +sim_ops 1067303522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 167040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 151040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3952000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28582936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 161216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 144320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3546944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27869040 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401920 # Number of bytes read from this memory -system.physmem.bytes_read::total 64976456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3952000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3546944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7498944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83152960 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 160000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3855296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28386264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 162496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 145216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3634496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27952240 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430656 # Number of bytes read from this memory +system.physmem.bytes_read::total 64872776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3855296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3634496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7489792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83283200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83173540 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 61750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 446616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 55421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 435459 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6280 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1015270 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1299265 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83303780 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2500 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 60239 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 443543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2269 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56789 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 436759 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6729 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1013650 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1301300 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1301838 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 76949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 556538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 69063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 542638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1265156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 76949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 69063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 146012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1619071 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1303873 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 75125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 553143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 544686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1264130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 75125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 145948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1622881 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1619471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1619071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 76949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 556939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 69063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 542638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2884628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1015270 # Number of read requests accepted -system.physmem.writeReqs 1929008 # Number of write requests accepted -system.physmem.readBursts 1015270 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1929008 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64941248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36032 # Total number of bytes read from write queue -system.physmem.bytesWritten 123000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64976456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 123312420 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 563 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7116 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 37405 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 61592 # Per bank write bursts -system.physmem.perBankRdBursts::1 63105 # Per bank write bursts -system.physmem.perBankRdBursts::2 59504 # Per bank write bursts -system.physmem.perBankRdBursts::3 58627 # Per bank write bursts -system.physmem.perBankRdBursts::4 63182 # Per bank write bursts -system.physmem.perBankRdBursts::5 72471 # Per bank write bursts -system.physmem.perBankRdBursts::6 63664 # Per bank write bursts -system.physmem.perBankRdBursts::7 61386 # Per bank write bursts -system.physmem.perBankRdBursts::8 55404 # Per bank write bursts -system.physmem.perBankRdBursts::9 84358 # Per bank write bursts -system.physmem.perBankRdBursts::10 61903 # Per bank write bursts -system.physmem.perBankRdBursts::11 68457 # Per bank write bursts -system.physmem.perBankRdBursts::12 58658 # Per bank write bursts -system.physmem.perBankRdBursts::13 64087 # Per bank write bursts -system.physmem.perBankRdBursts::14 58698 # Per bank write bursts -system.physmem.perBankRdBursts::15 59611 # Per bank write bursts -system.physmem.perBankWrBursts::0 118843 # Per bank write bursts -system.physmem.perBankWrBursts::1 118980 # Per bank write bursts -system.physmem.perBankWrBursts::2 119959 # Per bank write bursts -system.physmem.perBankWrBursts::3 120276 # Per bank write bursts -system.physmem.perBankWrBursts::4 119980 # Per bank write bursts -system.physmem.perBankWrBursts::5 124689 # Per bank write bursts -system.physmem.perBankWrBursts::6 121042 # Per bank write bursts -system.physmem.perBankWrBursts::7 120315 # Per bank write bursts -system.physmem.perBankWrBursts::8 116178 # Per bank write bursts -system.physmem.perBankWrBursts::9 121715 # Per bank write bursts -system.physmem.perBankWrBursts::10 120153 # Per bank write bursts -system.physmem.perBankWrBursts::11 124890 # Per bank write bursts -system.physmem.perBankWrBursts::12 118317 # Per bank write bursts -system.physmem.perBankWrBursts::13 123673 # Per bank write bursts -system.physmem.perBankWrBursts::14 117041 # Per bank write bursts -system.physmem.perBankWrBursts::15 115838 # Per bank write bursts +system.physmem.bw_write::total 1623282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1622881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 75125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 553544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 544686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2887412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1013650 # Number of read requests accepted +system.physmem.writeReqs 1930075 # Number of write requests accepted +system.physmem.readBursts 1013650 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1930075 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 64838144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35456 # Total number of bytes read from write queue +system.physmem.bytesWritten 120356480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 64872776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 123380708 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49498 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 37388 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 61871 # Per bank write bursts +system.physmem.perBankRdBursts::1 62981 # Per bank write bursts +system.physmem.perBankRdBursts::2 60043 # Per bank write bursts +system.physmem.perBankRdBursts::3 58309 # Per bank write bursts +system.physmem.perBankRdBursts::4 58023 # Per bank write bursts +system.physmem.perBankRdBursts::5 70636 # Per bank write bursts +system.physmem.perBankRdBursts::6 62371 # Per bank write bursts +system.physmem.perBankRdBursts::7 61877 # Per bank write bursts +system.physmem.perBankRdBursts::8 57508 # Per bank write bursts +system.physmem.perBankRdBursts::9 84884 # Per bank write bursts +system.physmem.perBankRdBursts::10 63101 # Per bank write bursts +system.physmem.perBankRdBursts::11 65471 # Per bank write bursts +system.physmem.perBankRdBursts::12 60660 # Per bank write bursts +system.physmem.perBankRdBursts::13 66399 # Per bank write bursts +system.physmem.perBankRdBursts::14 58532 # Per bank write bursts +system.physmem.perBankRdBursts::15 60430 # Per bank write bursts +system.physmem.perBankWrBursts::0 115217 # Per bank write bursts +system.physmem.perBankWrBursts::1 115969 # Per bank write bursts +system.physmem.perBankWrBursts::2 118272 # Per bank write bursts +system.physmem.perBankWrBursts::3 117255 # Per bank write bursts +system.physmem.perBankWrBursts::4 115771 # Per bank write bursts +system.physmem.perBankWrBursts::5 124355 # Per bank write bursts +system.physmem.perBankWrBursts::6 120059 # Per bank write bursts +system.physmem.perBankWrBursts::7 119259 # Per bank write bursts +system.physmem.perBankWrBursts::8 113485 # Per bank write bursts +system.physmem.perBankWrBursts::9 118397 # Per bank write bursts +system.physmem.perBankWrBursts::10 117107 # Per bank write bursts +system.physmem.perBankWrBursts::11 118510 # Per bank write bursts +system.physmem.perBankWrBursts::12 116303 # Per bank write bursts +system.physmem.perBankWrBursts::13 122603 # Per bank write bursts +system.physmem.perBankWrBursts::14 113656 # Per bank write bursts +system.physmem.perBankWrBursts::15 114352 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 47 # Number of times write queue was full causing retry -system.physmem.totGap 51358447292000 # Total gap between requests +system.physmem.numWrRetry 644 # Number of times write queue was full causing retry +system.physmem.totGap 51318117066500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1015255 # Read request sizes (log2) +system.physmem.readPktSize::6 1013635 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1926435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 609091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 267826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 93793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1927502 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 564185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 294633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 102008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 45915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -162,210 +162,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 38881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 81306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 107299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 121019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 120126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 130475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 126860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 129040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 115411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 107895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 107384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 92996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 90709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 88958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 633988 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.443718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.837628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.480307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 262069 41.34% 41.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 150940 23.81% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56528 8.92% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28800 4.54% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20482 3.23% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13112 2.07% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10788 1.70% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9843 1.55% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 81426 12.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 633988 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79397 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.779954 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 57.830581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 79390 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 29010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 66066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 62259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 89013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 88926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 107579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 116711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 122723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 101978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 95256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 108517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 90319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 86324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 81769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2118 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 627585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.090291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.534210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.652886 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 259317 41.32% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149298 23.79% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56496 9.00% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28437 4.53% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21665 3.45% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12676 2.02% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11310 1.80% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8646 1.38% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 79740 12.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 627585 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69573 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.561338 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 62.076495 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 69566 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79397 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.206066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.327441 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 16.891492 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 78 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 11 0.01% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.01% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 74 0.09% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 53395 67.25% 67.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2838 3.57% 71.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 719 0.91% 71.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6583 8.29% 80.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7477 9.42% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1320 1.66% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1452 1.83% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 838 1.06% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 841 1.06% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 314 0.40% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 349 0.44% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 180 0.23% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 342 0.43% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 280 0.35% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 234 0.29% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 238 0.30% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 362 0.46% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 134 0.17% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 99 0.12% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 90 0.11% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 295 0.37% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 94 0.12% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 72 0.09% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 132 0.17% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 106 0.13% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 42 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 41 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 32 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 104 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 22 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 10 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 22 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 21 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 15 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 11 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 20 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 17 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 9 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79397 # Writes before turning the bus around for reads -system.physmem.totQLat 27026112263 # Total ticks spent queuing -system.physmem.totMemAccLat 46051868513 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5073535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26634.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 69573 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69573 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.030170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.998159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 37.100716 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 59064 84.90% 84.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 4267 6.13% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4153 5.97% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 990 1.42% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 298 0.43% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 151 0.22% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 89 0.13% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 92 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 109 0.16% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 106 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 80 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 57 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 25 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 19 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 14 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1600-1631 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69573 # Writes before turning the bus around for reads +system.physmem.totQLat 27603415095 # Total ticks spent queuing +system.physmem.totMemAccLat 46598965095 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5065480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27246.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45384.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45996.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 2.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.31 # Average write queue length when enqueuing -system.physmem.readRowHits 781715 # Number of row buffer hits during reads -system.physmem.writeRowHits 1520891 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes -system.physmem.avgGap 17443477.58 # Average gap between requests -system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2437517880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1329994875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3927541800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6247264320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1237564295100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29729485998000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34335476748615 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.545842 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49457442122001 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.19 # Average write queue length when enqueuing +system.physmem.readRowHits 781690 # Number of row buffer hits during reads +system.physmem.writeRowHits 1484389 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.93 # Row buffer hit rate for writes +system.physmem.avgGap 17433054.06 # Average gap between requests +system.physmem.pageHitRate 78.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2390683680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1304440500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3869626800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6131097360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1233875646405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29708521981500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34307943272085 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.534751 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49422598441359 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713624640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 186034306749 # Time in different power states +system.physmem_0.memoryStateTime::ACT 181894714141 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2355431400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1285205625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3987126000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6206576400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235795450580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29731037607750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34335151534395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.539510 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49460023829001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem_1.actEnergy 2353858920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1284347625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4032475200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6054996240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1235994503985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29706663342750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34308233320560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.540403 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49419482573169 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713624640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183452804499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 185010821331 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -395,15 +360,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 134182977 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91246699 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5930019 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 92418572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 65829087 # Number of BTB hits +system.cpu0.branchPred.lookups 133240776 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90773806 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5898398 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90806413 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 65300191 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.229284 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17386110 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187768 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.911431 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17271308 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187435 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -434,97 +399,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 898809 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 898809 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17395 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94113 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 544060 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 354749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2049.828188 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 11956.771667 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 349905 98.63% 98.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 2560 0.72% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 1330 0.37% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 450 0.13% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 167 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 126 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 45 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 59 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 16 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 24 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 354749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 411281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21163.528109 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16798.259479 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15588.127658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 367100 89.26% 89.26% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 39499 9.60% 98.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2985 0.73% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 830 0.20% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 180 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 394 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 143 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 73 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 14 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 17 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 411281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 359646036796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.131612 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.643594 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 358749976796 99.75% 99.75% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 501279000 0.14% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 178636500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 105104000 0.03% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 41922000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 20797500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 20431000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 22734000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 4793500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 308500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walks 900960 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 900960 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16847 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91388 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 546326 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 354634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2141.455698 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12590.575916 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 352292 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1866 0.53% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 247 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 95 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 68 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 354634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 411836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21432.646658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17288.307814 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16337.255715 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 405278 98.41% 98.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5723 1.39% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 333 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 332 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 90 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 39 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 411836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 323720569592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.132299 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.681450 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 322818413592 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 497609500 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 179612000 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 106469500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 44651500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 21065000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 19836500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 27755000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 4822000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 304000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 19500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::44-47 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 3500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 359646036796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94113 84.40% 84.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17395 15.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 111508 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 898809 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::48-51 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 323720569592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 91388 84.43% 84.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16847 15.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 108235 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 900960 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 898809 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111508 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 900960 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108235 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111508 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1010317 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108235 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1009195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106848795 # DTB read hits -system.cpu0.dtb.read_misses 623268 # DTB read misses -system.cpu0.dtb.write_hits 83024984 # DTB write hits -system.cpu0.dtb.write_misses 275541 # DTB write misses -system.cpu0.dtb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 105886901 # DTB read hits +system.cpu0.dtb.read_misses 623655 # DTB read misses +system.cpu0.dtb.write_hits 81874264 # DTB write hits +system.cpu0.dtb.write_misses 277305 # DTB write misses +system.cpu0.dtb.flush_tlb 1077 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56194 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 160 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9669 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 54719 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 205 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9949 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56033 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 107472063 # DTB read accesses -system.cpu0.dtb.write_accesses 83300525 # DTB write accesses +system.cpu0.dtb.perms_faults 55268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106510556 # DTB read accesses +system.cpu0.dtb.write_accesses 82151569 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 189873779 # DTB hits -system.cpu0.dtb.misses 898809 # DTB misses -system.cpu0.dtb.accesses 190772588 # DTB accesses +system.cpu0.dtb.hits 187761165 # DTB hits +system.cpu0.dtb.misses 900960 # DTB misses +system.cpu0.dtb.accesses 188662125 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -554,673 +508,680 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 108604 # Table walker walks requested -system.cpu0.itb.walker.walksLong 108604 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3026 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 75552 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14309 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 94295 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1394.214964 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8384.902945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 93563 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 326 0.35% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 303 0.32% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 55 0.06% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 94295 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 92887 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25650.201395 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21071.590317 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17522.957706 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 91125 98.10% 98.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1488 1.60% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 173 0.19% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 92887 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 604413242668 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.909243 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.287630 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 54912274056 9.09% 9.09% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 549448743612 90.91% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 47582500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4106500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 406500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 604413242668 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 75552 96.15% 96.15% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3026 3.85% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 78578 # Table walker page sizes translated +system.cpu0.itb.walker.walks 103995 # Table walker walks requested +system.cpu0.itb.walker.walksLong 103995 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2920 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70184 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 13953 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 90042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1564.791986 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9356.128105 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 89344 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 299 0.33% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 238 0.26% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 101 0.11% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 90042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 87057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26438.085553 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21999.622082 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18398.516639 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48630 55.86% 55.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 36690 42.14% 98.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 630 0.72% 98.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 790 0.91% 99.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 103 0.12% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 96 0.11% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 24 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 87057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 276399275336 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.905006 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -250074257964 -90.48% -90.48% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 526414060300 190.45% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 52102500 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6093500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 943000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 232500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 42500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::7 59000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 276399275336 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 70184 96.01% 96.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2920 3.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 73104 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108604 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108604 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 103995 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 103995 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78578 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78578 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 187182 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 96451691 # ITB inst hits -system.cpu0.itb.inst_misses 108604 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73104 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73104 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 177099 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 95374234 # ITB inst hits +system.cpu0.itb.inst_misses 103995 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1077 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 42484 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40386 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204587 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 207806 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 96560295 # ITB inst accesses -system.cpu0.itb.hits 96451691 # DTB hits -system.cpu0.itb.misses 108604 # DTB misses -system.cpu0.itb.accesses 96560295 # DTB accesses -system.cpu0.numCycles 678169162 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 95478229 # ITB inst accesses +system.cpu0.itb.hits 95374234 # DTB hits +system.cpu0.itb.misses 103995 # DTB misses +system.cpu0.itb.accesses 95478229 # DTB accesses +system.cpu0.numCycles 670757384 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 248888472 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 597668364 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 134182977 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83215197 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 388705337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13495131 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2539677 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 21156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 4430 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5365960 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 171714 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 96228071 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3656691 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 42208 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 652445982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.071952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.318616 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 244295585 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 592642803 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 133240776 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82571499 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 387821427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13413764 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2417197 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3440 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5441880 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 164758 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2028 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 95148929 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3635106 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41714 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 646873994 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.071808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.317751 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 504779765 77.37% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18600914 2.85% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18675892 2.86% 83.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13601130 2.08% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28939785 4.44% 89.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9186194 1.41% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9881419 1.51% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8590984 1.32% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40189899 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 500514392 77.37% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18314774 2.83% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18453367 2.85% 83.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13440049 2.08% 85.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 29078999 4.50% 89.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9061143 1.40% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9714650 1.50% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8499613 1.31% 93.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39797007 6.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 652445982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.197861 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.881297 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 202230502 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 323725330 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 107157055 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13964232 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5366791 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19957602 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1400195 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 652122035 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4310941 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5366791 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 210017200 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 28890111 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 254295095 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 113145299 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 40729265 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 636448025 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 83808 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2425012 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1797238 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 20704845 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 5054 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 608929978 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 980367872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 752692960 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 918645 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 510273791 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 98656187 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15296129 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13303285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78526904 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102548023 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 87419598 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13782768 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14655222 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 603808817 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15342366 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 603678166 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 829707 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 77491896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 54214041 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 352970 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 652445982 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.925254 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.646571 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 646873994 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.198642 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.883543 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 198183326 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 323426019 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105981621 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13950733 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5329290 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19638547 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1397625 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 646526277 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4318123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5329290 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 205971985 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23697587 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259101155 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111995163 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 40775442 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 631047036 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 83751 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2209243 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1613560 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 20761963 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3444 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 605295621 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 976490610 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 746368883 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 733214 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 508351996 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96943625 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15774650 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13795198 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78408950 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101681556 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86254396 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13698017 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14540360 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598113520 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15856672 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 599090036 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 857856 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 76035125 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 52627296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 360655 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 646873994 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.926131 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.649248 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 415092251 63.62% 63.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100237257 15.36% 78.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 44034564 6.75% 85.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31483239 4.83% 90.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23657330 3.63% 94.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16258445 2.49% 96.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10998020 1.69% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6466609 0.99% 99.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4218267 0.65% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 410738698 63.50% 63.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100810060 15.58% 79.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43443549 6.72% 85.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31018554 4.80% 90.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22931602 3.54% 94.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16104373 2.49% 96.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11033021 1.71% 98.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6462279 1.00% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4331858 0.67% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 652445982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 646873994 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3031745 25.47% 25.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22352 0.19% 25.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2380 0.02% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4899657 41.16% 66.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3948703 33.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2999808 25.24% 25.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22948 0.19% 25.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2663 0.02% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4871857 40.99% 66.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3988147 33.55% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408914830 67.74% 67.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1483700 0.25% 67.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67594 0.01% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 189 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 10 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 26 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 67735 0.01% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 109003987 18.06% 86.06% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84140078 13.94% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 406422040 67.84% 67.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1476912 0.25% 68.09% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65361 0.01% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 96 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 58788 0.01% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108073598 18.04% 86.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82993236 13.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 603678166 # Type of FU issued -system.cpu0.iq.rate 0.890159 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11904839 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019721 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1871435984 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 696824280 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 580857585 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1100876 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 525941 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 475487 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 614994656 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 588349 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4797344 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 599090036 # Type of FU issued +system.cpu0.iq.rate 0.893155 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11885426 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019839 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1856813329 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 690194574 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 576693438 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 984019 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 484790 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 438468 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 610449620 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 525838 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4726109 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16957941 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 22519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 718505 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 9238289 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16731454 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 21127 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 684950 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 9161643 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3918093 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8730401 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3853062 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8592397 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5366791 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15638409 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 11458161 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 619287399 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1818065 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102548023 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 87419598 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13010956 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 256814 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11089494 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 718505 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2724850 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2330540 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5055390 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 596785117 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106839289 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6007087 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5329290 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14836046 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7169747 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 614106722 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1810261 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 101681556 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86254396 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13499171 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 248453 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6830033 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 684950 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2723761 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2339558 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5063319 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 592213762 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105878130 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5990174 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136216 # number of nop insts executed -system.cpu0.iew.exec_refs 189866682 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110402162 # Number of branches executed -system.cpu0.iew.exec_stores 83027393 # Number of stores executed -system.cpu0.iew.exec_rate 0.879994 # Inst execution rate -system.cpu0.iew.wb_sent 582539449 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 581333072 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286508471 # num instructions producing a value -system.cpu0.iew.wb_consumers 497555384 # num instructions consuming a value +system.cpu0.iew.exec_nop 136530 # number of nop insts executed +system.cpu0.iew.exec_refs 187756937 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109862908 # Number of branches executed +system.cpu0.iew.exec_stores 81878807 # Number of stores executed +system.cpu0.iew.exec_rate 0.882903 # Inst execution rate +system.cpu0.iew.wb_sent 578421970 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 577131906 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 284711853 # num instructions producing a value +system.cpu0.iew.wb_consumers 494921051 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.857210 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575832 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.860418 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575267 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 83249738 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14989396 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4548973 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 638320811 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.839633 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.833868 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 81841846 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15496017 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4520537 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 632994694 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.840706 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.831217 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 441333872 69.14% 69.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97259629 15.24% 84.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33853962 5.30% 89.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15327337 2.40% 92.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10781377 1.69% 93.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6688169 1.05% 94.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6042869 0.95% 95.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4086388 0.64% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22947208 3.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 436057133 68.89% 68.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 98370072 15.54% 84.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33369017 5.27% 89.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15116509 2.39% 92.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10820224 1.71% 93.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6529796 1.03% 94.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6075579 0.96% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3929496 0.62% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22726868 3.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 638320811 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 456208771 # Number of instructions committed -system.cpu0.commit.committedOps 535955511 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 632994694 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453175477 # Number of instructions committed +system.cpu0.commit.committedOps 532162399 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 163771391 # Number of memory references committed -system.cpu0.commit.loads 85590082 # Number of loads committed -system.cpu0.commit.membars 3686850 # Number of memory barriers committed -system.cpu0.commit.branches 101715990 # Number of branches committed -system.cpu0.commit.fp_insts 455933 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 492018334 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13342246 # Number of function calls committed. +system.cpu0.commit.refs 162042855 # Number of memory references committed +system.cpu0.commit.loads 84950102 # Number of loads committed +system.cpu0.commit.membars 3716655 # Number of memory barriers committed +system.cpu0.commit.branches 101218853 # Number of branches committed +system.cpu0.commit.fp_insts 419354 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 488117298 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13243427 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 370951931 69.21% 69.21% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1123996 0.21% 69.42% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 50135 0.01% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 58016 0.01% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 85590082 15.97% 85.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 78181309 14.59% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 368889724 69.32% 69.32% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1132190 0.21% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48139 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 49491 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84950102 15.96% 85.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77092753 14.49% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 535955511 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22947208 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 532162399 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22726868 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1230638929 # The number of ROB reads -system.cpu0.rob.rob_writes 1252557383 # The number of ROB writes -system.cpu0.timesIdled 4102528 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25723180 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 48923483834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 456208771 # Number of Instructions Simulated -system.cpu0.committedOps 535955511 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.486532 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.486532 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.672706 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.672706 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 703703491 # number of integer regfile reads -system.cpu0.int_regfile_writes 414789220 # number of integer regfile writes -system.cpu0.fp_regfile_reads 851205 # number of floating regfile reads -system.cpu0.fp_regfile_writes 517790 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127713204 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128825628 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2353610328 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15112961 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10694855 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.983549 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 305873629 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10695367 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.598703 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 310.817389 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 201.166160 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.392903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 1220262369 # The number of ROB reads +system.cpu0.rob.rob_writes 1241914021 # The number of ROB writes +system.cpu0.timesIdled 4040058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23883390 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 52531652861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 453175477 # Number of Instructions Simulated +system.cpu0.committedOps 532162399 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.480127 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.480127 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.675618 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.675618 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 698520758 # number of integer regfile reads +system.cpu0.int_regfile_writes 411524007 # number of integer regfile writes +system.cpu0.fp_regfile_reads 797183 # number of floating regfile reads +system.cpu0.fp_regfile_writes 468068 # number of floating regfile writes +system.cpu0.cc_regfile_reads 128308023 # number of cc regfile reads +system.cpu0.cc_regfile_writes 129504102 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2335799510 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15629054 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10737693 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983333 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 307043958 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10738205 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.593602 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1675743000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 201.777727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 310.205606 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.394097 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.605870 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999967 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1351414929 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1351414929 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 81475453 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80033887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 161509340 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68849485 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67022058 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135871543 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201211 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202496 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403707 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171344 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 154502 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 325846 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1773976 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1825826 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3599802 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028728 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2086704 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4115432 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150324938 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 147055945 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 297380883 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150526149 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 147258441 # number of overall hits -system.cpu0.dcache.overall_hits::total 297784590 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6522961 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6552499 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 13075460 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6494487 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6576721 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13071208 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 662604 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 664801 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1327405 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 630242 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 610465 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1240707 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 318489 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 320942 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 639431 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13017448 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 13129220 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 26146668 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13680052 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13794021 # number of overall misses -system.cpu0.dcache.overall_misses::total 27474073 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112227265953 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112380964165 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 224608230118 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 258123381451 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 251959078660 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 510082460111 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 25291195259 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 24024875532 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 49316070791 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4598532454 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4591438187 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 9189970641 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 148500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 161500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 370350647404 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 364340042825 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 734690690229 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 370350647404 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 364340042825 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 734690690229 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87998414 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 86586386 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 174584800 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75343972 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 73598779 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 148942751 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 863815 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 867297 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1731112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 801586 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 764967 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1566553 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2092465 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2146768 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4239233 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2028729 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2086710 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4115439 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163342386 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 160185165 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 323527551 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164206201 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 161052462 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 325258663 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074126 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.075676 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.074895 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086198 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.089359 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087760 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767067 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.766521 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766793 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.786244 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.798028 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.791998 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.152208 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149500 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.150836 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.079694 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.081963 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.080817 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.083310 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.085649 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.084468 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17204.957373 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17150.855600 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17177.845377 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39744.999328 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38310.744619 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39023.360359 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40129.339617 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39355.041701 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39748.361854 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.591141 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14306.130662 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14372.106828 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24750 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23071.428571 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28450.326623 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27750.318970 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28098.826597 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27072.312839 # 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number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 81489620 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 162142386 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67583074 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 68792819 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 136375893 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205065 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202220 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 407285 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 153643 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 172343 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 325986 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1812235 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1802328 # 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number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 187500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 109500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 297000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 332579661708 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 327047107460 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 659626769168 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 332579661708 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 327047107460 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 659626769168 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87185339 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 87714211 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 174899550 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74244222 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 75229092 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 149473314 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 912975 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 824708 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1737683 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 787684 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 779176 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1566860 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2117860 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2138844 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4256704 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2053136 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2077483 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4130619 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 161429561 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 162943303 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 324372864 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162342536 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 163768011 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 326110547 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074927 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.070964 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.072940 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089719 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.085556 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087624 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.775388 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.754798 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765616 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.804943 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.778814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.791950 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.144308 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.150854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081731 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.077701 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.079706 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085631 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.081111 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.083361 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15528.236116 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15442.457065 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15486.382024 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34699.773331 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35878.547755 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35279.041112 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 29835.411019 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28593.641157 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 29228.139909 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13079.492784 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13139.193191 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13110.778969 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20833.333333 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 36500 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24750 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25207.419628 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25831.341957 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25512.951346 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23923.787195 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24620.826690 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24264.380418 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 52126007 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 51266 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3578465 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1028 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.566583 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.869650 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8181117 # number of writebacks -system.cpu0.dcache.writebacks::total 8181117 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664959 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3663666 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7328625 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5405222 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5470276 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10875498 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12970544028 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12958416533 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25928960561 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 23908668069 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 22678349912 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 46587017981 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1638689162 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1618682187 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3257371349 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 136500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83760487610 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83733721981 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 167494209591 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 96731031638 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 96692138514 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 193423170152 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2840564251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2875998253 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716562504 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2826497047 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2753568465 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5580065512 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5667061298 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5629566718 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296628016 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032478 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033364 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032917 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014457 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759266 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759942 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759604 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782045 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793348 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787564 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059588 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058772 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059175 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024166 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024942 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024550 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028033 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028900 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028462 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15194.842233 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15267.007055 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15231.118222 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37028.269629 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35817.314181 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36418.054436 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19776.240580 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19660.923741 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19718.440531 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38139.389718 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37368.446925 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37760.164230 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.632730 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12829.374550 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12985.076435 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21071.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21219.868737 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20958.171617 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21088.229225 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21014.177225 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20774.471344 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20893.660889 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 8209351 # number of writebacks +system.cpu0.dcache.writebacks::total 8209351 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3628927 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3346283 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6975210 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5547863 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5347347 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10895210 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3396 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3377 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6773 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 184138 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 204631 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 388769 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9176790 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8693630 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 17870420 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9176790 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8693630 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17870420 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2903646 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2878308 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5781954 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1113285 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1088926 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2202211 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 695379 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 617800 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1313179 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 630645 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 603456 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1234101 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121487 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 131885 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253372 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4016931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3967234 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7984165 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39142786504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39217956097 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 78360742601 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11875956517 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9839614769 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21715571286 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17839341538 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16312287276 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 34151628814 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1586128009 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1744790264 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3330918273 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 174000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 279000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82699431205 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 82313052514 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 165012483719 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94575387722 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 92152667283 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 186728055005 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2796204500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2965118250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5761322750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2832162536 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2783504957 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5615667493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5628367036 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5748623207 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11376990243 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032815 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033059 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014995 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014475 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014733 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.761663 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755707 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.800632 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.774480 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787627 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057363 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061662 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059523 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024883 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029027 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028510 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15000.673188 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14972.371413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14986.584314 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35159.717866 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36015.262834 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35582.758692 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17078.393965 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15926.861070 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16536.642214 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 28287.454175 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27031.444341 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27673.285099 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13055.948447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13229.633878 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13146.355055 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23250 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20587.715150 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20748.222191 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20667.469137 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1231,137 +1192,137 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16173930 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.955160 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 173933615 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16174442 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.753608 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13621642000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 273.473305 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 238.481855 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.534128 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.465785 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16169102 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 173971503 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16169614 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.759162 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13124671250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 233.058192 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 278.897543 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.455192 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.544722 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999914 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 97614087232 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 193582181661 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95968094429 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 97614087232 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 193582181661 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 951349751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 639066000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1590415751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 951349751 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 639066000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1590415751 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084503 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084503 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084503 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11971.882637 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1369,15 +1330,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 132595782 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89991047 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5894262 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90157022 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 64704998 # Number of BTB hits +system.cpu1.branchPred.lookups 133788555 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5908759 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 92439735 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65341745 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.769227 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17429206 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189878 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 70.685777 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17599042 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188594 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1407,95 +1368,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 890417 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 890417 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17386 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91593 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 535956 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 354461 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2058.191169 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12119.324471 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 349672 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2519 0.71% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 1342 0.38% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 424 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 149 0.04% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 114 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 10 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 354461 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 404532 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20689.820452 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16434.872295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15113.304602 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 363916 89.96% 89.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 36589 9.04% 99.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 2703 0.67% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 595 0.15% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 189 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 278 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 138 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 43 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 30 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 404532 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 334236526020 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.086173 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.625283 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 333380386520 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 477486500 0.14% 99.89% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 168839000 0.05% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 100636500 0.03% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 41145500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 20471500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 20409500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 23342000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 3487500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 317500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 334236526020 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91594 84.05% 84.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17386 15.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108980 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 890417 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 918015 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 918015 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17288 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94464 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 562013 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 356002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2214.229134 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13073.684616 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 353584 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1851 0.52% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 299 0.08% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 120 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 79 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 356002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 421643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21453.513266 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17357.718896 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16015.202358 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 415023 98.43% 98.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 5756 1.37% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 364 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 366 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 33 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 421643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 354035793664 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.135779 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.675726 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 353071895664 99.73% 99.73% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 535230500 0.15% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 190116000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 115191500 0.03% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 44312000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 22451500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 21588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 29378000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5201500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 359000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 41000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 354035793664 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94465 84.53% 84.53% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17288 15.47% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 111753 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918015 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 890417 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108980 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918015 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111753 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108980 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 999397 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111753 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1029768 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 105460349 # DTB read hits -system.cpu1.dtb.read_misses 614707 # DTB read misses -system.cpu1.dtb.write_hits 81263219 # DTB write hits -system.cpu1.dtb.write_misses 275710 # DTB write misses -system.cpu1.dtb.flush_tlb 1092 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 105548583 # DTB read hits +system.cpu1.dtb.read_misses 631805 # DTB read misses +system.cpu1.dtb.write_hits 82907544 # DTB write hits +system.cpu1.dtb.write_misses 286210 # DTB write misses +system.cpu1.dtb.flush_tlb 1083 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55487 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 238 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9789 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56278 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9625 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106075056 # DTB read accesses -system.cpu1.dtb.write_accesses 81538929 # DTB write accesses +system.cpu1.dtb.perms_faults 55021 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106180388 # DTB read accesses +system.cpu1.dtb.write_accesses 83193754 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 186723568 # DTB hits -system.cpu1.dtb.misses 890417 # DTB misses -system.cpu1.dtb.accesses 187613985 # DTB accesses +system.cpu1.dtb.hits 188456127 # DTB hits +system.cpu1.dtb.misses 918015 # DTB misses +system.cpu1.dtb.accesses 189374142 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1525,392 +1481,399 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 101825 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101825 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2978 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69124 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 13788 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 88037 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1472.687620 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8948.821118 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 87265 99.12% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 389 0.44% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 275 0.31% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 88037 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 85890 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25260.851287 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20589.361475 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17130.840101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 84234 98.07% 98.07% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1438 1.67% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 145 0.17% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 40 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 85890 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 299874193152 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.837074 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -250957583628 -83.69% -83.69% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 550779312780 183.67% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 46468000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5344000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 484000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 65500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 54500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 299874193152 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69124 95.87% 95.87% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2978 4.13% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72102 # Table walker page sizes translated +system.cpu1.itb.walker.walks 104751 # Table walker walks requested +system.cpu1.itb.walker.walksLong 104751 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2979 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 72067 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14103 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 90648 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1509.569985 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8604.112743 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 89986 99.27% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 255 0.28% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 242 0.27% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 116 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 90648 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 89149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26484.081515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22228.139492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17447.399907 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 48433 54.33% 54.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 39159 43.93% 98.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 575 0.64% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 708 0.79% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 80 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 45 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 89149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 396982969624 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.388871 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -154312061728 -38.87% -38.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 551239764852 138.86% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 48839000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5683000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 518000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 149500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::7 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::8 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::9 8500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::10 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 396982969624 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 72067 96.03% 96.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2979 3.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 75046 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101825 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101825 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104751 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104751 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72102 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72102 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 173927 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95285493 # ITB inst hits -system.cpu1.itb.inst_misses 101825 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 75046 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 75046 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 179797 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 96448537 # ITB inst hits +system.cpu1.itb.inst_misses 104751 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1092 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1083 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40874 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 42139 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205822 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 204302 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95387318 # ITB inst accesses -system.cpu1.itb.hits 95285493 # DTB hits -system.cpu1.itb.misses 101825 # DTB misses -system.cpu1.itb.accesses 95387318 # DTB accesses -system.cpu1.numCycles 677360427 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 96553288 # ITB inst accesses +system.cpu1.itb.hits 96448537 # DTB hits +system.cpu1.itb.misses 104751 # DTB misses +system.cpu1.itb.accesses 96553288 # DTB accesses +system.cpu1.numCycles 667631540 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 248549507 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 588684684 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132595782 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82134204 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 389145480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13431349 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2335492 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 20294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4597 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5447640 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 169416 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95058557 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3668998 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 40025 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 652389771 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.056521 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.304488 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 247941482 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 595071407 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133788555 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82940787 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 381163571 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13497944 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2492160 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22589 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 3825 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5325029 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 172051 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 1992 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 96222293 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3665245 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41130 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643871402 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.082515 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.328245 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 506719262 77.67% 77.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18449281 2.83% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18323109 2.81% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13434339 2.06% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28729534 4.40% 89.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8986163 1.38% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9758970 1.50% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8450464 1.30% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39538649 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 496782409 77.16% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18583795 2.89% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18517016 2.88% 82.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13597412 2.11% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28667245 4.45% 89.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9152993 1.42% 90.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9918803 1.54% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8570268 1.33% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40081461 6.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 652389771 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.195754 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.869086 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201147393 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 326816283 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105097642 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 14007460 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5318954 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19647868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1416154 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 641757938 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4369017 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5318954 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 208911045 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28047403 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 258823969 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 111174433 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 40111705 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 626286274 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 89729 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2292362 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1848085 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19940508 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 5105 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 599962292 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 966932024 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 740689310 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 881849 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 503173353 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96788934 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15525446 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13560324 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 79127309 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101049697 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85573282 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13915572 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14825014 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 593826390 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15642550 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 594476204 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 818225 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 76136612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53142905 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356951 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 652389771 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.911229 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.632553 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643871402 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200393 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.891317 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201631753 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 315887121 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 107474204 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13522341 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5353840 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 20035378 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1415024 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 649950843 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4347472 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5353840 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 209303047 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22542941 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 254388545 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 113174340 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39106401 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 634340427 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 84329 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1777036 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1562975 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19949989 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3657 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 605941232 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 974899397 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 750081260 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 811718 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 508709616 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97231611 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15188925 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13206274 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 75533982 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 102194667 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 87314859 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13957552 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14774854 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 601797044 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15287986 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 601499543 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 865295 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 76155843 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52376442 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 362406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643871402 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.934192 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.656161 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 416908971 63.90% 63.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 100667120 15.43% 79.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43571359 6.68% 86.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31041594 4.76% 90.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23116047 3.54% 94.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15866958 2.43% 96.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10833871 1.66% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6331428 0.97% 99.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4052423 0.62% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 408171960 63.39% 63.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99067431 15.39% 78.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 44002532 6.83% 85.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31313283 4.86% 90.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23144485 3.59% 94.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16264635 2.53% 96.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11075626 1.72% 98.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6519272 1.01% 99.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4312178 0.67% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 652389771 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643871402 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2996828 25.66% 25.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24624 0.21% 25.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2734 0.02% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 3 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4869636 41.69% 67.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3787065 32.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3037678 26.20% 26.20% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 24339 0.21% 26.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2694 0.02% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4607398 39.74% 66.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3921783 33.83% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 402964828 67.78% 67.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1445986 0.24% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66608 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 132 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 61370 0.01% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 107585906 18.10% 86.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82351372 13.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 408162511 67.86% 67.86% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1426997 0.24% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69303 0.01% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 134 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 22 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 70416 0.01% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 107729216 17.91% 86.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 84040920 13.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 594476204 # Type of FU issued -system.cpu1.iq.rate 0.877636 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11680890 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019649 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1852781725 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 685800777 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 571863197 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1059569 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 502092 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 457373 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 605590748 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 566345 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4749876 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 601499543 # Type of FU issued +system.cpu1.iq.rate 0.900945 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11593896 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019275 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1858238935 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 693444958 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 579923061 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1090744 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 536293 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 488146 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 612510547 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 582891 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4820885 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16757289 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 22108 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 708788 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9117452 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16648209 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 23106 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 751890 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9224511 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3937125 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8714130 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4009170 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7426024 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5318954 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15381414 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 10835277 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 609605144 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1787029 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101049697 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85573282 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13260611 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 256865 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 10466220 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 708788 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2676587 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2314011 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4990598 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 587727574 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 105451218 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5872593 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5353840 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14516681 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6539646 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 617219827 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1819635 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 102194667 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 87314859 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12911400 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 240081 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6211315 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 751890 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2725767 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2332140 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5057907 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 594561904 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 105538370 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6033124 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 136204 # number of nop insts executed -system.cpu1.iew.exec_refs 186716455 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109034476 # Number of branches executed -system.cpu1.iew.exec_stores 81265237 # Number of stores executed -system.cpu1.iew.exec_rate 0.867673 # Inst execution rate -system.cpu1.iew.wb_sent 573536970 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 572320570 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281697554 # num instructions producing a value -system.cpu1.iew.wb_consumers 489376492 # num instructions consuming a value +system.cpu1.iew.exec_nop 134797 # number of nop insts executed +system.cpu1.iew.exec_refs 188445888 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110364560 # Number of branches executed +system.cpu1.iew.exec_stores 82907518 # Number of stores executed +system.cpu1.iew.exec_rate 0.890554 # Inst execution rate +system.cpu1.iew.wb_sent 581679133 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 580411207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 286057076 # num instructions producing a value +system.cpu1.iew.wb_consumers 496538403 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.844928 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575625 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.869359 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.576103 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 81905872 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15285599 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4497270 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 638458448 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.826393 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.816586 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 81975668 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14925580 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4513358 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 629946041 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.849503 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.842378 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 442788562 69.35% 69.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 97620349 15.29% 84.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33589881 5.26% 89.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 14950626 2.34% 92.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10704317 1.68% 93.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6546690 1.03% 94.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5838446 0.91% 95.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3972340 0.62% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22447237 3.52% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433603733 68.83% 68.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96615693 15.34% 84.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33704251 5.35% 89.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15419971 2.45% 91.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10970958 1.74% 93.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6585832 1.05% 94.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6182969 0.98% 95.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3954863 0.63% 96.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22907771 3.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 638458448 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 448865132 # Number of instructions committed -system.cpu1.commit.committedOps 527617659 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 629946041 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 455165016 # Number of instructions committed +system.cpu1.commit.committedOps 535141123 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160748237 # Number of memory references committed -system.cpu1.commit.loads 84292407 # Number of loads committed -system.cpu1.commit.membars 3769330 # Number of memory barriers committed -system.cpu1.commit.branches 100442689 # Number of branches committed -system.cpu1.commit.fp_insts 439800 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 484228202 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13335340 # Number of function calls committed. +system.cpu1.commit.refs 163636805 # Number of memory references committed +system.cpu1.commit.loads 85546457 # Number of loads committed +system.cpu1.commit.membars 3765916 # Number of memory barriers committed +system.cpu1.commit.branches 101697828 # Number of branches committed +system.cpu1.commit.fp_insts 467953 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 491500354 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13521989 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 365655543 69.30% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1112211 0.21% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49677 0.01% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 51991 0.01% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84292407 15.98% 85.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76455830 14.49% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 370285651 69.19% 69.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1106053 0.21% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 52121 0.01% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 60451 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85546457 15.99% 85.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78090348 14.59% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 527617659 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22447237 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 535141123 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22907771 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1221498833 # The number of ROB reads -system.cpu1.rob.rob_writes 1232997569 # The number of ROB writes -system.cpu1.timesIdled 4096806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24970656 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 52437515063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 448865132 # Number of Instructions Simulated -system.cpu1.committedOps 527617659 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.509051 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.509051 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.662668 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.662668 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 693047790 # number of integer regfile reads -system.cpu1.int_regfile_writes 408438474 # number of integer regfile writes -system.cpu1.fp_regfile_reads 823112 # number of floating regfile reads -system.cpu1.fp_regfile_writes 494780 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126134775 # number of cc regfile reads -system.cpu1.cc_regfile_writes 127188255 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2330176021 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15424448 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40375 # Transaction distribution -system.iobus.trans_dist::ReadResp 40375 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.cpu1.rob.rob_reads 1220174232 # The number of ROB reads +system.cpu1.rob.rob_writes 1248183780 # The number of ROB writes +system.cpu1.timesIdled 4134360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23760138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 48765821681 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 455165016 # Number of Instructions Simulated +system.cpu1.committedOps 535141123 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.466790 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.466790 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.681761 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.681761 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 701277155 # number of integer regfile reads +system.cpu1.int_regfile_writes 414494210 # number of integer regfile writes +system.cpu1.fp_regfile_reads 871148 # number of floating regfile reads +system.cpu1.fp_regfile_writes 523684 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126609999 # number of cc regfile reads +system.cpu1.cc_regfile_writes 127812398 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2340278076 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15057964 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1925,13 +1888,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1946,13 +1909,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1980,71 +1943,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042399628 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607055505 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 178994733 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148389509 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.429644 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.425424 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090563453000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.541528 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.888116 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221346 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430507 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651853 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090073143000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544298 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881126 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221519 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430070 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039614 # Number of tag accesses -system.iocache.tags.data_accesses 1039614 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses -system.iocache.demand_misses::total 8849 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8809 # number of overall misses -system.iocache.overall_misses::total 8849 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1920259350 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1925744350 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28938987545 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28938987545 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1920259350 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1926083350 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1920259350 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1926083350 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1661250694 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1666322694 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19868709302 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19868709302 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1661250694 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1666675194 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1661250694 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1666675194 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2058,55 +2021,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217988.347145 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217696.625593 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271309.790979 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271309.790979 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217661.131201 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217661.131201 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 227974 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188521.413300 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188306.327721 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186273.806551 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186273.806551 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 188282.330999 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 188282.330999 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 113607 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27752 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16342 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.214687 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.951842 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1462065868 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1465626868 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23392010493 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23392010493 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1462065868 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1465809868 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1462065868 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1465809868 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201855604 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1204997604 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322073410 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322073410 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1201855604 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1205191104 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1201855604 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1205191104 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2120,292 +2083,297 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165974.102395 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165682.440425 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219305.581011 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219305.581011 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136388.516114 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136173.308170 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134272.795039 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134272.795039 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1414814 # number of replacements -system.l2c.tags.tagsinuse 65356.208679 # Cycle average of tags in use -system.l2c.tags.total_refs 31586438 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1477430 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.379313 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2484527000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35855.564521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 171.544585 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 252.706280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3390.645466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10658.750636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 169.049447 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 250.456312 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3915.870098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10691.621334 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.547112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003856 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.162640 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003822 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.163141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997257 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 354 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 353 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2774 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5014 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53845 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005402 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.950043 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 297087469 # Number of tag accesses -system.l2c.tags.data_accesses 297087469 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 549429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 200595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 8013735 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3471974 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 542581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 184113 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 8064127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3507527 # number of ReadReq hits -system.l2c.ReadReq_hits::total 24534081 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8181117 # number of Writeback hits -system.l2c.Writeback_hits::total 8181117 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347604 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 365500 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 713104 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4965 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5155 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10120 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 785554 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 813200 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1598754 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 549429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 200595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8013735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4257528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 542581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 184113 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8064127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4320727 # number of demand (read+write) hits -system.l2c.demand_hits::total 26132835 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 549429 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 200595 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8013735 # number of overall hits -system.l2c.overall_hits::cpu0.data 4257528 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 542581 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 184113 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8064127 # number of overall hits -system.l2c.overall_hits::cpu1.data 4320727 # number of overall hits -system.l2c.overall_hits::total 26132835 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2398 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 49272 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 160159 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2534 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2288 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 47310 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 159515 # number of ReadReq misses -system.l2c.ReadReq_misses::total 426096 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 279272 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 241385 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 520657 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18107 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18517 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36624 # number of UpgradeReq misses +system.l2c.tags.replacements 1412518 # number of replacements +system.l2c.tags.tagsinuse 65354.490513 # Cycle average of tags in use +system.l2c.tags.total_refs 31645259 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1474766 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.457817 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2643820000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35783.123237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 158.967100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 249.670952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3744.975731 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12205.230455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 164.981843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 255.022053 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3435.700252 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9356.818889 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.546007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.186237 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.052425 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.142774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997230 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 337 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 333 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 503 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2841 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5066 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53373 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005142 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.944687 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 297548374 # Number of tag accesses +system.l2c.tags.data_accesses 297548374 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 541623 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 186900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7965775 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3551683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 548604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 190887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 8107304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3470388 # number of ReadReq hits +system.l2c.ReadReq_hits::total 24563164 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8209351 # number of Writeback hits +system.l2c.Writeback_hits::total 8209351 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 352587 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 361830 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 714417 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 4898 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5089 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9987 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 814701 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 785760 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1600461 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 541623 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 186900 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7965775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4366384 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 548604 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 190887 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 8107304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4256148 # number of demand (read+write) hits +system.l2c.demand_hits::total 26163625 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 541623 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 186900 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7965775 # number of overall hits +system.l2c.overall_hits::cpu0.data 4366384 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 548604 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 190887 # number of overall hits +system.l2c.overall_hits::cpu1.inst 8107304 # number of overall hits +system.l2c.overall_hits::cpu1.data 4256148 # number of overall hits +system.l2c.overall_hits::total 26163625 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2520 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2317 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 47910 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 162942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2554 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2304 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 48528 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 151193 # number of ReadReq misses +system.l2c.ReadReq_misses::total 420268 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 278058 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 241626 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 519684 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 18363 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18249 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36612 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 287058 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 276629 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 563687 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2620 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2398 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 49272 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 447217 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2534 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2288 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 47310 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036374 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036374 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 79682.628798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77675.511291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77355.208270 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33717.092556 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34183.846403 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33934.108791 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17759.726624 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17756.082251 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17757.910111 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83846.404002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 83507.798698 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 83680.233686 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89351.153103 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89221.557305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 89285.780821 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2619,57 +2591,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 489224 # Transaction distribution -system.membus.trans_dist::ReadResp 489224 # Transaction distribution -system.membus.trans_dist::WriteReq 33860 # Transaction distribution -system.membus.trans_dist::WriteResp 33860 # Transaction distribution -system.membus.trans_dist::Writeback 1299265 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 627170 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 627170 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37411 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37412 # Transaction distribution -system.membus.trans_dist::ReadExReq 563054 # Transaction distribution -system.membus.trans_dist::ReadExResp 563054 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 483310 # Transaction distribution +system.membus.trans_dist::ReadResp 483310 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::Writeback 1301300 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 626202 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 626202 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37394 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37396 # Transaction distribution +system.membus.trans_dist::ReadExReq 566817 # Transaction distribution +system.membus.trans_dist::ReadExResp 566817 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4332246 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4462384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4797472 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4328173 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4457819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4793358 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174236076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174408348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14052800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14052800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188461148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3233 # Total snoops (count) -system.membus.snoop_fanout::samples 2961771 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174172012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174343786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14081472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2786 # Total snoops (count) +system.membus.snoop_fanout::samples 2961350 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2961771 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2961350 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2961771 # Request fanout histogram -system.membus.reqLayer0.occupancy 99708500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2961350 # Request fanout histogram +system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5504999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5469002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18802986477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11041524273 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10120184001 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6008607805 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186568267 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151555991 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2680,11 +2652,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2713,58 +2685,56 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 25574289 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25566182 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33860 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33860 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8181117 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1340428 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1233761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46747 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46754 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2162441 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2162441 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32390529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29801361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 923404 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2600212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 65715506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036485248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1208333724 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3115152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8777312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2256711436 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 667123 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37442651 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003085 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.055458 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 25599599 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25591523 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8209351 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1340869 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1234101 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46602 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46614 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2167911 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2167911 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32380531 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29914539 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 911927 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2596271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 65803268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036169984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1212884202 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3059264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 669395 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37310136 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003099 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.055581 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 37327135 99.69% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115516 0.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 37194516 99.69% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115620 0.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37442651 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 56492183787 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 37310136 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3327000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 72944134855 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 43405971950 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 537017212 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24319536063 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 15088594286 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 530670154 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1517407654 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1505035766 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16420 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16426 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |