diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 11:07:18 +0100 |
commit | 62b6ff22ec1f90014b1d0fc778014bdb38cc09ce (patch) | |
tree | 8dc7be3b13f98b2f6d082dc7424335d9ddfe764d /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | |
parent | 71a02f624e9c406ad37a1ed7030f98a36da6e59f (diff) | |
download | gem5-62b6ff22ec1f90014b1d0fc778014bdb38cc09ce.tar.xz |
stats: update for snoop filter tweak
--HG--
extra : source : 2323557eb4f4866fa1ea1575a9f5969e0022adc1
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | 3357 |
1 files changed, 1685 insertions, 1672 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index ab74bea7e..0789be798 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,160 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.799232 # Number of seconds simulated -sim_ticks 51799232151500 # Number of ticks simulated -final_tick 51799232151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.821000 # Number of seconds simulated +sim_ticks 51820999867500 # Number of ticks simulated +final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 780767 # Simulator instruction rate (inst/s) -host_op_rate 917508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48392163425 # Simulator tick rate (ticks/s) -host_mem_usage 677024 # Number of bytes of host memory used -host_seconds 1070.41 # Real time elapsed on the host -sim_insts 835736802 # Number of instructions simulated -sim_ops 982105580 # Number of ops (including micro ops) simulated +host_inst_rate 784285 # Simulator instruction rate (inst/s) +host_op_rate 921634 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45455267989 # Simulator tick rate (ticks/s) +host_mem_usage 675212 # Number of bytes of host memory used +host_seconds 1140.04 # Real time elapsed on the host +sim_insts 894119248 # Number of instructions simulated +sim_ops 1050702892 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 74880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 80448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2375384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 17755184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 76352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 77888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2376540 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 17975768 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 395840 # Number of bytes read from this memory -system.physmem.bytes_read::total 41188284 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2375384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2376540 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 4751924 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 62641792 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 15860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 4720 # Number of bytes written to this memory -system.physmem.bytes_written::total 62662372 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1257 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 57776 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 277428 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1193 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1217 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56880 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 280881 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6185 # Number of read requests responded to by this memory -system.physmem.num_reads::total 683987 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 978778 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 1983 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 590 # Number of write requests responded to by this memory -system.physmem.num_writes::total 981351 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 45858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 342769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 347028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 795152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 45858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45880 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 91737 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1209319 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 306 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 91 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1209716 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1209319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 45858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 343075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2004869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 683987 # Number of read requests accepted -system.physmem.writeReqs 981351 # Number of write requests accepted -system.physmem.readBursts 683987 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 981351 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 43730304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44864 # Total number of bytes read from write queue -system.physmem.bytesWritten 62662336 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 41188284 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 62662372 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 701 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 26029680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 150208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 131904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2604676 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 25292888 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 407488 # Number of bytes read from this memory +system.physmem.bytes_read::total 57465468 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2599472 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2604676 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5204148 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78618432 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory +system.physmem.bytes_written::total 78639012 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1919 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1974 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64898 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 406717 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2061 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56824 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 395211 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6367 # Number of read requests responded to by this memory +system.physmem.num_reads::total 938318 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1228413 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1230986 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2370 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 50163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 502300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2545 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 488082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7863 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1108922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 50163 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50263 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 100425 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1517115 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1517512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1517115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2370 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 50163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 502300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 488479 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2626435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 938318 # Number of read requests accepted +system.physmem.writeReqs 1230986 # Number of write requests accepted +system.physmem.readBursts 938318 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1230986 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 60016640 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35712 # Total number of bytes read from write queue +system.physmem.bytesWritten 78638272 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 57465468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78639012 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 558 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 41322 # Per bank write bursts -system.physmem.perBankRdBursts::1 41177 # Per bank write bursts -system.physmem.perBankRdBursts::2 39218 # Per bank write bursts -system.physmem.perBankRdBursts::3 39952 # Per bank write bursts -system.physmem.perBankRdBursts::4 41092 # Per bank write bursts -system.physmem.perBankRdBursts::5 49504 # Per bank write bursts -system.physmem.perBankRdBursts::6 36877 # Per bank write bursts -system.physmem.perBankRdBursts::7 36988 # Per bank write bursts -system.physmem.perBankRdBursts::8 38459 # Per bank write bursts -system.physmem.perBankRdBursts::9 81977 # Per bank write bursts -system.physmem.perBankRdBursts::10 39138 # Per bank write bursts -system.physmem.perBankRdBursts::11 41925 # Per bank write bursts -system.physmem.perBankRdBursts::12 38445 # Per bank write bursts -system.physmem.perBankRdBursts::13 41518 # Per bank write bursts -system.physmem.perBankRdBursts::14 36799 # Per bank write bursts -system.physmem.perBankRdBursts::15 38895 # Per bank write bursts -system.physmem.perBankWrBursts::0 61042 # Per bank write bursts -system.physmem.perBankWrBursts::1 63110 # Per bank write bursts -system.physmem.perBankWrBursts::2 61459 # Per bank write bursts -system.physmem.perBankWrBursts::3 62355 # Per bank write bursts -system.physmem.perBankWrBursts::4 60847 # Per bank write bursts -system.physmem.perBankWrBursts::5 67831 # Per bank write bursts -system.physmem.perBankWrBursts::6 59687 # Per bank write bursts -system.physmem.perBankWrBursts::7 59677 # Per bank write bursts -system.physmem.perBankWrBursts::8 60696 # Per bank write bursts -system.physmem.perBankWrBursts::9 62695 # Per bank write bursts -system.physmem.perBankWrBursts::10 60108 # Per bank write bursts -system.physmem.perBankWrBursts::11 60915 # Per bank write bursts -system.physmem.perBankWrBursts::12 59030 # Per bank write bursts -system.physmem.perBankWrBursts::13 62102 # Per bank write bursts -system.physmem.perBankWrBursts::14 56975 # Per bank write bursts -system.physmem.perBankWrBursts::15 60570 # Per bank write bursts +system.physmem.perBankRdBursts::0 57802 # Per bank write bursts +system.physmem.perBankRdBursts::1 61444 # Per bank write bursts +system.physmem.perBankRdBursts::2 58618 # Per bank write bursts +system.physmem.perBankRdBursts::3 56911 # Per bank write bursts +system.physmem.perBankRdBursts::4 53280 # Per bank write bursts +system.physmem.perBankRdBursts::5 57178 # Per bank write bursts +system.physmem.perBankRdBursts::6 52016 # Per bank write bursts +system.physmem.perBankRdBursts::7 52831 # Per bank write bursts +system.physmem.perBankRdBursts::8 55081 # Per bank write bursts +system.physmem.perBankRdBursts::9 100686 # Per bank write bursts +system.physmem.perBankRdBursts::10 57898 # Per bank write bursts +system.physmem.perBankRdBursts::11 58894 # Per bank write bursts +system.physmem.perBankRdBursts::12 52465 # Per bank write bursts +system.physmem.perBankRdBursts::13 56002 # Per bank write bursts +system.physmem.perBankRdBursts::14 52925 # Per bank write bursts +system.physmem.perBankRdBursts::15 53729 # Per bank write bursts +system.physmem.perBankWrBursts::0 76591 # Per bank write bursts +system.physmem.perBankWrBursts::1 80097 # Per bank write bursts +system.physmem.perBankWrBursts::2 79619 # Per bank write bursts +system.physmem.perBankWrBursts::3 80251 # Per bank write bursts +system.physmem.perBankWrBursts::4 74804 # Per bank write bursts +system.physmem.perBankWrBursts::5 78970 # Per bank write bursts +system.physmem.perBankWrBursts::6 72699 # Per bank write bursts +system.physmem.perBankWrBursts::7 74032 # Per bank write bursts +system.physmem.perBankWrBursts::8 75192 # Per bank write bursts +system.physmem.perBankWrBursts::9 79224 # Per bank write bursts +system.physmem.perBankWrBursts::10 76715 # Per bank write bursts +system.physmem.perBankWrBursts::11 78463 # Per bank write bursts +system.physmem.perBankWrBursts::12 72476 # Per bank write bursts +system.physmem.perBankWrBursts::13 78380 # Per bank write bursts +system.physmem.perBankWrBursts::14 75126 # Per bank write bursts +system.physmem.perBankWrBursts::15 76084 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 35 # Number of times write queue was full causing retry -system.physmem.totGap 51799229214500 # Total gap between requests +system.physmem.numWrRetry 41 # Number of times write queue was full causing retry +system.physmem.totGap 51820996946500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 640871 # Read request sizes (log2) +system.physmem.readPktSize::6 895202 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 978778 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 654776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 22950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 529 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 667 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 66 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1228413 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 903707 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 501 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 492 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -165,188 +165,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1451 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1423 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 37595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 53715 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 53386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 56244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 54082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 56988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 54298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 54807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 54383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 55346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 57492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 55406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 55164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 56641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 53923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 52610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 52233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 437346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 243.268076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.507272 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 286.058540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 195461 44.69% 44.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 115696 26.45% 71.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 38501 8.80% 79.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20148 4.61% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13086 2.99% 87.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 8742 2.00% 89.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7314 1.67% 91.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5744 1.31% 92.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 32654 7.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 437346 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 51642 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.230801 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 107.035752 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 51638 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 66568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 69544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 72891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 70544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 68952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 70814 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 68944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 68807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 563401 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.102850 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.051526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.279361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250361 44.44% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146586 26.02% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 50209 8.91% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27045 4.80% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18004 3.20% 87.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12090 2.15% 89.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8995 1.60% 91.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7664 1.36% 92.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42447 7.53% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 563401 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65697 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.273848 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.818256 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65693 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 51642 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 51642 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.959355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.129785 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 8.514310 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 120 0.23% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 58 0.11% 0.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 71 0.14% 0.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 110 0.21% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 46610 90.26% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2201 4.26% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 409 0.79% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 381 0.74% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 125 0.24% 96.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 97 0.19% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 249 0.48% 97.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.07% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 313 0.61% 98.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 78 0.15% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 24 0.05% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 64 0.12% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 317 0.61% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 20 0.04% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 23 0.04% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 120 0.23% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 150 0.29% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 12 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 17 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 65697 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65697 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.702878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.053855 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.999985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 137 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 78 0.12% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 60 0.09% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 99 0.15% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51857 78.93% 79.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9705 14.77% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1082 1.65% 95.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 596 0.91% 96.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 852 1.30% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 335 0.51% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 83 0.13% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 33 0.05% 98.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 55 0.08% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 34 0.05% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 40 0.06% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 30 0.05% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 421 0.64% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 37 0.06% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 32 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 21 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 5 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 14 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 17 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 8 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 51642 # Writes before turning the bus around for reads -system.physmem.totQLat 9080957107 # Total ticks spent queuing -system.physmem.totMemAccLat 21892569607 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3416430000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13290.13 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 65697 # Writes before turning the bus around for reads +system.physmem.totQLat 12237400086 # Total ticks spent queuing +system.physmem.totMemAccLat 29820400086 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4688800000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13049.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32040.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.21 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31799.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.30 # Average write queue length when enqueuing -system.physmem.readRowHits 503634 # Number of row buffer hits during reads -system.physmem.writeRowHits 721404 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.68 # Row buffer hit rate for writes -system.physmem.avgGap 31104333.90 # Average gap between requests -system.physmem.pageHitRate 73.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1696456440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 925645875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2543814000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3214131840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1286151175755 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29951333686500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34629138628650 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.526160 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49826371298908 # Time in different power states -system.physmem_0.memoryStateTime::REF 1729690040000 # Time in different power states +system.physmem.avgWrQLen 7.91 # Average write queue length when enqueuing +system.physmem.readRowHits 705929 # Number of row buffer hits during reads +system.physmem.writeRowHits 897152 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.01 # Row buffer hit rate for writes +system.physmem.avgGap 23888305.63 # Average gap between requests +system.physmem.pageHitRate 73.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2146397400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1171149375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3510585000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3998568240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1301998363920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29950494857250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34648015573185 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.609580 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49824747021214 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730417000000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 243166128592 # Time in different power states +system.physmem_0.memoryStateTime::ACT 265835434786 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1609879320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 878406375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2785777800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3130429680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3383273718240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1282982007105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29954113659000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34628773877520 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.519119 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49831003018963 # Time in different power states -system.physmem_1.memoryStateTime::REF 1729690040000 # Time in different power states +system.physmem_1.actEnergy 2112914160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1152879750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3803904000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3963556800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1301510416275 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29950922881500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34648162204485 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.612409 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49825423536265 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730417000000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 238538435537 # Time in different power states +system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -400,70 +403,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 118484 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 118484 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17724 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 86321 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 118475 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 0.236337 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 81.347587 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-2047 118474 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 118475 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 104054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25330.679263 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 21934.679716 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 16178.136591 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 103422 99.39% 99.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 549 0.53% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 13 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 39 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 133030 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95696 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 133019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 133019 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 133019 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 116836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25679.131432 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22619.213536 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13703.555245 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 115888 99.19% 99.19% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 821 0.70% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 61 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 31 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 104054 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2515798788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.690729 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 1737735704 -69.07% -69.07% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -4253534492 169.07% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2515798788 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 86322 82.97% 82.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17724 17.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 104046 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 118484 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 116836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 9230012852 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.024648 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -227501296 -2.46% -2.46% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 9457514148 102.46% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 9230012852 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 95697 81.91% 81.91% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 21129 18.09% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 116826 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 133030 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 118484 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104046 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 133030 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116826 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104046 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 222530 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116826 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 249856 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78608030 # DTB read hits -system.cpu0.dtb.read_misses 90806 # DTB read misses -system.cpu0.dtb.write_hits 71283429 # DTB write hits -system.cpu0.dtb.write_misses 27678 # DTB write misses -system.cpu0.dtb.flush_tlb 51806 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 83528271 # DTB read hits +system.cpu0.dtb.read_misses 101098 # DTB read misses +system.cpu0.dtb.write_hits 76299925 # DTB write hits +system.cpu0.dtb.write_misses 31932 # DTB write misses +system.cpu0.dtb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 69055 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 73288 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4281 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9631 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78698836 # DTB read accesses -system.cpu0.dtb.write_accesses 71311107 # DTB write accesses +system.cpu0.dtb.perms_faults 9926 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83629369 # DTB read accesses +system.cpu0.dtb.write_accesses 76331857 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 149891459 # DTB hits -system.cpu0.dtb.misses 118484 # DTB misses -system.cpu0.dtb.accesses 150009943 # DTB accesses +system.cpu0.dtb.hits 159828196 # DTB hits +system.cpu0.dtb.misses 133030 # DTB misses +system.cpu0.dtb.accesses 159961226 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -493,555 +490,555 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 76645 # Table walker walks requested -system.cpu0.itb.walker.walksLong 76645 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4248 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67077 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 76645 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 76645 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 76645 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 71325 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28947.290571 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25637.754479 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19237.260354 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70555 98.92% 98.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 2 0.00% 98.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 668 0.94% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 18 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 42 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 71325 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 1705681704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1705681704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67077 94.04% 94.04% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4248 5.96% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 71325 # Table walker page sizes translated +system.cpu0.itb.walker.walks 78025 # Table walker walks requested +system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67964 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 78025 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 78025 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78025 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72373 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28767.572161 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25800.961773 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 15890.832899 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 71328 98.56% 98.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 906 1.25% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 58 0.08% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 43 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72373 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294749296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294749296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294749296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 67964 93.91% 93.91% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4409 6.09% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72373 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 76645 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 76645 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78025 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78025 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71325 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71325 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 147970 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 417906874 # ITB inst hits -system.cpu0.itb.inst_misses 76645 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72373 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 150398 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 446488504 # ITB inst hits +system.cpu0.itb.inst_misses 78025 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51806 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 19521 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 503 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 51690 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53811 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 417983519 # ITB inst accesses -system.cpu0.itb.hits 417906874 # DTB hits -system.cpu0.itb.misses 76645 # DTB misses -system.cpu0.itb.accesses 417983519 # DTB accesses -system.cpu0.numCycles 51800067955 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 446566529 # ITB inst accesses +system.cpu0.itb.hits 446488504 # DTB hits +system.cpu0.itb.misses 78025 # DTB misses +system.cpu0.itb.accesses 446566529 # DTB accesses +system.cpu0.numCycles 51821574278 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16018 # number of quiesce instructions executed -system.cpu0.committedInsts 417645333 # Number of instructions committed -system.cpu0.committedOps 490761503 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 451046619 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 435772 # Number of float alu accesses -system.cpu0.num_func_calls 25047272 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 63386661 # number of instructions that are conditional controls -system.cpu0.num_int_insts 451046619 # number of integer instructions -system.cpu0.num_fp_insts 435772 # number of float instructions -system.cpu0.num_int_register_reads 653989680 # number of times the integer registers were read -system.cpu0.num_int_register_writes 357583746 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 703407 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 366712 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 108509856 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 108205607 # number of times the CC registers were written -system.cpu0.num_mem_refs 149883436 # number of memory refs -system.cpu0.num_load_insts 78604497 # Number of load instructions -system.cpu0.num_store_insts 71278939 # Number of store instructions -system.cpu0.num_idle_cycles 50264779959.264511 # Number of idle cycles -system.cpu0.num_busy_cycles 1535287995.735491 # Number of busy cycles -system.cpu0.not_idle_fraction 0.029639 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.970361 # Percentage of idle cycles -system.cpu0.Branches 93191056 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16348 # number of quiesce instructions executed +system.cpu0.committedInsts 446216062 # Number of instructions committed +system.cpu0.committedOps 524400051 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 481388306 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 440832 # Number of float alu accesses +system.cpu0.num_func_calls 26357525 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68205669 # number of instructions that are conditional controls +system.cpu0.num_int_insts 481388306 # number of integer instructions +system.cpu0.num_fp_insts 440832 # number of float instructions +system.cpu0.num_int_register_reads 703333504 # number of times the integer registers were read +system.cpu0.num_int_register_writes 381971540 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 708271 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 380080 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117540708 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117236412 # number of times the CC registers were written +system.cpu0.num_mem_refs 159819450 # number of memory refs +system.cpu0.num_load_insts 83525533 # Number of load instructions +system.cpu0.num_store_insts 76293917 # Number of store instructions +system.cpu0.num_idle_cycles 50236144373.803871 # Number of idle cycles +system.cpu0.num_busy_cycles 1585429904.196130 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030594 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969406 # Percentage of idle cycles +system.cpu0.Branches 99643757 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 339970284 69.23% 69.23% # Class of executed instruction -system.cpu0.op_class::IntMult 1088528 0.22% 69.46% # Class of executed instruction -system.cpu0.op_class::IntDiv 48838 0.01% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 4 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 11 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 16 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 53987 0.01% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu0.op_class::MemRead 78604497 16.01% 85.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 71278939 14.52% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 363667031 69.31% 69.31% # Class of executed instruction +system.cpu0.op_class::IntMult 1107197 0.21% 69.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 49205 0.01% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55532 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::MemRead 83525533 15.92% 85.46% # Class of executed instruction +system.cpu0.op_class::MemWrite 76293917 14.54% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 491045105 # Class of executed instruction -system.cpu0.dcache.tags.replacements 9348690 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.942765 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 290545917 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9349202 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.077082 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 5830459500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 239.060392 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 272.882373 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466915 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.532973 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999888 # Average percentage of cache occupancy +system.cpu0.op_class::total 524698416 # Class of executed instruction +system.cpu0.dcache.tags.replacements 10234473 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10234985 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.294589 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3504381500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 238.684462 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 273.281191 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466181 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.533752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1209380446 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1209380446 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73565050 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 73675214 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 147240264 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 67654945 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67959241 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135614186 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188452 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 185421 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 373873 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 174201 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 157964 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 332165 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1663387 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1666647 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3330034 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1801503 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1811825 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3613328 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 141394196 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 141792419 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 283186615 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 141582648 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 141977840 # number of overall hits -system.cpu0.dcache.overall_hits::total 283560488 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2455322 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2424347 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 4879669 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1010929 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 979195 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1990124 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579794 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 548628 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1128422 # number of SoftPFReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu0.data 615937 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::cpu1.data 604869 # number of WriteLineReq misses -system.cpu0.dcache.WriteLineReq_misses::total 1220806 # number of WriteLineReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 138893 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 146035 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 284928 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72354151 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 72480719 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 144834870 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 212404128000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3180599500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3018965000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6199564500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3180599500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3018965000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6199564500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032157 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031714 # 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number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 39571050000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 78577127000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32849881500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31814880500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 64664762000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10562457500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10483200000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21045657500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 12173685500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11859131500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24032817000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1545963000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623615500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3169578500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 143000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 82000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 225000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 84029644000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83245062000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 167274706000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94592101500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93728262000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 188320363500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3122320000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3110634500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232954500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3122320000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3110634500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232954500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032439 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032923 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032683 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015148 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014815 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014981 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770234 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765295 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767784 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789986 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781729 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785875 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057648 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059302 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027919 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.027339 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.027629 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031731 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.030940 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031335 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16118.940424 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15946.282062 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16033.164972 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32918.787684 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34477.794942 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33685.100619 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18503.015914 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19184.461278 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18834.300950 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 38122.623742 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38839.284209 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 38477.705303 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13901.900698 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13638.545843 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13765.684553 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 79000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 81000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23596.535610 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23919.459166 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23756.481717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22961.095144 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23347.429092 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23152.014437 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185555.072633 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182271.629536 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183941.505459 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89946.537145 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 94189.598153 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91963.931289 # average overall mshr uncacheable latency -system.cpu0.icache.tags.replacements 13311280 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.820918 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 822940675 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13311792 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 61.820428 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 49369795500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 242.457113 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 269.363804 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.473549 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.526101 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999650 # Average percentage of cache occupancy +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028124 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028106 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032188 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032109 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032148 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14911.206893 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14755.555373 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14832.413274 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29514.028873 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29185.366532 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29351.407979 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15932.966629 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16174.907231 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.569856 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19572.628321 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19431.069541 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19502.518476 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13333.819204 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13426.410148 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.088783 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 47666.666667 # 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Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 232.219683 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 279.671389 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.453554 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.546233 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 849564269 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 849564269 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 411229460 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 411711215 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 822940675 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 411229460 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 411711215 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 822940675 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 411229460 # 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number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 17201 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 84606442500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 84117530000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 168723972500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 84606442500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 84117530000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 168723972500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 84606442500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 84117530000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 168723972500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 5436799500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2780591500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 2656208000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 5436799500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015918 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015918 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015978 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015859 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015918 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12674.770544 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12670.540197 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12679.028329 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12674.770544 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 126070.713043 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 126035.332245 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126107.771922 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 126070.713043 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 85279523000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 86108596000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 171388119000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 85279523000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 86108596000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 171388119000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 85279523000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 86108596000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 171388119000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3263480000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3263480000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015409 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015409 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015409 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12432.231409 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1071,68 +1068,73 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 116402 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 116402 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17438 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84735 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 8 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 116394 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.103098 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 35.173529 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 116393 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 116394 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 102181 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25297.388947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 21878.077952 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 16308.937968 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 101549 99.38% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.00% 99.38% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 548 0.54% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 11 0.01% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 41 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 2 0.00% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 102181 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 344855740 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean -3.415840 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1522827704 441.58% 441.58% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1177971964 -341.58% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 344855740 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 84735 82.93% 82.93% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17438 17.07% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 102173 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 116402 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 133445 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 96452 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 133432 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.299778 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 83.395537 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 133430 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 133432 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 117373 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25894.485955 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22861.122715 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13849.356083 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 74140 63.17% 63.17% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 42199 35.95% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 555 0.47% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 343 0.29% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 6 0.01% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 29 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 23 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 117373 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 6007861436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.129422 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -777548296 -12.94% -12.94% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 6785409732 112.94% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 6007861436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 96452 82.18% 82.18% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20908 17.82% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 117360 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 133445 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 116402 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102173 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 133445 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 117360 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102173 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 218575 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 117360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 250805 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 78662844 # DTB read hits -system.cpu1.dtb.read_misses 89684 # DTB read misses -system.cpu1.dtb.write_hits 71537174 # DTB write hits -system.cpu1.dtb.write_misses 26718 # DTB write misses -system.cpu1.dtb.flush_tlb 51800 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 84301684 # DTB read hits +system.cpu1.dtb.read_misses 101780 # DTB read misses +system.cpu1.dtb.write_hits 76371214 # DTB write hits +system.cpu1.dtb.write_misses 31665 # DTB write misses +system.cpu1.dtb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 67247 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 74029 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 3767 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9113 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 78752528 # DTB read accesses -system.cpu1.dtb.write_accesses 71563892 # DTB write accesses +system.cpu1.dtb.perms_faults 10027 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84403464 # DTB read accesses +system.cpu1.dtb.write_accesses 76402879 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 150200018 # DTB hits -system.cpu1.dtb.misses 116402 # DTB misses -system.cpu1.dtb.accesses 150316420 # DTB accesses +system.cpu1.dtb.hits 160672898 # DTB hits +system.cpu1.dtb.misses 133445 # DTB misses +system.cpu1.dtb.accesses 160806343 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1162,127 +1164,131 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 74223 # Table walker walks requested -system.cpu1.itb.walker.walksLong 74223 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4163 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 64958 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 74223 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 74223 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 74223 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 69121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28935.417601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25541.870805 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19930.697059 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 68364 98.90% 98.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 4 0.01% 98.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 655 0.95% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 17 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 38 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 69121 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1449734704 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1449734704 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 64958 93.98% 93.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4163 6.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 69121 # Table walker page sizes translated +system.cpu1.itb.walker.walks 78111 # Table walker walks requested +system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68231 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 78111 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 78111 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 78111 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 72561 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 28942.620692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 25930.573552 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16143.079615 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 35934 49.52% 49.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 35483 48.90% 98.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 386 0.53% 98.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 612 0.84% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 10 0.01% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 47 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 72561 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -850152296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -850152296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -850152296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 68231 94.03% 94.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4330 5.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 72561 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 74223 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 74223 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78111 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 69121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 69121 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 143344 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 418345598 # ITB inst hits -system.cpu1.itb.inst_misses 74223 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72561 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72561 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 150672 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 448183312 # ITB inst hits +system.cpu1.itb.inst_misses 78111 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51800 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 18845 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 504 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 49961 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53985 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 418419821 # ITB inst accesses -system.cpu1.itb.hits 418345598 # DTB hits -system.cpu1.itb.misses 74223 # DTB misses -system.cpu1.itb.accesses 418419821 # DTB accesses -system.cpu1.numCycles 51798396348 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 448261423 # ITB inst accesses +system.cpu1.itb.hits 448183312 # DTB hits +system.cpu1.itb.misses 78111 # DTB misses +system.cpu1.itb.accesses 448261423 # DTB accesses +system.cpu1.numCycles 51820425457 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 418091469 # Number of instructions committed -system.cpu1.committedOps 491344077 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 451749452 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 464131 # Number of float alu accesses -system.cpu1.num_func_calls 25120971 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 63413635 # number of instructions that are conditional controls -system.cpu1.num_int_insts 451749452 # number of integer instructions -system.cpu1.num_fp_insts 464131 # number of float instructions -system.cpu1.num_int_register_reads 653305653 # number of times the integer registers were read -system.cpu1.num_int_register_writes 357922313 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 749406 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 392664 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 108141039 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 107840924 # number of times the CC registers were written -system.cpu1.num_mem_refs 150187574 # number of memory refs -system.cpu1.num_load_insts 78657446 # Number of load instructions -system.cpu1.num_store_insts 71530128 # Number of store instructions -system.cpu1.num_idle_cycles 50264307367.295029 # Number of idle cycles -system.cpu1.num_busy_cycles 1534088980.704967 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029617 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970383 # Percentage of idle cycles -system.cpu1.Branches 93317418 # Number of branches fetched +system.cpu1.committedInsts 447903186 # Number of instructions committed +system.cpu1.committedOps 526302841 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 483164392 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 453837 # Number of float alu accesses +system.cpu1.num_func_calls 26485275 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68482317 # number of instructions that are conditional controls +system.cpu1.num_int_insts 483164392 # number of integer instructions +system.cpu1.num_fp_insts 453837 # number of float instructions +system.cpu1.num_int_register_reads 704985819 # number of times the integer registers were read +system.cpu1.num_int_register_writes 383399771 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 733419 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 379508 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 118000089 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117710485 # number of times the CC registers were written +system.cpu1.num_mem_refs 160666503 # number of memory refs +system.cpu1.num_load_insts 84298667 # Number of load instructions +system.cpu1.num_store_insts 76367836 # Number of store instructions +system.cpu1.num_idle_cycles 50233099437.419525 # Number of idle cycles +system.cpu1.num_busy_cycles 1587326019.580469 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030631 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969369 # Percentage of idle cycles +system.cpu1.Branches 100046269 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 340283943 69.22% 69.22% # Class of executed instruction -system.cpu1.op_class::IntMult 1041145 0.21% 69.43% # Class of executed instruction -system.cpu1.op_class::IntDiv 48269 0.01% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 4 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 2 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 5 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 58327 0.01% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.45% # Class of executed instruction -system.cpu1.op_class::MemRead 78657446 16.00% 85.45% # Class of executed instruction -system.cpu1.op_class::MemWrite 71530128 14.55% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364713411 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 1116791 0.21% 69.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 48530 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54891 0.01% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::MemRead 84298667 16.01% 85.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 76367836 14.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 491619269 # Class of executed instruction -system.iobus.trans_dist::ReadReq 40338 # Transaction distribution -system.iobus.trans_dist::ReadResp 40338 # Transaction distribution +system.cpu1.op_class::total 526600168 # Class of executed instruction +system.iobus.trans_dist::ReadReq 40318 # Transaction distribution +system.iobus.trans_dist::ReadResp 40318 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1299,11 +1305,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231034 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230994 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230994 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353778 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1318,14 +1324,14 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334568 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334408 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492488 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42145500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42147500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1335,9 +1341,9 @@ system.iobus.reqLayer4.occupancy 11000 # La system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1345,73 +1351,73 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25719500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25749000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38601500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38609000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 566847151 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568885533 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147794000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147754000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115499 # number of replacements -system.iocache.tags.tagsinuse 10.451110 # Cycle average of tags in use +system.iocache.tags.replacements 115478 # number of replacements +system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115515 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115494 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13171691140000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.508460 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.942650 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219279 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433916 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653194 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13153888090000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.511180 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946135 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219449 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434133 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040010 # Number of tag accesses -system.iocache.tags.data_accesses 1040010 # Number of data accesses +system.iocache.tags.tag_accesses 1039830 # Number of tag accesses +system.iocache.tags.data_accesses 1039830 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8853 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8890 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8833 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8870 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115517 # number of demand (read+write) misses -system.iocache.demand_misses::total 115557 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115497 # number of demand (read+write) misses +system.iocache.demand_misses::total 115537 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115517 # number of overall misses -system.iocache.overall_misses::total 115557 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5070500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1618419141 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1623489641 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115497 # number of overall misses +system.iocache.overall_misses::total 115537 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1609929768 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1615016268 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 13411968510 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 13411968510 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5421500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 15030387651 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 15035809151 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5421500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 15030387651 # number of overall miss cycles -system.iocache.overall_miss_latency::total 15035809151 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12771447265 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12771447265 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14381377033 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14386814533 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14381377033 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14386814533 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8853 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8890 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8833 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8870 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115517 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115557 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115497 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115537 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115517 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115557 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115497 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115537 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1425,53 +1431,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137040.540541 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182810.249746 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182619.757143 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182263.078003 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182076.242165 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125740.348290 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125740.348290 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130114.075426 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130115.952742 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135537.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130114.075426 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130115.952742 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31642 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119735.311492 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119735.311492 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124521.274856 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124521.274856 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31700 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3353 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3352 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.436922 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.457041 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8853 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8890 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8833 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115517 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115557 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115497 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115537 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115517 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115557 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3220500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1175769141 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1178989641 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115497 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115537 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1168279768 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1171516268 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8073599158 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 8073599158 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3421500 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 9249368299 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 9252789799 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3421500 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 9249368299 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 9252789799 # number of overall MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7431457785 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 7431457785 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8599737553 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8603175053 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8599737553 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8603175053 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1485,564 +1491,571 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87040.540541 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132810.249746 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 132619.757143 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132263.078003 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132076.242165 # average ReadReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75691.884403 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75691.884403 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80069.325718 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80071.218524 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85537.500000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80069.325718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80071.218524 # average overall mshr miss latency -system.l2c.tags.replacements 1026360 # number of replacements -system.l2c.tags.tagsinuse 65258.201118 # Cycle average of tags in use -system.l2c.tags.total_refs 41749797 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1088957 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 38.339252 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 12386120500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37949.534950 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 104.286779 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 159.329733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4753.488207 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9126.220322 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 118.614839 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 183.809686 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3411.314898 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9451.601704 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.579064 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001591 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002431 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.072532 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.139255 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001810 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002805 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.052053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.144220 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995761 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62377 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54048 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.951797 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 372663502 # Number of tag accesses -system.l2c.tags.data_accesses 372663502 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 212373 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 162936 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 207984 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 157286 # number of ReadReq hits -system.l2c.ReadReq_hits::total 740579 # number of ReadReq hits -system.l2c.WritebackDirty_hits::writebacks 7311510 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 7311510 # number of WritebackDirty hits -system.l2c.WritebackClean_hits::writebacks 13309724 # number of WritebackClean hits -system.l2c.WritebackClean_hits::total 13309724 # number of WritebackClean hits -system.l2c.UpgradeReq_hits::cpu0.data 4522 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4435 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 8957 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 815767 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 776062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1591829 # number of ReadExReq hits -system.l2c.ReadCleanReq_hits::cpu0.inst 6641663 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 6598566 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 13240229 # number of ReadCleanReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 3014297 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 2962809 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 5977106 # number of ReadSharedReq hits -system.l2c.InvalidateReq_hits::cpu0.data 376322 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::cpu1.data 363170 # number of InvalidateReq hits -system.l2c.InvalidateReq_hits::total 739492 # number of InvalidateReq hits -system.l2c.demand_hits::cpu0.dtb.walker 212373 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 162936 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6641663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3830064 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 207984 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 157286 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6598566 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3738871 # number of demand (read+write) hits -system.l2c.demand_hits::total 21549743 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 212373 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 162936 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6641663 # number of overall hits -system.l2c.overall_hits::cpu0.data 3830064 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 207984 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 157286 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6598566 # number of overall hits -system.l2c.overall_hits::cpu1.data 3738871 # number of overall hits -system.l2c.overall_hits::total 21549743 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1170 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1257 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1193 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1217 # number of ReadReq misses -system.l2c.ReadReq_misses::total 4837 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 16637 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16471 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 33108 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69671.658526 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69671.658526 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74458.536178 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74462.510304 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74458.536178 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74462.510304 # average overall mshr miss latency +system.l2c.tags.replacements 1307385 # number of replacements +system.l2c.tags.tagsinuse 65260.397522 # Cycle average of tags in use +system.l2c.tags.total_refs 44030779 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1370457 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 32.128537 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 6646395500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38500.682373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 145.371302 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 226.787619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3397.197981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9485.761310 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 150.823098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 211.566669 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2947.507944 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10194.699226 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.587474 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002218 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.144741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002301 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003228 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.044975 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.155559 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995795 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 284 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62788 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2444 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5467 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54432 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.958069 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 395683924 # Number of tag accesses +system.l2c.tags.data_accesses 395683924 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 246270 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 166121 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 249681 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 166863 # number of ReadReq hits +system.l2c.ReadReq_hits::total 828935 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 7894898 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 7894898 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 13783694 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 13783694 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 4999 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5005 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10004 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 822661 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 809558 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1632219 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6820625 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 6886530 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 13707155 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3255016 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3312365 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6567381 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 362783 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 360629 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 723412 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 246270 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 166121 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6820625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4077677 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 249681 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 166863 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6886530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4121923 # number of demand (read+write) hits +system.l2c.demand_hits::total 22735690 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 246270 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 166121 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6820625 # number of overall hits +system.l2c.overall_hits::cpu0.data 4077677 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 249681 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 166863 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6886530 # number of overall hits +system.l2c.overall_hits::cpu1.data 4121923 # number of overall hits +system.l2c.overall_hits::total 22735690 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1919 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1974 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2347 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2061 # number of ReadReq misses +system.l2c.ReadReq_misses::total 8301 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17868 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18114 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35982 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 164166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 170807 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 334973 # number of ReadExReq misses -system.l2c.ReadCleanReq_misses::cpu0.inst 35751 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 35817 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 71568 # number of ReadCleanReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 113964 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 110564 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 224528 # number of ReadSharedReq misses -system.l2c.InvalidateReq_misses::cpu0.data 239615 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::cpu1.data 241699 # number of InvalidateReq misses -system.l2c.InvalidateReq_misses::total 481314 # number of InvalidateReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1170 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1257 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 35751 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 278130 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1193 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1217 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 35817 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 281371 # number of demand (read+write) misses -system.l2c.demand_misses::total 635906 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1170 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1257 # number of overall misses -system.l2c.overall_misses::cpu0.inst 35751 # number of overall misses -system.l2c.overall_misses::cpu0.data 278130 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1193 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1217 # number of overall misses -system.l2c.overall_misses::cpu1.inst 35817 # number of overall misses -system.l2c.overall_misses::cpu1.data 281371 # number of overall misses -system.l2c.overall_misses::total 635906 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 158334000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 173858500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 161742000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 169455500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 663390000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 664049000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 658035500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 1322084500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 77500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 157000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 21519096500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 22411791000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 43930887500 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 4720674000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 4748397000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 9469071000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 15191781000 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 14765909500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 29957690500 # number of ReadSharedReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu0.data 155000 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::cpu1.data 387500 # number of InvalidateReq miss cycles -system.l2c.InvalidateReq_miss_latency::total 542500 # number of InvalidateReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 158334000 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121991.405875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 125575.859179 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 129240.345111 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122573.833654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122130.138582 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 122127.735764 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173032.961904 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 169747.690636 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138947.871247 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113535.332245 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83876.530641 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 113607.771922 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 87717.802321 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 96575.168720 # average overall mshr uncacheable latency -system.membus.trans_dist::ReadReq 76829 # Transaction distribution -system.membus.trans_dist::ReadResp 386652 # Transaction distribution -system.membus.trans_dist::WriteReq 33709 # Transaction distribution -system.membus.trans_dist::WriteResp 33709 # Transaction distribution -system.membus.trans_dist::WritebackDirty 978778 # Transaction distribution -system.membus.trans_dist::CleanEvict 162070 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33685 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7 # Transaction distribution -system.membus.trans_dist::ReadExReq 334406 # Transaction distribution -system.membus.trans_dist::ReadExResp 334406 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 309823 # Transaction distribution -system.membus.trans_dist::InvalidateReq 587971 # Transaction distribution +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.245375 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241261 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.243340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005704 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041166 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040639 # mshr miss rate for ReadSharedReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.416724 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.409113 # mshr miss rate for InvalidateReq accesses +system.l2c.InvalidateReq_mshr_miss_rate::total 0.412955 # mshr miss rate for InvalidateReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011743 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.090803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009312 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012201 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.087625 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.037673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011743 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009312 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012201 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.087625 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.037673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76900.975786 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18924.669801 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18923.291377 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18923.975877 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 36166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44750 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72050.491966 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71881.386450 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71967.562553 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72781.640257 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74479.073353 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74378.277580 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74428.910610 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18671.781922 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18663.857839 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18667.893869 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173784.623188 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171027.320470 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.538572 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91362.585482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81557.769149 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.649234 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2972233 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1487104 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.trans_dist::ReadReq 76831 # Transaction distribution +system.membus.trans_dist::ReadResp 450834 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1228413 # Transaction distribution +system.membus.trans_dist::CleanEvict 193324 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36554 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::UpgradeResp 8 # Transaction distribution +system.membus.trans_dist::ReadExReq 524356 # Transaction distribution +system.membus.trans_dist::ReadExResp 524356 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 374003 # Transaction distribution +system.membus.trans_dist::InvalidateReq 615538 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6936 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2901743 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3031441 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237241 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 3268682 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3851094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4088476 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 96630432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 96800270 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7220224 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 104020494 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3365 # Total snoops (count) -system.membus.snoop_fanout::samples 2517308 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128872672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129042522 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7231808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7231808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 136274330 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3165 # Total snoops (count) +system.membus.snoop_fanout::samples 1660996 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019349 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.137749 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2517308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1628857 98.07% 98.07% # Request fanout histogram +system.membus.snoop_fanout::1 32139 1.93% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2517308 # Request fanout histogram -system.membus.reqLayer0.occupancy 106894000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1660996 # Request fanout histogram +system.membus.reqLayer0.occupancy 106934500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5659000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5678000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6490935886 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8069625955 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3578419285 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4926078787 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44788681 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2096,61 +2109,61 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 45897959 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 23236926 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2692 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2692 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 1189053 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 20703336 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33709 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33709 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 8290323 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13311280 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2200261 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 42068 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 42070 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1926802 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1926802 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13311797 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6210524 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1327470 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1220806 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 40021124 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28266989 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 766613 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1091027 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 70145753 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1704049428 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 988401530 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2581568 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3381760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2698414286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1625114 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 25183319 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021416 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.144767 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 9016681 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13785272 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2525177 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45989 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45993 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2157137 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2157137 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13785789 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6848293 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1261037 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1232293 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41443100 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30932231 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796412 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1256395 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 74428138 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764720404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081696966 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2696152 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 4001736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2853115258 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1718109 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 26731746 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021922 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146427 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 24643989 97.86% 97.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 539330 2.14% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 26145745 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 586001 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 25183319 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 43932563500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 26731746 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 46403347500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1579898 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1695386 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20010820500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20721808500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12874657982 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14193795462 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 443917000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 459393000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 668307000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 756178000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |