diff options
author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
---|---|---|
committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | |
parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | 3320 |
1 files changed, 1659 insertions, 1661 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index e35d19105..3836d4f0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,161 +1,161 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821000 # Number of seconds simulated -sim_ticks 51820999867500 # Number of ticks simulated -final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.820975 # Number of seconds simulated +sim_ticks 51820974875500 # Number of ticks simulated +final_tick 51820974875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 622691 # Simulator instruction rate (inst/s) -host_op_rate 731741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36089691928 # Simulator tick rate (ticks/s) -host_mem_usage 680680 # Number of bytes of host memory used -host_seconds 1435.89 # Real time elapsed on the host -sim_insts 894119248 # Number of instructions simulated -sim_ops 1050702892 # Number of ops (including micro ops) simulated +host_inst_rate 496355 # Simulator instruction rate (inst/s) +host_op_rate 583273 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28752228320 # Simulator tick rate (ticks/s) +host_mem_usage 675168 # Number of bytes of host memory used +host_seconds 1802.33 # Real time elapsed on the host +sim_insts 894595581 # Number of instructions simulated +sim_ops 1051249500 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 26029680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 150208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 131904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2604676 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 25292888 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 407488 # Number of bytes read from this memory -system.physmem.bytes_read::total 57465468 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2599472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2604676 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5204148 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78618432 # Number of bytes written to this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 122624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2604528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25895856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 149760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2570820 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 25432280 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 409472 # Number of bytes read from this memory +system.physmem.bytes_read::total 57443708 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2604528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2570820 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5175348 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 78747648 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 78639012 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1919 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 64898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 406717 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2061 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56824 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 395211 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6367 # Number of read requests responded to by this memory -system.physmem.num_reads::total 938318 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1228413 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 78768228 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64977 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 404626 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 397389 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6398 # Number of read requests responded to by this memory +system.physmem.num_reads::total 937978 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1230432 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1230986 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 50163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 502300 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50263 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 488082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1108922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 50163 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50263 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 100425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1517115 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1233005 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 50260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 499718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2890 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 490772 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7902 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1108503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 50260 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 99870 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1519610 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1517512 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1517115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 50163 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 502300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2545 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 488479 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7863 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2626435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 938318 # Number of read requests accepted -system.physmem.writeReqs 1230986 # Number of write requests accepted -system.physmem.readBursts 938318 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1230986 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 60016640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35712 # Total number of bytes read from write queue -system.physmem.bytesWritten 78638272 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 57465468 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 78639012 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 558 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2260 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_write::total 1520007 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1519610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 50260 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 499718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 491169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2628510 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 937978 # Number of read requests accepted +system.physmem.writeReqs 1233005 # Number of write requests accepted +system.physmem.readBursts 937978 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1233005 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59999232 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31360 # Total number of bytes read from write queue +system.physmem.bytesWritten 78767552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 57443708 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 78768228 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 490 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2262 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 57802 # Per bank write bursts -system.physmem.perBankRdBursts::1 61444 # Per bank write bursts -system.physmem.perBankRdBursts::2 58618 # Per bank write bursts -system.physmem.perBankRdBursts::3 56911 # Per bank write bursts -system.physmem.perBankRdBursts::4 53280 # Per bank write bursts -system.physmem.perBankRdBursts::5 57178 # Per bank write bursts -system.physmem.perBankRdBursts::6 52016 # Per bank write bursts -system.physmem.perBankRdBursts::7 52831 # Per bank write bursts -system.physmem.perBankRdBursts::8 55081 # Per bank write bursts -system.physmem.perBankRdBursts::9 100686 # Per bank write bursts -system.physmem.perBankRdBursts::10 57898 # Per bank write bursts -system.physmem.perBankRdBursts::11 58894 # Per bank write bursts -system.physmem.perBankRdBursts::12 52465 # Per bank write bursts -system.physmem.perBankRdBursts::13 56002 # Per bank write bursts -system.physmem.perBankRdBursts::14 52925 # Per bank write bursts -system.physmem.perBankRdBursts::15 53729 # Per bank write bursts -system.physmem.perBankWrBursts::0 76591 # Per bank write bursts -system.physmem.perBankWrBursts::1 80097 # Per bank write bursts -system.physmem.perBankWrBursts::2 79619 # Per bank write bursts -system.physmem.perBankWrBursts::3 80251 # Per bank write bursts -system.physmem.perBankWrBursts::4 74804 # Per bank write bursts -system.physmem.perBankWrBursts::5 78970 # Per bank write bursts -system.physmem.perBankWrBursts::6 72699 # Per bank write bursts -system.physmem.perBankWrBursts::7 74032 # Per bank write bursts -system.physmem.perBankWrBursts::8 75192 # Per bank write bursts -system.physmem.perBankWrBursts::9 79224 # Per bank write bursts -system.physmem.perBankWrBursts::10 76715 # Per bank write bursts -system.physmem.perBankWrBursts::11 78463 # Per bank write bursts -system.physmem.perBankWrBursts::12 72476 # Per bank write bursts -system.physmem.perBankWrBursts::13 78380 # Per bank write bursts -system.physmem.perBankWrBursts::14 75126 # Per bank write bursts -system.physmem.perBankWrBursts::15 76084 # Per bank write bursts +system.physmem.perBankRdBursts::0 55925 # Per bank write bursts +system.physmem.perBankRdBursts::1 62794 # Per bank write bursts +system.physmem.perBankRdBursts::2 56907 # Per bank write bursts +system.physmem.perBankRdBursts::3 56516 # Per bank write bursts +system.physmem.perBankRdBursts::4 54249 # Per bank write bursts +system.physmem.perBankRdBursts::5 59650 # Per bank write bursts +system.physmem.perBankRdBursts::6 52080 # Per bank write bursts +system.physmem.perBankRdBursts::7 52710 # Per bank write bursts +system.physmem.perBankRdBursts::8 54230 # Per bank write bursts +system.physmem.perBankRdBursts::9 101225 # Per bank write bursts +system.physmem.perBankRdBursts::10 56377 # Per bank write bursts +system.physmem.perBankRdBursts::11 58912 # Per bank write bursts +system.physmem.perBankRdBursts::12 52835 # Per bank write bursts +system.physmem.perBankRdBursts::13 56393 # Per bank write bursts +system.physmem.perBankRdBursts::14 52915 # Per bank write bursts +system.physmem.perBankRdBursts::15 53770 # Per bank write bursts +system.physmem.perBankWrBursts::0 75516 # Per bank write bursts +system.physmem.perBankWrBursts::1 81375 # Per bank write bursts +system.physmem.perBankWrBursts::2 78514 # Per bank write bursts +system.physmem.perBankWrBursts::3 79379 # Per bank write bursts +system.physmem.perBankWrBursts::4 75747 # Per bank write bursts +system.physmem.perBankWrBursts::5 80437 # Per bank write bursts +system.physmem.perBankWrBursts::6 73343 # Per bank write bursts +system.physmem.perBankWrBursts::7 74340 # Per bank write bursts +system.physmem.perBankWrBursts::8 74711 # Per bank write bursts +system.physmem.perBankWrBursts::9 79754 # Per bank write bursts +system.physmem.perBankWrBursts::10 76052 # Per bank write bursts +system.physmem.perBankWrBursts::11 78875 # Per bank write bursts +system.physmem.perBankWrBursts::12 73771 # Per bank write bursts +system.physmem.perBankWrBursts::13 78567 # Per bank write bursts +system.physmem.perBankWrBursts::14 74862 # Per bank write bursts +system.physmem.perBankWrBursts::15 75500 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 41 # Number of times write queue was full causing retry -system.physmem.totGap 51820996946500 # Total gap between requests +system.physmem.numWrRetry 33 # Number of times write queue was full causing retry +system.physmem.totGap 51820971954500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 895202 # Read request sizes (log2) +system.physmem.readPktSize::6 894862 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1228413 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 903707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 324 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 501 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 483 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 76 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1230432 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 903465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 1195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 317 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 117 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -166,148 +166,149 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1523 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 33745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 39129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 33891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 39270 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 66568 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 69544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 72891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 70544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 68952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 71209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 73943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 70814 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 76250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 74490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 70684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 68944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 68807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 66563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 66004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 65153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 136 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563401 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 246.102850 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 148.051526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 287.279361 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 250361 44.44% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 146586 26.02% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50209 8.91% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 27045 4.80% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 18004 3.20% 87.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12090 2.15% 89.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8995 1.60% 91.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7664 1.36% 92.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 42447 7.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563401 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 65697 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.273848 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 106.818256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 65693 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::18 69647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 73027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 70654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 69180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 71444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 74057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 71008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 76504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 74752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 70724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 69059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 69030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 66768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 66112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 65180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 564009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 246.035904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 148.070971 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 287.068931 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 250512 44.42% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 146974 26.06% 70.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49960 8.86% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27236 4.83% 84.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 18139 3.22% 87.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12170 2.16% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8948 1.59% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7660 1.36% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 42410 7.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 564009 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 65824 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.242267 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 106.817618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 65819 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 65697 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 65697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.702878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.053855 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 6.999985 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 137 0.21% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 78 0.12% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 60 0.09% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 99 0.15% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 51857 78.93% 79.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 9705 14.77% 94.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 1082 1.65% 95.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 596 0.91% 96.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 852 1.30% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 335 0.51% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 83 0.13% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.05% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 55 0.08% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 34 0.05% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 40 0.06% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 30 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 421 0.64% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 37 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 32 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.05% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 21 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 5 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 65824 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 65824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.697481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.054439 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 6.954009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 139 0.21% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 76 0.12% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 52 0.08% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 125 0.19% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 51932 78.90% 79.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 9755 14.82% 94.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1068 1.62% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 579 0.88% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 868 1.32% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 349 0.53% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 83 0.13% 98.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 31 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 49 0.07% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 50 0.08% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 24 0.04% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 26 0.04% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 422 0.64% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 35 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 36 0.05% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 31 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 4 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 5 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.00% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.00% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 17 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 8 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 16 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 12 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 65697 # Writes before turning the bus around for reads -system.physmem.totQLat 12237400086 # Total ticks spent queuing -system.physmem.totMemAccLat 29820400086 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4688800000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13049.61 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 65824 # Writes before turning the bus around for reads +system.physmem.totQLat 12248455604 # Total ticks spent queuing +system.physmem.totMemAccLat 29826355604 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4687440000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13065.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31799.61 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31815.19 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s @@ -317,42 +318,42 @@ system.physmem.busUtil 0.02 # Da system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.91 # Average write queue length when enqueuing -system.physmem.readRowHits 705929 # Number of row buffer hits during reads -system.physmem.writeRowHits 897152 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.28 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.01 # Row buffer hit rate for writes -system.physmem.avgGap 23888305.63 # Average gap between requests +system.physmem.avgWrQLen 9.53 # Average write queue length when enqueuing +system.physmem.readRowHits 705562 # Number of row buffer hits during reads +system.physmem.writeRowHits 898659 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes +system.physmem.avgGap 23869819.32 # Average gap between requests system.physmem.pageHitRate 73.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2146397400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1171149375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3510585000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3998568240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1301998363920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29950494857250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34648015573185 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.609580 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49824747021214 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730417000000 # Time in different power states +system.physmem_0.actEnergy 2151787680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1174090500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3516442800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4008858480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1301405336775 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29951001041250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34647951683805 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.608648 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49825590774964 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730416220000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 265835434786 # Time in different power states +system.physmem_0.memoryStateTime::ACT 264967468786 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2112914160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1152879750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3803904000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3963556800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1301510416275 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29950922881500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34648162204485 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.612409 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49825423536265 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730417000000 # Time in different power states +system.physmem_1.actEnergy 2112120360 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1152446625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3795924600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3966356160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1300719308715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29951602820250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34648043103030 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.610412 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49826557272121 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730416220000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states +system.physmem_1.memoryStateTime::ACT 264000971629 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -369,9 +370,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -379,7 +380,7 @@ system.cf0.dma_write_full_pages 1666 # Nu system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -409,66 +410,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 133030 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95696 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 133019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 133019 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 133019 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 116836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 25679.131432 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 22619.213536 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13703.555245 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 115888 99.19% 99.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 821 0.70% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 61 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 31 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 134174 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 134174 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20899 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96911 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 134161 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 134161 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 134161 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 117823 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 25678.780883 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 22579.177668 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13711.855097 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 116916 99.23% 99.23% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.66% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 116836 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 9230012852 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.024648 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -227501296 -2.46% -2.46% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 9457514148 102.46% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 9230012852 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95697 81.91% 81.91% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 21129 18.09% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 116826 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 133030 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 117823 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 4912294556 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.048082 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -236192296 -4.81% -4.81% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 5148486852 104.81% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 4912294556 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 96912 82.26% 82.26% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 20899 17.74% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 117811 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 134174 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 133030 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116826 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 134174 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 117811 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116826 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 249856 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 117811 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 251985 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83528271 # DTB read hits -system.cpu0.dtb.read_misses 101098 # DTB read misses -system.cpu0.dtb.write_hits 76299925 # DTB write hits -system.cpu0.dtb.write_misses 31932 # DTB write misses +system.cpu0.dtb.read_hits 83610055 # DTB read hits +system.cpu0.dtb.read_misses 101997 # DTB read misses +system.cpu0.dtb.write_hits 76232981 # DTB write hits +system.cpu0.dtb.write_misses 32177 # DTB write misses system.cpu0.dtb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 73224 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 74001 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4744 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9926 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83629369 # DTB read accesses -system.cpu0.dtb.write_accesses 76331857 # DTB write accesses +system.cpu0.dtb.perms_faults 10268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83712052 # DTB read accesses +system.cpu0.dtb.write_accesses 76265158 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 159828196 # DTB hits -system.cpu0.dtb.misses 133030 # DTB misses -system.cpu0.dtb.accesses 159961226 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 159843036 # DTB hits +system.cpu0.dtb.misses 134174 # DTB misses +system.cpu0.dtb.accesses 159977210 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -498,68 +499,74 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 78025 # Table walker walks requested -system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67964 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 78025 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 78025 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 78025 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72373 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 28767.572161 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 25800.961773 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 15890.832899 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 71328 98.56% 98.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 906 1.25% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 58 0.08% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 43 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72373 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 79618 # Table walker walks requested +system.cpu0.itb.walker.walksLong 79618 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4423 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69406 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 79618 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 79618 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 79618 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 73829 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 28640.046594 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 25708.417232 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 15347.109309 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 36310 49.18% 49.18% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 36530 49.48% 98.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 322 0.44% 99.10% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 541 0.73% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 50 0.07% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 20 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 14 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 73829 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples -294749296 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 -294749296 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total -294749296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67964 93.91% 93.91% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4409 6.09% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 72373 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 69406 94.01% 94.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4423 5.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 73829 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78025 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78025 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79618 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79618 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72373 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72373 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 150398 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 446488504 # ITB inst hits -system.cpu0.itb.inst_misses 78025 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73829 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73829 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 153447 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 446783848 # ITB inst hits +system.cpu0.itb.inst_misses 79618 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51828 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 53747 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 55085 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 446566529 # ITB inst accesses -system.cpu0.itb.hits 446488504 # DTB hits -system.cpu0.itb.misses 78025 # DTB misses -system.cpu0.itb.accesses 446566529 # DTB accesses -system.cpu0.numPwrStateTransitions 16564 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 8282 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 6000025981.117725 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 124621883322.639465 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 3529 42.61% 42.61% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 4688 56.60% 99.22% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 446863466 # ITB inst accesses +system.cpu0.itb.hits 446783848 # DTB hits +system.cpu0.itb.misses 79618 # DTB misses +system.cpu0.itb.accesses 446863466 # DTB accesses +system.cpu0.numPwrStateTransitions 16584 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 8292 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 5987638231.190425 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 124545672847.091751 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 3540 42.69% 42.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 4687 56.52% 99.22% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.23% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 5 0.06% 99.29% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.54% 99.83% # Distribution of time spent in the clock gated state @@ -568,510 +575,510 @@ system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.86 system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 5700356796932 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 8282 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 2128784691883 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 49692215175617 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 51821574278 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 5700356716960 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 8292 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 2171478662469 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 49649496213031 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 51821531497 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16348 # number of quiesce instructions executed -system.cpu0.committedInsts 446216062 # Number of instructions committed -system.cpu0.committedOps 524400051 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 481388306 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 440832 # Number of float alu accesses -system.cpu0.num_func_calls 26357525 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68205669 # number of instructions that are conditional controls -system.cpu0.num_int_insts 481388306 # number of integer instructions -system.cpu0.num_fp_insts 440832 # number of float instructions -system.cpu0.num_int_register_reads 703333504 # number of times the integer registers were read -system.cpu0.num_int_register_writes 381971540 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 708271 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 380080 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117540708 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117236412 # number of times the CC registers were written -system.cpu0.num_mem_refs 159819450 # number of memory refs -system.cpu0.num_load_insts 83525533 # Number of load instructions -system.cpu0.num_store_insts 76293917 # Number of store instructions -system.cpu0.num_idle_cycles 50236144373.803871 # Number of idle cycles -system.cpu0.num_busy_cycles 1585429904.196130 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030594 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969406 # Percentage of idle cycles -system.cpu0.Branches 99643757 # Number of branches fetched +system.cpu0.kern.inst.quiesce 16350 # number of quiesce instructions executed +system.cpu0.committedInsts 446506838 # Number of instructions committed +system.cpu0.committedOps 524620955 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 481485743 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 439185 # Number of float alu accesses +system.cpu0.num_func_calls 26339620 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68267650 # number of instructions that are conditional controls +system.cpu0.num_int_insts 481485743 # number of integer instructions +system.cpu0.num_fp_insts 439185 # number of float instructions +system.cpu0.num_int_register_reads 703915697 # number of times the integer registers were read +system.cpu0.num_int_register_writes 382127275 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 705229 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 378788 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 117675600 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 117367653 # number of times the CC registers were written +system.cpu0.num_mem_refs 159834987 # number of memory refs +system.cpu0.num_load_insts 83607531 # Number of load instructions +system.cpu0.num_store_insts 76227456 # Number of store instructions +system.cpu0.num_idle_cycles 50234015072.883141 # Number of idle cycles +system.cpu0.num_busy_cycles 1587516424.116865 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030634 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969366 # Percentage of idle cycles +system.cpu0.Branches 99742938 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 363667031 69.31% 69.31% # Class of executed instruction -system.cpu0.op_class::IntMult 1107197 0.21% 69.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 49205 0.01% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55532 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 83525533 15.92% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 76293917 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 363863642 69.32% 69.32% # Class of executed instruction +system.cpu0.op_class::IntMult 1121256 0.21% 69.53% # Class of executed instruction +system.cpu0.op_class::IntDiv 48514 0.01% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 55488 0.01% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu0.op_class::MemRead 83607531 15.93% 85.48% # Class of executed instruction +system.cpu0.op_class::MemWrite 76227456 14.52% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 524698416 # Class of executed instruction -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 10234473 # number of replacements +system.cpu0.op_class::total 524923888 # Class of executed instruction +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 10233133 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10234985 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.294589 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 310246690 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10233645 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.316343 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 3504381500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 238.684462 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 273.281191 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466181 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.533752 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 237.355546 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 274.610106 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.463585 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.536348 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72354151 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 72480719 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 144834870 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196883 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197851 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 394734 # number of SoftPFReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165349 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::cpu1.data 170410 # number of WriteLineReq hits -system.cpu0.dcache.WriteLineReq_hits::total 335759 # number of WriteLineReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1859357 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1826349 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3685706 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2010395 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1982201 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3992596 # 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Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 78084246 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78779688 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156863934 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72276585 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 72648252 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 144924837 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 197426 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197729 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395155 # number of SoftPFReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu0.data 164722 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::cpu1.data 170823 # number of WriteLineReq hits +system.cpu0.dcache.WriteLineReq_hits::total 335545 # number of WriteLineReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1869757 # 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average WriteReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 20577.024872 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20449.279640 # average WriteLineReq miss latency +system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 20513.817411 # average WriteLineReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14754.809500 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14696.882701 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14724.934095 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 57000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 83000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 57250 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20356.193932 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20035.874198 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 20195.386458 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17671.986198 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17463.286601 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17567.422164 # average overall miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 65666.666667 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20293.123547 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20108.215358 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20200.385694 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17610.835060 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17537.470583 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17574.131558 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 7894898 # number of writebacks -system.cpu0.dcache.writebacks::total 7894898 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 9495 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 12245 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 21740 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 9899 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 11338 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21237 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 35923 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35789 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 71712 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 19394 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 23583 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 42977 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 19394 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 23583 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 42977 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2615890 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2681773 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5297663 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1113026 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1090097 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2203123 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 662931 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 648115 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1311046 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 621975 # number of WriteLineReq MSHR misses -system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 610318 # 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number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21221 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 36169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35602 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 71771 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 20845 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 22207 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 43052 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 20845 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 22207 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 43052 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2615682 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2681417 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5297099 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1115792 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1088468 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2204260 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 665476 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 644343 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1309819 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 622669 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 609834 # number of WriteLineReq MSHR misses +system.cpu0.dcache.WriteLineReq_mshr_misses::total 1232503 # number of WriteLineReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 112807 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 123061 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 235868 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4350891 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 4382188 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 8733079 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5013822 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 5030303 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 10044125 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16759 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 16947 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4354143 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 4379719 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 8733862 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5019619 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 5024062 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 10043681 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16676 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17030 # number of ReadReq MSHR uncacheable system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15119 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18591 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 14991 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 18719 # number of WriteReq MSHR uncacheable system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31878 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35538 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31667 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 35749 # number of overall MSHR uncacheable misses system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 39006077000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 39571050000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 78577127000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32849881500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31814880500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 64664762000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10562457500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10483200000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21045657500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 12173685500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11859131500 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24032817000 # number of WriteLineReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1545963000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1623615500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3169578500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 143000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38950730500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 39600598000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 78551328500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32683890500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 32050078500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 64733969000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 10672378000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10358334500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21030712500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 12190006500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11860832000 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24050838500 # number of WriteLineReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1508170000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1647856500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3156026500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 112000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 82000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 225000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 84029644000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83245062000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 167274706000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94592101500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93728262000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 188320363500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3122320000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3110634500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232954500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3122320000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3110634500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232954500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032439 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032923 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032683 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015148 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014815 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014981 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770234 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.765295 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767784 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.789986 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781729 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.785875 # mshr miss rate for WriteLineReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057648 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060980 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059302 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 194000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83824627500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83511508500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 167336136000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94497005500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 93869843000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 188366848500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3111292000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3121623000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6232915000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3111292000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 3121623000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6232915000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032408 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032912 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032661 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015201 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014759 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014980 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.770427 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.764355 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.767428 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.790800 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.781180 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.786011 # mshr miss rate for WriteLineReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055880 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062259 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059036 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028088 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028124 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028106 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032188 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032109 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032148 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14911.206893 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14755.555373 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14832.413274 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29514.028873 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29185.366532 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29351.407979 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15932.966629 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16174.907231 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.569856 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19572.628321 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19431.069541 # average WriteLineReq mshr miss latency -system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19502.518476 # average WriteLineReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13333.819204 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13426.410148 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13381.088783 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 47666.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028109 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028075 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028092 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032226 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.032032 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.032129 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14891.233147 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14768.533951 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14829.122223 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29292.099692 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29445.127004 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 29367.664885 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16037.209456 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16075.808226 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16056.197459 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 19577.024872 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19449.279640 # average WriteLineReq mshr miss latency +system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 19513.817411 # average WriteLineReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13369.471753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13390.566467 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13380.477640 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 56000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 82000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 56250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19313.203663 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18996.232476 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19154.150100 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18866.266393 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18632.726895 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18749.305042 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186307.058894 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183550.746445 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184921.215807 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97945.918815 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87529.813158 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92455.121930 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 13785272 # number of replacements +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 64666.666667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19251.693732 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19067.777750 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19159.466454 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18825.533472 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18684.053461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18754.762173 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186573.039098 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183301.409278 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184920.043909 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 98250.292102 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 87320.568408 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 92454.536015 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 13781825 # number of replacements system.cpu0.icache.tags.tagsinuse 511.891071 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 880886027 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13785784 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 63.898145 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 881366045 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13782337 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 63.948955 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 31614405500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 232.219683 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 279.671389 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.453554 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.546233 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 231.253269 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 280.637803 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.451667 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.548121 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999787 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 908457605 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 908457605 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 439628868 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 441257159 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 880886027 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 439628868 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 441257159 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 880886027 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 439628868 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 441257159 # number of overall hits -system.cpu0.icache.overall_hits::total 880886027 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6859636 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6926153 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13785789 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6859636 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6926153 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13785789 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6859636 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6926153 # number of overall misses -system.cpu0.icache.overall_misses::total 13785789 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92139159000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93034749000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 185173908000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 92139159000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 93034749000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 185173908000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 92139159000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 93034749000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 185173908000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 446488504 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 448183312 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 894671816 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 446488504 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 448183312 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 894671816 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 446488504 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 448183312 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 894671816 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015364 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015454 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015409 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015364 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015454 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015409 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015364 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015454 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015409 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13432.077008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13432.384326 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13432.231409 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13432.077008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13432.384326 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13432.231409 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13432.077008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13432.384326 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13432.231409 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 908930729 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 908930729 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 439927744 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 441438301 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 881366045 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 439927744 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 441438301 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 881366045 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 439927744 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 441438301 # number of overall hits +system.cpu0.icache.overall_hits::total 881366045 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6856104 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6926238 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13782342 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6856104 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6926238 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13782342 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6856104 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6926238 # number of overall misses +system.cpu0.icache.overall_misses::total 13782342 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92096826500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93000613500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 185097440000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 92096826500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 93000613500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 185097440000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 92096826500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 93000613500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 185097440000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 446783848 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 448364539 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 895148387 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 446783848 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 448364539 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 895148387 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 446783848 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 448364539 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 895148387 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015345 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015448 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015397 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015345 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015448 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015397 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015345 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015448 # 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number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1959551500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1303928500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 3263480000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015409 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015364 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015454 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015409 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015364 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015397 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015397 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015397 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12430.042586 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1101,75 +1108,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 133445 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 96452 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 133432 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.299778 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 83.395537 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 133430 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 131388 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 131388 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20694 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94767 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 12 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 131376 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.304470 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 84.045560 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 131374 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 133432 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 117373 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 25894.485955 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 22861.122715 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13849.356083 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 74140 63.17% 63.17% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 42199 35.95% 99.12% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 555 0.47% 99.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 343 0.29% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 6 0.01% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 29 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 23 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 117373 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 6007861436 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.129422 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -777548296 -12.94% -12.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 6785409732 112.94% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 6007861436 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 96452 82.18% 82.18% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 20908 17.82% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 117360 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 133445 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 131376 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 115473 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 25989.651260 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 22881.227305 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14446.882730 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 114392 99.06% 99.06% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 917 0.79% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 63 0.05% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 52 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 115473 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 5991401436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 1.130704 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -783101296 -13.07% -13.07% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 6774502732 113.07% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 5991401436 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94767 82.08% 82.08% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20694 17.92% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 115461 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 131388 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 133445 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 117360 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 131388 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115461 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 117360 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 250805 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115461 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 246849 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 84301684 # DTB read hits -system.cpu1.dtb.read_misses 101780 # DTB read misses -system.cpu1.dtb.write_hits 76371214 # DTB write hits -system.cpu1.dtb.write_misses 31665 # DTB write misses +system.cpu1.dtb.read_hits 84308595 # DTB read hits +system.cpu1.dtb.read_misses 100203 # DTB read misses +system.cpu1.dtb.write_hits 76530288 # DTB write hits +system.cpu1.dtb.write_misses 31185 # DTB write misses system.cpu1.dtb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 73965 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 73106 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4660 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10027 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 84403464 # DTB read accesses -system.cpu1.dtb.write_accesses 76402879 # DTB write accesses +system.cpu1.dtb.perms_faults 9685 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 84408798 # DTB read accesses +system.cpu1.dtb.write_accesses 76561473 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 160672898 # DTB hits -system.cpu1.dtb.misses 133445 # DTB misses -system.cpu1.dtb.accesses 160806343 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 160838883 # DTB hits +system.cpu1.dtb.misses 131388 # DTB misses +system.cpu1.dtb.accesses 160970271 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1199,150 +1201,144 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 78111 # Table walker walks requested -system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68231 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 78111 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 78111 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 78111 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 72561 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 28942.620692 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 25930.573552 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 16143.079615 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 35934 49.52% 49.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 35483 48.90% 98.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 386 0.53% 98.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 612 0.84% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 10 0.01% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 47 0.06% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 72561 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 76510 # Table walker walks requested +system.cpu1.itb.walker.walksLong 76510 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4384 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66713 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 76510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 76510 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 76510 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71097 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 29111.284583 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 26008.835767 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16533.926039 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 69890 98.30% 98.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1057 1.49% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 63 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71097 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -850152296 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -850152296 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -850152296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 68231 94.03% 94.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4330 5.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72561 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 66713 93.83% 93.83% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4384 6.17% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71097 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78111 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 76510 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 76510 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72561 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72561 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 150672 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 448183312 # ITB inst hits -system.cpu1.itb.inst_misses 78111 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71097 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71097 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 147607 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 448364539 # ITB inst hits +system.cpu1.itb.inst_misses 76510 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51822 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53921 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 52840 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 448261423 # ITB inst accesses -system.cpu1.itb.hits 448183312 # DTB hits -system.cpu1.itb.misses 78111 # DTB misses -system.cpu1.itb.accesses 448261423 # DTB accesses -system.cpu1.numPwrStateTransitions 16084 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 8042 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 6194937221.007833 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 118254200557.171326 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 3517 43.73% 43.73% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 4458 55.43% 99.17% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.06% 99.23% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 448441049 # ITB inst accesses +system.cpu1.itb.hits 448364539 # DTB hits +system.cpu1.itb.misses 76510 # DTB misses +system.cpu1.itb.accesses 448441049 # DTB accesses +system.cpu1.numPwrStateTransitions 16068 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 8034 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 6192978089.022779 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 118311828609.490631 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 3509 43.68% 43.68% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 4459 55.50% 99.18% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.23% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.79% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.81% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::overflows 13 0.16% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 3977581677820 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 8042 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 2001314736155 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 49819685131345 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 51820425457 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 3977581604528 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 8034 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 2066588908291 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 49754385967209 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 51820418254 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.committedInsts 447903186 # Number of instructions committed -system.cpu1.committedOps 526302841 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 483164392 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 453837 # Number of float alu accesses -system.cpu1.num_func_calls 26485275 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 68482317 # number of instructions that are conditional controls -system.cpu1.num_int_insts 483164392 # number of integer instructions -system.cpu1.num_fp_insts 453837 # number of float instructions -system.cpu1.num_int_register_reads 704985819 # number of times the integer registers were read -system.cpu1.num_int_register_writes 383399771 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 733419 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 379508 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 118000089 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 117710485 # number of times the CC registers were written -system.cpu1.num_mem_refs 160666503 # number of memory refs -system.cpu1.num_load_insts 84298667 # Number of load instructions -system.cpu1.num_store_insts 76367836 # Number of store instructions -system.cpu1.num_idle_cycles 50233099437.419525 # Number of idle cycles -system.cpu1.num_busy_cycles 1587326019.580469 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030631 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969369 # Percentage of idle cycles -system.cpu1.Branches 100046269 # Number of branches fetched +system.cpu1.committedInsts 448088743 # Number of instructions committed +system.cpu1.committedOps 526628545 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 483582453 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 455004 # Number of float alu accesses +system.cpu1.num_func_calls 26546962 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68480445 # number of instructions that are conditional controls +system.cpu1.num_int_insts 483582453 # number of integer instructions +system.cpu1.num_fp_insts 455004 # number of float instructions +system.cpu1.num_int_register_reads 705060671 # number of times the integer registers were read +system.cpu1.num_int_register_writes 383633333 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 735821 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 380160 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 117946404 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117660346 # number of times the CC registers were written +system.cpu1.num_mem_refs 160831979 # number of memory refs +system.cpu1.num_load_insts 84305574 # Number of load instructions +system.cpu1.num_store_insts 76526405 # Number of store instructions +system.cpu1.num_idle_cycles 50231588268.978668 # Number of idle cycles +system.cpu1.num_busy_cycles 1588829985.021333 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030660 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969340 # Percentage of idle cycles +system.cpu1.Branches 100054364 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 364713411 69.26% 69.26% # Class of executed instruction -system.cpu1.op_class::IntMult 1116791 0.21% 69.47% # Class of executed instruction -system.cpu1.op_class::IntDiv 48530 0.01% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 54891 0.01% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction -system.cpu1.op_class::MemRead 84298667 16.01% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 76367836 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 364882138 69.25% 69.25% # Class of executed instruction +system.cpu1.op_class::IntMult 1103160 0.21% 69.46% # Class of executed instruction +system.cpu1.op_class::IntDiv 49288 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 54935 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::MemRead 84305574 16.00% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 76526405 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 526600168 # Class of executed instruction -system.iobus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 40318 # Transaction distribution -system.iobus.trans_dist::ReadResp 40318 # Transaction distribution +system.cpu1.op_class::total 526921542 # Class of executed instruction +system.iobus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 40309 # Transaction distribution +system.iobus.trans_dist::ReadResp 40309 # Transaction distribution system.iobus.trans_dist::WriteReq 136571 # Transaction distribution system.iobus.trans_dist::WriteResp 136571 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) @@ -1359,11 +1355,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230994 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230994 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353778 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) @@ -1378,16 +1374,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334408 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334408 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492328 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 42147500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -1405,75 +1401,75 @@ system.iobus.reqLayer16.occupancy 17000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 25749000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 25738000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38609000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 568885533 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 568948940 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 147754000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 115478 # number of replacements -system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 115469 # number of replacements +system.iocache.tags.tagsinuse 10.457310 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115494 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115485 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153888090000 # Cycle when the warmup percentage was hit. +system.iocache.tags.warmup_cycle 13153887286000 # Cycle when the warmup percentage was hit. system.iocache.tags.occ_blocks::realview.ethernet 3.511180 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946135 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946130 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ethernet 0.219449 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.434133 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.653582 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039830 # Number of tag accesses -system.iocache.tags.data_accesses 1039830 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.iocache.tags.tag_accesses 1039749 # Number of tag accesses +system.iocache.tags.data_accesses 1039749 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8833 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8870 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8824 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8861 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 115497 # number of demand (read+write) misses -system.iocache.demand_misses::total 115537 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 115488 # number of demand (read+write) misses +system.iocache.demand_misses::total 115528 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 115497 # number of overall misses -system.iocache.overall_misses::total 115537 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1609929768 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1615016268 # number of ReadReq miss cycles +system.iocache.overall_misses::realview.ide 115488 # number of overall misses +system.iocache.overall_misses::total 115528 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1592669163 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1597755163 # number of ReadReq miss cycles system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 12771447265 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 12771447265 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 14381377033 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14386814533 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 14381377033 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14386814533 # number of overall miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 12771081777 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 12771081777 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 14363750940 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14369187940 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 14363750940 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14369187940 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8833 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8870 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8824 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8861 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 115497 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 115537 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 115488 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 115528 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 115497 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 115537 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 115488 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 115528 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1487,53 +1483,53 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 182263.078003 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 182076.242165 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 180492.878853 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 180313.188466 # average ReadReq miss latency system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119735.311492 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 119735.311492 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124521.274856 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124517.321082 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124521.274856 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 31700 # number of cycles access was blocked +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 119731.884956 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 119731.884956 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124374.402016 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124378.401253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124374.402016 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124378.401253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 30368 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3352 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 9.457041 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.067781 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8833 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8870 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8824 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8861 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 115497 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 115537 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 115488 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 115528 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 115497 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 115537 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1168279768 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1171516268 # number of ReadReq MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 115488 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 115528 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1151469163 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1154705163 # number of ReadReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_latency::total 201000 # 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number of overall hits -system.l2c.overall_hits::cpu0.data 4077677 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 249681 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 166863 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6886530 # number of overall hits -system.l2c.overall_hits::cpu1.data 4121923 # number of overall hits -system.l2c.overall_hits::total 22735690 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1919 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1974 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2347 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2061 # number of ReadReq misses -system.l2c.ReadReq_misses::total 8301 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17868 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18114 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35982 # 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number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 169318 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 245899 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 163828 # number of ReadReq hits +system.l2c.ReadReq_hits::total 827525 # number of ReadReq hits +system.l2c.WritebackDirty_hits::writebacks 7895103 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 7895103 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 13780242 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 13780242 # number of WritebackClean hits +system.l2c.UpgradeReq_hits::cpu0.data 5072 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4937 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10009 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 827908 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 804935 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1632843 # number of ReadExReq hits +system.l2c.ReadCleanReq_hits::cpu0.inst 6817014 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 6887144 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 13704158 # number of ReadCleanReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 3253717 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 3311406 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 6565123 # number of ReadSharedReq hits +system.l2c.InvalidateReq_hits::cpu0.data 363022 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::cpu1.data 359819 # number of InvalidateReq hits +system.l2c.InvalidateReq_hits::total 722841 # number of InvalidateReq hits +system.l2c.demand_hits::cpu0.dtb.walker 248480 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 169318 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6817014 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4081625 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.037667 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77153.623538 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18916.583027 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18919.496014 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18918.039642 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 44500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44750 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72050.491966 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71881.386450 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 71967.562553 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72781.640257 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74479.073353 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74378.277580 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74428.910610 # average ReadSharedReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18671.781922 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18663.857839 # average InvalidateReq mshr miss latency -system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18667.893869 # average InvalidateReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72001.797054 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71983.378667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 71992.661792 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72797.017293 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74403.995372 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74590.725350 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74496.407757 # average ReadSharedReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18670.722173 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18670.205788 # average InvalidateReq mshr miss latency +system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.468860 # average InvalidateReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 72892.859506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 72892.859506 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173784.623188 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174050.071960 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171027.320470 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.538572 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170778.479154 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.017948 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91362.585482 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91655.635204 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81557.769149 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.649234 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 2972233 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 1487104 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 3352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81354.933005 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.287378 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 2973114 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 1487263 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 3311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 76831 # Transaction distribution -system.membus.trans_dist::ReadResp 450834 # Transaction distribution +system.membus.trans_dist::ReadResp 449832 # Transaction distribution system.membus.trans_dist::WriteReq 33710 # Transaction distribution system.membus.trans_dist::WriteResp 33710 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1228413 # Transaction distribution -system.membus.trans_dist::CleanEvict 193324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36554 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1230432 # Transaction distribution +system.membus.trans_dist::CleanEvict 191908 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36440 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 8 # Transaction distribution -system.membus.trans_dist::ReadExReq 524356 # Transaction distribution -system.membus.trans_dist::ReadExResp 524356 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 374003 # Transaction distribution -system.membus.trans_dist::InvalidateReq 615538 # Transaction distribution +system.membus.trans_dist::ReadExReq 524978 # Transaction distribution +system.membus.trans_dist::ReadExResp 524978 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 373001 # Transaction distribution +system.membus.trans_dist::InvalidateReq 616319 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721390 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3851094 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 237382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4088476 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721926 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 3851630 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 237395 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4089025 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128872672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 129042522 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7231808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 7231808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 136274330 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3165 # Total snoops (count) -system.membus.snoop_fanout::samples 1660996 # Request fanout histogram -system.membus.snoop_fanout::mean 0.019349 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.137749 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128978144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129147994 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7233792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 136381786 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3125 # Total snoops (count) +system.membus.snoopTraffic 199488 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 1661282 # Request fanout histogram +system.membus.snoop_fanout::mean 0.019128 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.136975 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1628857 98.07% 98.07% # Request fanout histogram -system.membus.snoop_fanout::1 32139 1.93% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 1629505 98.09% 98.09% # Request fanout histogram +system.membus.snoop_fanout::1 31777 1.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 1660996 # Request fanout histogram -system.membus.reqLayer0.occupancy 106934500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 1661282 # Request fanout histogram +system.membus.reqLayer0.occupancy 106916500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5678000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5690500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 8069625955 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 8079257005 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4926078787 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4924178426 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 44658046 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -2173,85 +2170,86 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 48659442 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 24643437 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1748 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 2028 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 1290012 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21916025 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 9016681 # Transaction distribution -system.toL2Bus.trans_dist::WritebackClean 13785272 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2525177 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45989 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45993 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2157137 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2157137 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 13785789 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 6848293 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 1261037 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 1232293 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41443100 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30932231 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796412 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1256395 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 74428138 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764720404 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081696966 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2696152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 4001736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2853115258 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1718109 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 26731746 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.021922 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.146427 # Request fanout histogram +system.toL2Bus.trans_dist::WritebackDirty 9018905 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 13781825 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2522217 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45883 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2158380 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2158380 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 13782342 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 6845459 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 1260926 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 1232503 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41432759 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30927957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796484 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1252515 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 74409715 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764279188 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081608326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2697464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3989080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2852574058 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1717339 # Total snoops (count) +system.toL2Bus.snoopTraffic 74998872 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 26724704 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.021941 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.146492 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 26145745 97.81% 97.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 586001 2.19% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 26138332 97.81% 97.81% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 586372 2.19% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 26731746 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 46403347500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 26724704 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 46394070000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1695386 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1633889 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 20721808500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 20716638000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 14193795462 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 14191518968 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 459393000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 459301000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 756178000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 753880000 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |