diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:50:15 -0500 |
| commit | 29cd50e14e0709c28200bcbdbc08c1093ba300d7 (patch) | |
| tree | ce3db836e947d154cbd0e4d7e1959f7617a7cc0c /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | |
| parent | 7a0bf814b6eb2db57f37977a0cca6c442f957d68 (diff) | |
| download | gem5-29cd50e14e0709c28200bcbdbc08c1093ba300d7.tar.xz | |
arm, tests: Add 64-bit ARM regression tests
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt | 1861 |
1 files changed, 1861 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt new file mode 100644 index 000000000..3f21941cc --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -0,0 +1,1861 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 51.861029 # Number of seconds simulated +sim_ticks 51861029093000 # Number of ticks simulated +final_tick 51861029093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 655308 # Simulator instruction rate (inst/s) +host_op_rate 770071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39176575505 # Simulator tick rate (ticks/s) +host_mem_usage 667356 # Number of bytes of host memory used +host_seconds 1323.78 # Real time elapsed on the host +sim_insts 867480679 # Number of instructions simulated +sim_ops 1019401547 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.ide 385536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 227072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 396672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2360360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 30329136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 251456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 422720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2259596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 29551000 # Number of bytes read from this memory +system.physmem.bytes_read::total 66183548 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2360360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2259596 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 4619956 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 36744512 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 6826496 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 49590532 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 50357856 # Number of bytes written to this memory +system.physmem.bytes_written::total 143519396 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 6024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 3548 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 6198 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64295 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 473896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3929 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 6605 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 48299 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 461744 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1074538 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 574133 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 106664 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 774853 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 789092 # Number of write requests responded to by this memory +system.physmem.num_writes::total 2244742 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 7434 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 4378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 7649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 45513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 584816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 569811 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1276171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 45513 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43570 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 89083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 708519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 131631 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 956220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 971015 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2767384 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 708519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 139065 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 4378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 7649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 45513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1541035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1540827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4043555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1074538 # Number of read requests accepted +system.physmem.writeReqs 2244742 # Number of write requests accepted +system.physmem.readBursts 1074538 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2244742 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68582272 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 188160 # Total number of bytes read from write queue +system.physmem.bytesWritten 138957696 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 66183548 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 143519396 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2940 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 73507 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 34757 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 71255 # Per bank write bursts +system.physmem.perBankRdBursts::1 63640 # Per bank write bursts +system.physmem.perBankRdBursts::2 66612 # Per bank write bursts +system.physmem.perBankRdBursts::3 61740 # Per bank write bursts +system.physmem.perBankRdBursts::4 60545 # Per bank write bursts +system.physmem.perBankRdBursts::5 71198 # Per bank write bursts +system.physmem.perBankRdBursts::6 58053 # Per bank write bursts +system.physmem.perBankRdBursts::7 57022 # Per bank write bursts +system.physmem.perBankRdBursts::8 61158 # Per bank write bursts +system.physmem.perBankRdBursts::9 112029 # Per bank write bursts +system.physmem.perBankRdBursts::10 66876 # Per bank write bursts +system.physmem.perBankRdBursts::11 66235 # Per bank write bursts +system.physmem.perBankRdBursts::12 62785 # Per bank write bursts +system.physmem.perBankRdBursts::13 68778 # Per bank write bursts +system.physmem.perBankRdBursts::14 63805 # Per bank write bursts +system.physmem.perBankRdBursts::15 59867 # Per bank write bursts +system.physmem.perBankWrBursts::0 127784 # Per bank write bursts +system.physmem.perBankWrBursts::1 113302 # Per bank write bursts +system.physmem.perBankWrBursts::2 227736 # Per bank write bursts +system.physmem.perBankWrBursts::3 110987 # Per bank write bursts +system.physmem.perBankWrBursts::4 128170 # Per bank write bursts +system.physmem.perBankWrBursts::5 133310 # Per bank write bursts +system.physmem.perBankWrBursts::6 113658 # Per bank write bursts +system.physmem.perBankWrBursts::7 104648 # Per bank write bursts +system.physmem.perBankWrBursts::8 114567 # Per bank write bursts +system.physmem.perBankWrBursts::9 129854 # Per bank write bursts +system.physmem.perBankWrBursts::10 127393 # Per bank write bursts +system.physmem.perBankWrBursts::11 118149 # Per bank write bursts +system.physmem.perBankWrBursts::12 133562 # Per bank write bursts +system.physmem.perBankWrBursts::13 181801 # Per bank write bursts +system.physmem.perBankWrBursts::14 180172 # Per bank write bursts +system.physmem.perBankWrBursts::15 126121 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 51861026536500 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 43101 # Read request sizes (log2) +system.physmem.readPktSize::3 13 # Read request sizes (log2) +system.physmem.readPktSize::4 2 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 1031422 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 1 # Write request sizes (log2) +system.physmem.writePktSize::3 2572 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 2242169 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1023941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 42084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 554 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 705 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 99 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 93 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 1684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1645 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1621 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 85670 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 108888 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 136245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 120874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 128354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 124706 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 123045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 137746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 127099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 129811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 118729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 118092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 115613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 114537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 111395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 110878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 111594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 108741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 38 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 634955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 326.856851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.109909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.606066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251774 39.65% 39.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 143572 22.61% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53819 8.48% 70.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28426 4.48% 75.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19160 3.02% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 14370 2.26% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 10671 1.68% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11114 1.75% 83.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 102049 16.07% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 634955 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 109417 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.793551 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 155.538286 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 109409 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::18432-20479 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 109417 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 109417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.843480 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.459226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 5.174824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 51 0.05% 0.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 17 0.02% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 14 0.01% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 145 0.13% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 52162 47.67% 47.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 51235 46.83% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 1984 1.81% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 1760 1.61% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 951 0.87% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 159 0.15% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 147 0.13% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 71 0.06% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 99 0.09% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 20 0.02% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 21 0.02% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 18 0.02% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 372 0.34% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 33 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 39 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 25 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 36 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 9 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 109417 # Writes before turning the bus around for reads +system.physmem.totQLat 11994975500 # Total ticks spent queuing +system.physmem.totMemAccLat 32087438000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5357990000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11193.54 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 29943.54 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 10.58 # Average write queue length when enqueuing +system.physmem.readRowHits 810923 # Number of row buffer hits during reads +system.physmem.writeRowHits 1796931 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.76 # Row buffer hit rate for writes +system.physmem.avgGap 15624179.50 # Average gap between requests +system.physmem.pageHitRate 80.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 49513780638000 # Time in different power states +system.physmem.memoryStateTime::REF 1731753660000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 615493469500 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem.actEnergy::0 2375299080 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 2424960720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 1296046125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 1323143250 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 3978491400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 4379902800 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 6866175600 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 7203291120 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 3387310158960 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 3387310158960 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 1391264257590 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 1403130352860 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 29896208916750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 29885800061250 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 34689299345505 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 34691571870960 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.889557 # Core power per rank (mW) +system.physmem.averagePower::1 668.933377 # Core power per rank (mW) +system.membus.trans_dist::ReadReq 477149 # Transaction distribution +system.membus.trans_dist::ReadResp 477149 # Transaction distribution +system.membus.trans_dist::WriteReq 33873 # Transaction distribution +system.membus.trans_dist::WriteResp 33873 # Transaction distribution +system.membus.trans_dist::Writeback 574133 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 1668036 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 1668036 # Transaction distribution +system.membus.trans_dist::UpgradeReq 34762 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 34763 # Transaction distribution +system.membus.trans_dist::ReadExReq 634040 # Transaction distribution +system.membus.trans_dist::ReadExResp 634040 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5908571 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6038767 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 228229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 228229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6266996 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 202490912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 202661260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7212032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 7212032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 209873292 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2859 # Total snoops (count) +system.membus.snoop_fanout::samples 3311225 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 3311225 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3311225 # Request fanout histogram +system.membus.reqLayer0.occupancy 107353000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 5576998 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 22591732739 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 12337625717 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 186623209 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.l2c.tags.replacements 742012 # number of replacements +system.l2c.tags.tagsinuse 64270.398590 # Cycle average of tags in use +system.l2c.tags.total_refs 26902368 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 803524 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 33.480478 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 13975543266000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37175.370722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 164.612464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 268.035680 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3943.940555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8908.960135 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 136.845941 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 225.029794 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3060.985707 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 10386.617592 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.567251 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004090 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.060180 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.135940 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002088 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003434 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.046707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.158487 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.980688 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 429 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61083 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 418 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1800 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5332 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53777 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.006546 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.932053 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 254875429 # Number of tag accesses +system.l2c.tags.data_accesses 254875429 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 223794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 158122 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6853057 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3117827 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 234015 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 160485 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 6849994 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3144760 # number of ReadReq hits +system.l2c.ReadReq_hits::total 20742054 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 6657868 # number of Writeback hits +system.l2c.Writeback_hits::total 6657868 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 4874 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5098 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9972 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 711006 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 709189 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1420195 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 223794 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 158122 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6853057 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3828833 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 234015 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 160485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6849994 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3853949 # number of demand (read+write) hits +system.l2c.demand_hits::total 22162249 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 223794 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 158122 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6853057 # number of overall hits +system.l2c.overall_hits::cpu0.data 3828833 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 234015 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 160485 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6849994 # number of overall hits +system.l2c.overall_hits::cpu1.data 3853949 # number of overall hits +system.l2c.overall_hits::total 22162249 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3548 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 6198 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 35053 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 148459 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3929 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 6605 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 34440 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 153129 # number of ReadReq misses +system.l2c.ReadReq_misses::total 391361 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17026 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 17173 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 34199 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 325694 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 308906 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 634600 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3548 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 6198 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 35053 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 474153 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3929 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 6605 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34440 # 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mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.314164 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303416 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.308839 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.015606 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.037719 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.110192 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.016512 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.039530 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.107052 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.044245 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.015606 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.037719 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.110192 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.016512 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.039530 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.107052 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.044245 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61921.392452 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61488.721934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61808.552748 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.024727 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.852093 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.444487 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 59385.087720 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58837.681366 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 59118.625213 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 60179.213802 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59716.297036 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60144.719509 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64077.156144 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64393.877057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61448.385359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 60179.213802 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64551.094426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 65615.064345 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61368.888124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59716.297036 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60144.719509 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.txBytes 966 # Bytes Transmitted +system.realview.ethernet.txPackets 3 # Number of Packets Transmitted +system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device +system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device +system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totPackets 3 # Total Packets +system.realview.ethernet.totBytes 966 # Total Bytes +system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) +system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 18 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1669 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 21596881 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 21588675 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 6657868 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1668053 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1561372 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 44174 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 44175 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2054795 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2054795 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27631338 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27242891 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 786774 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1184296 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 56845299 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881615316 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1077879160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2651280 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3722288 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 1965868044 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 493907 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 31944858 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.003617 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.060036 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 31829300 99.64% 99.64% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 115558 0.36% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 31944858 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 48864007000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 3007500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 62042103256 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 39821087024 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 456077500 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 719536250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 40403 # Transaction distribution +system.iobus.trans_dist::ReadResp 40403 # Transaction distribution +system.iobus.trans_dist::WriteReq 136728 # Transaction distribution +system.iobus.trans_dist::WriteResp 136733 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 5 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 981115277 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 179046791 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 81298671 # DTB read hits +system.cpu0.dtb.read_misses 94598 # DTB read misses +system.cpu0.dtb.write_hits 74077534 # DTB write hits +system.cpu0.dtb.write_misses 29691 # DTB write misses +system.cpu0.dtb.flush_tlb 51863 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 72449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 4385 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 9644 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81393269 # DTB read accesses +system.cpu0.dtb.write_accesses 74107225 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 155376205 # DTB hits +system.cpu0.dtb.misses 124289 # DTB misses +system.cpu0.dtb.accesses 155500494 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu0.itb.inst_hits 433719693 # ITB inst hits +system.cpu0.itb.inst_misses 76771 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 51863 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 19908 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 526 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53078 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 433796464 # ITB inst accesses +system.cpu0.itb.hits 433719693 # DTB hits +system.cpu0.itb.misses 76771 # DTB misses +system.cpu0.itb.accesses 433796464 # DTB accesses +system.cpu0.numCycles 51861670459 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 433465167 # Number of instructions committed +system.cpu0.committedOps 509426348 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 467950836 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 437595 # Number of float alu accesses +system.cpu0.num_func_calls 25817816 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 66030471 # number of instructions that are conditional controls +system.cpu0.num_int_insts 467950836 # number of integer instructions +system.cpu0.num_fp_insts 437595 # number of float instructions +system.cpu0.num_int_register_reads 681169150 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371166205 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 709571 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 361724 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113513031 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113190912 # number of times the CC registers were written +system.cpu0.num_mem_refs 155365727 # number of memory refs +system.cpu0.num_load_insts 81295009 # Number of load instructions +system.cpu0.num_store_insts 74070718 # Number of store instructions +system.cpu0.num_idle_cycles 50261080538.032112 # Number of idle cycles +system.cpu0.num_busy_cycles 1600589920.967886 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030863 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969137 # Percentage of idle cycles +system.cpu0.Branches 96751437 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 353168573 69.29% 69.29% # Class of executed instruction +system.cpu0.op_class::IntMult 1074186 0.21% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 48850 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52802 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 81295009 15.95% 85.47% # Class of executed instruction +system.cpu0.op_class::MemWrite 74070718 14.53% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 509710139 # Class of executed instruction +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 16204 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 13772027 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.894677 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 854244882 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13772539 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.025229 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 31522505250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 257.415454 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 254.479223 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.502765 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.497030 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999794 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 186 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 881789970 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 881789970 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 426831583 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 427413299 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 854244882 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 426831583 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 427413299 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 854244882 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 426831583 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 427413299 # number of overall hits +system.cpu0.icache.overall_hits::total 854244882 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6888110 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6884434 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13772544 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6888110 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6884434 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13772544 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6888110 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6884434 # number of overall misses +system.cpu0.icache.overall_misses::total 13772544 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92034347501 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 91949004755 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 183983352256 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 92034347501 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 91949004755 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 183983352256 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 92034347501 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 91949004755 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 183983352256 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 433719693 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 434297733 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 868017426 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 433719693 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 434297733 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 868017426 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 433719693 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 434297733 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 868017426 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015881 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015852 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015867 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015881 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015852 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015867 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015881 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015852 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015867 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13361.335330 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13356.073245 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13358.704990 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13361.335330 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13356.073245 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13358.704990 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13361.335330 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13356.073245 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13358.704990 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6888110 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6884434 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 13772544 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6888110 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 6884434 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 13772544 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 78167770745 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 156413334744 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 912090000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2831704500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 912090000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 2831704500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015881 # 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average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 9844382 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.969698 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 301160300 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 9844894 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.590507 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 231.008949 # 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miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763110 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.757001 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760076 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077745 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076624 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077184 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024033 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024176 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024105 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028015 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028061 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028038 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15814.645087 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15859.003827 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15837.031986 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 33150.063365 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 32313.199090 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32734.814354 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14134.142108 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14395.484168 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14264.010214 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26501 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20953.638863 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20621.136573 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 20786.658245 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17878.178294 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17672.228332 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17774.978500 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 1561372 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 6657868 # number of writebacks +system.cpu0.dcache.writebacks::total 6657868 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 2373 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2635 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 5008 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 9569 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 11674 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21243 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34459 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35374 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 69833 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 11942 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 14309 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 26251 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 11942 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 14309 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 26251 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2532723 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2580350 # 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number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3591323 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3620716 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7212039 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4210993 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4227089 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8438082 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34851412248 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 35605867999 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 70457280247 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32909222465 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31498383779 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 64407606244 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 9405033000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9253843000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18658876000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25180083991 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 25557110497 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 50737194488 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1372984750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1359653250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2732638000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 24499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 24499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67760634713 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 67104251778 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 134864886491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77165667713 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 76358094778 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 153523762491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2724103000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3004117998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728220998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2593769750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2980348000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574117750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5317872750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5984465998 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302338748 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032238 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032663 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032451 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014832 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014580 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014706 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.762894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.756761 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759849 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059686 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058128 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023953 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024081 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024017 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027935 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027965 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027950 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13760.451596 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13798.852093 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13779.830690 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31087.495244 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30276.252568 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30685.397593 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15177.486404 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15260.974681 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15218.777808 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12055.040696 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12230.837216 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12141.873909 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18867.875352 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18533.420400 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18699.966333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18324.815005 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18063.990320 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18194.153896 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 81731723 # DTB read hits +system.cpu1.dtb.read_misses 99102 # DTB read misses +system.cpu1.dtb.write_hits 74078403 # DTB write hits +system.cpu1.dtb.write_misses 30075 # DTB write misses +system.cpu1.dtb.flush_tlb 51867 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 72169 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 4438 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 9782 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 81830825 # DTB read accesses +system.cpu1.dtb.write_accesses 74108478 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 155810126 # DTB hits +system.cpu1.dtb.misses 129177 # DTB misses +system.cpu1.dtb.accesses 155939303 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu1.itb.inst_hits 434297733 # ITB inst hits +system.cpu1.itb.inst_misses 78021 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 51867 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 20925 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 515 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 53659 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 434375754 # ITB inst accesses +system.cpu1.itb.hits 434297733 # DTB hits +system.cpu1.itb.misses 78021 # DTB misses +system.cpu1.itb.accesses 434375754 # DTB accesses +system.cpu1.numCycles 51860387727 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 434015512 # Number of instructions committed +system.cpu1.committedOps 509975199 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 468434913 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 458508 # Number of float alu accesses +system.cpu1.num_func_calls 25828963 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 66119194 # number of instructions that are conditional controls +system.cpu1.num_int_insts 468434913 # number of integer instructions +system.cpu1.num_fp_insts 458508 # number of float instructions +system.cpu1.num_int_register_reads 681011171 # number of times the integer registers were read +system.cpu1.num_int_register_writes 371474138 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 735722 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 396908 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 113358693 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 113081851 # number of times the CC registers were written +system.cpu1.num_mem_refs 155802990 # number of memory refs +system.cpu1.num_load_insts 81728236 # Number of load instructions +system.cpu1.num_store_insts 74074754 # Number of store instructions +system.cpu1.num_idle_cycles 50263670387.895683 # Number of idle cycles +system.cpu1.num_busy_cycles 1596717339.104316 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030789 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969211 # Percentage of idle cycles +system.cpu1.Branches 96920557 # Number of branches fetched +system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 353254188 69.23% 69.23% # Class of executed instruction +system.cpu1.op_class::IntMult 1106936 0.22% 69.45% # Class of executed instruction +system.cpu1.op_class::IntDiv 48650 0.01% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 58473 0.01% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.47% # Class of executed instruction +system.cpu1.op_class::MemRead 81728236 16.02% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 74074754 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 510271279 # Class of executed instruction +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iocache.tags.replacements 115483 # number of replacements +system.iocache.tags.tagsinuse 10.461502 # Cycle average of tags in use +system.iocache.tags.total_refs 3 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 115499 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 13154061165000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 5.844281 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 4.617221 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.365268 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.288576 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653844 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 1039906 # Number of tag accesses +system.iocache.tags.data_accesses 1039906 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 106664 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 106664 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses +system.iocache.WriteReq_misses::total 3 # number of WriteReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 5 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 5 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses +system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ethernet 40 # number of overall misses +system.iocache.overall_misses::realview.ide 8837 # number of overall misses +system.iocache.overall_misses::total 8877 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1908690112 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1914175112 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1908690112 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1914514112 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1908690112 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1914514112 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106669 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106669 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses +system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000047 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000047 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 215988.470295 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 215706.007663 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 215671.297961 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 215988.470295 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 215671.297961 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 51929 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 9.458834 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 106664 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses +system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses +system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses +system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1449081112 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1452642112 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6526726956 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6526726956 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1449081112 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1452825112 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1449081112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1452825112 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses +system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses +system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163978.851646 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 163696.429119 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 163978.851646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 163661.722654 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- |