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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
commit84f138ba96201431513eb2ae5f847389ac731aa2 (patch)
tree3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing
parenta288c94387b110112461ff5686fa727a43ddbe9c (diff)
downloadgem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing')
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini317
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr159
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout10
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt3320
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal256
5 files changed, 2256 insertions, 1806 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
index 8093ae03e..f55dd08a3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/config.ini
@@ -12,23 +12,25 @@ time_sync_spin_threshold=100000000
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/work/gem5/dist/binaries/boot_emm.arm64
+boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb
+default_p_state=UNDEFINED
+dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
+exit_on_work_items=false
flags_addr=469827632
gic_cpu_addr=738205696
have_large_asid_64=false
-have_lpae=false
+have_lpae=true
have_security=false
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/work/gem5/dist/binaries/vmlinux.aarch64.20140821
+kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
@@ -40,12 +42,18 @@ mmap_using_noreserve=false
multi_proc=true
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh
+power_model=Null
+readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh
reset_addr_64=0
symbolfile=
+thermal_components=
+thermal_model=Null
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -58,8 +66,13 @@ system_port=system.membus.slave[1]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
delay=50000
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911
req_size=16
resp_size=16
@@ -86,7 +99,7 @@ table_size=65536
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/work/gem5/dist/disks/linaro-minimal-aarch64.img
+image_file=/arm/projectscratch/randd/systems/dist/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
@@ -104,6 +117,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -121,6 +135,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -139,13 +157,17 @@ addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -164,8 +186,13 @@ type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -188,9 +215,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker
[system.cpu0.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu0.dtb]
@@ -204,9 +236,14 @@ walker=system.cpu0.dtb.walker
[system.cpu0.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.toL2Bus.slave[3]
@@ -217,13 +254,17 @@ addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -242,8 +283,13 @@ type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=32768
@@ -301,9 +347,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker
[system.cpu0.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu0.itb]
@@ -317,9 +368,14 @@ walker=system.cpu0.itb.walker
[system.cpu0.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.toL2Bus.slave[2]
@@ -334,6 +390,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -351,6 +408,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -379,9 +440,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker
[system.cpu1.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu1.dtb]
@@ -395,9 +461,14 @@ walker=system.cpu1.dtb.walker
[system.cpu1.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu1.isa]
@@ -450,9 +521,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker
[system.cpu1.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu1.itb]
@@ -466,9 +542,14 @@ walker=system.cpu1.itb.walker
[system.cpu1.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu1.tracer]
@@ -499,9 +580,14 @@ sys=system
[system.iobus]
type=NoncoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=1
frontend_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
response_latency=2
use_default_range=false
width=16
@@ -515,13 +601,17 @@ addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=false
hit_latency=50
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=50
@@ -540,8 +630,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=50
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=1024
@@ -552,13 +647,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-forward_snoops=true
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -577,20 +676,31 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=4194304
[system.membus]
type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=true
+power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -602,11 +712,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=0
pio_latency=100000
pio_size=8
+power_model=Null
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
@@ -617,6 +732,13 @@ update_data=false
warn_access=warn
pio=system.membus.default
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
IDD0=0.075000
@@ -651,6 +773,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -662,7 +785,11 @@ max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
page_policy=open_adaptive
+power_model=Null
range=2147483648:2415919103
ranks_per_channel=2
read_buffer_size=32
@@ -705,10 +832,15 @@ system=system
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470024192
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[18]
@@ -789,14 +921,19 @@ VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=2
+default_p_state=UNDEFINED
disks=
eventq_index=0
host=system.realview.pci_host
io_shift=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_bus=2
pci_dev=0
pci_func=0
pio_latency=30000
+power_model=Null
system=system
dma=system.iobus.slave[2]
pio=system.iobus.master[9]
@@ -805,13 +942,18 @@ pio=system.iobus.master[9]
type=Pl111
amba_id=1315089
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
enable_capture=true
eventq_index=0
gic=system.realview.gic
int_num=46
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=471793664
pio_latency=10000
pixel_clock=41667
+power_model=Null
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
@@ -821,6 +963,7 @@ pio=system.iobus.master[5]
type=SubSystem
children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
eventq_index=0
+thermal_domain=Null
[system.realview.dcc.osc_cpu]
type=RealViewOsc
@@ -891,10 +1034,15 @@ voltage_domain=system.voltage_domain
[system.realview.energy_ctrl]
type=EnergyCtrl
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
dvfs_handler=system.dvfs_handler
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470286336
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[22]
@@ -974,17 +1122,22 @@ SubsystemVendorID=32902
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
+default_p_state=UNDEFINED
eventq_index=0
fetch_comp_delay=10000
fetch_delay=10000
hardware_address=00:90:00:00:00:01
host=system.realview.pci_host
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_bus=0
pci_dev=0
pci_func=0
phy_epid=896
phy_pid=680
pio_latency=30000
+power_model=Null
rx_desc_cache_size=64
rx_fifo_size=393216
rx_write_delay=0
@@ -1010,12 +1163,18 @@ type=Pl390
clk_domain=system.clk_domain
cpu_addr=738205696
cpu_pio_delay=10000
+default_p_state=UNDEFINED
dist_addr=738201600
dist_pio_delay=10000
eventq_index=0
+gem5_extensions=true
int_latency=10000
it_lines=128
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
platform=system.realview
+power_model=Null
system=system
pio=system.membus.master[2]
@@ -1023,14 +1182,19 @@ pio=system.membus.master[2]
type=HDLcd
amba_id=1314816
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
enable_capture=true
eventq_index=0
gic=system.realview.gic
int_num=117
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=721420288
pio_latency=10000
pixel_buffer_size=2048
pixel_chunk=32
+power_model=Null
pxl_clk=system.realview.dcc.osc_pxl
system=system
vnc=system.vncserver
@@ -1116,14 +1280,19 @@ VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
+default_p_state=UNDEFINED
disks=system.cf0
eventq_index=0
host=system.realview.pci_host
io_shift=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
+power_model=Null
system=system
dma=system.iobus.slave[3]
pio=system.iobus.master[23]
@@ -1132,13 +1301,18 @@ pio=system.iobus.master[23]
type=Pl050
amba_id=1314896
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=1000000
int_num=44
is_mouse=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470155264
pio_latency=100000
+power_model=Null
system=system
vnc=system.vncserver
pio=system.iobus.master[7]
@@ -1147,13 +1321,18 @@ pio=system.iobus.master[7]
type=Pl050
amba_id=1314896
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=1000000
int_num=45
is_mouse=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470220800
pio_latency=100000
+power_model=Null
system=system
vnc=system.vncserver
pio=system.iobus.master[8]
@@ -1161,11 +1340,16 @@ pio=system.iobus.master[8]
[system.realview.l2x0_fake]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=739246080
pio_latency=100000
pio_size=4095
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1179,11 +1363,16 @@ pio=system.iobus.master[12]
[system.realview.lan_fake]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=436207616
pio_latency=100000
pio_size=65535
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1197,19 +1386,25 @@ pio=system.iobus.master[19]
[system.realview.local_cpu_timer]
type=CpuLocalTimer
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num_timer=29
int_num_watchdog=30
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=738721792
pio_latency=100000
+power_model=Null
system=system
pio=system.membus.master[4]
[system.realview.mcc]
type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
eventq_index=0
+thermal_domain=Null
[system.realview.mcc.osc_clcd]
type=RealViewOsc
@@ -1255,14 +1450,29 @@ position=0
site=0
voltage_domain=system.voltage_domain
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470089728
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[21]
@@ -1271,11 +1481,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:67108863
port=system.membus.master[1]
@@ -1285,21 +1500,31 @@ clk_domain=system.clk_domain
conf_base=805306368
conf_device_bits=12
conf_size=268435456
+default_p_state=UNDEFINED
eventq_index=0
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pci_dma_base=0
pci_mem_base=0
pci_pio_base=788529152
platform=system.realview
+power_model=Null
system=system
pio=system.iobus.master[2]
[system.realview.realview_io]
type=RealViewCtrl
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
idreg=35979264
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=469827584
pio_latency=100000
+power_model=Null
proc_id0=335544320
proc_id1=335544320
system=system
@@ -1309,12 +1534,17 @@ pio=system.iobus.master[1]
type=PL031
amba_id=3412017
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_delay=100000
int_num=36
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=471269376
pio_latency=100000
+power_model=Null
system=system
time=Thu Jan 1 00:00:00 2009
pio=system.iobus.master[10]
@@ -1323,10 +1553,15 @@ pio=system.iobus.master[10]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=true
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=469893120
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[16]
@@ -1336,12 +1571,17 @@ amba_id=1316868
clk_domain=system.clk_domain
clock0=1000000
clock1=1000000
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num0=34
int_num1=34
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470876160
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[3]
@@ -1351,26 +1591,36 @@ amba_id=1316868
clk_domain=system.clk_domain
clock0=1000000
clock1=1000000
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
int_num0=35
int_num1=35
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470941696
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[4]
[system.realview.uart]
type=Pl011
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
end_on_eot=false
eventq_index=0
gic=system.realview.gic
int_delay=100000
int_num=37
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470351872
pio_latency=100000
platform=system.realview
+power_model=Null
system=system
terminal=system.terminal
pio=system.iobus.master[0]
@@ -1379,10 +1629,15 @@ pio=system.iobus.master[0]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470417408
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[13]
@@ -1390,10 +1645,15 @@ pio=system.iobus.master[13]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470482944
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[14]
@@ -1401,21 +1661,31 @@ pio=system.iobus.master[14]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470548480
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[15]
[system.realview.usb_fake]
type=IsaFake
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
fake_mem=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=452984832
pio_latency=100000
pio_size=131071
+power_model=Null
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
@@ -1429,11 +1699,16 @@ pio=system.iobus.master[20]
[system.realview.vgic]
type=VGic
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
gic=system.realview.gic
hv_addr=738213888
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_delay=10000
platform=system.realview
+power_model=Null
ppint=25
system=system
vcpu_addr=738222080
@@ -1444,11 +1719,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=false
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=402653184:436207615
port=system.iobus.master[11]
@@ -1456,10 +1736,15 @@ port=system.iobus.master[11]
type=AmbaFake
amba_id=0
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
ignore_access=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
pio_addr=470745088
pio_latency=100000
+power_model=Null
system=system
pio=system.iobus.master[17]
@@ -1475,9 +1760,15 @@ port=3456
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
index faa00bf6c..2fb53d936 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simerr
@@ -3,8 +3,11 @@ warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64.
warn: Sockets disabled, not accepting vnc client connections
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
+warn: ClockedObject: Already in the requested power state, request ignored
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
@@ -1505,3 +1508,159 @@ warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
index ffdfb4a34..43fe4b5cc 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 4 2015 11:13:17
-gem5 started Dec 4 2015 11:31:31
-gem5 executing on e104799-lin, pid 30776
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:39:41
+gem5 executing on e108600-lin, pid 23105
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
index e35d19105..3836d4f0c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt
@@ -1,161 +1,161 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 51.821000 # Number of seconds simulated
-sim_ticks 51820999867500 # Number of ticks simulated
-final_tick 51820999867500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.820975 # Number of seconds simulated
+sim_ticks 51820974875500 # Number of ticks simulated
+final_tick 51820974875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 622691 # Simulator instruction rate (inst/s)
-host_op_rate 731741 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 36089691928 # Simulator tick rate (ticks/s)
-host_mem_usage 680680 # Number of bytes of host memory used
-host_seconds 1435.89 # Real time elapsed on the host
-sim_insts 894119248 # Number of instructions simulated
-sim_ops 1050702892 # Number of ops (including micro ops) simulated
+host_inst_rate 496355 # Simulator instruction rate (inst/s)
+host_op_rate 583273 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28752228320 # Simulator tick rate (ticks/s)
+host_mem_usage 675168 # Number of bytes of host memory used
+host_seconds 1802.33 # Real time elapsed on the host
+sim_insts 894595581 # Number of instructions simulated
+sim_ops 1051249500 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.dtb.walker 122816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 126336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 2599472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 26029680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 150208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 131904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2604676 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 25292888 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 407488 # Number of bytes read from this memory
-system.physmem.bytes_read::total 57465468 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2599472 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2604676 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5204148 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 78618432 # Number of bytes written to this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.dtb.walker 122624 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 122112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2604528 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 25895856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 149760 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 136256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2570820 # Number of bytes read from this memory
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system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bytesPerActivate::samples 563401 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 246.102850 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 148.051526 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 287.279361 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 250361 44.44% 44.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 146586 26.02% 70.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 50209 8.91% 79.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 27045 4.80% 84.17% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 18004 3.20% 87.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12090 2.15% 89.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8995 1.60% 91.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7664 1.36% 92.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 42447 7.53% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 563401 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 65697 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 14.273848 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 106.818256 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 65693 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 564009 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 246.035904 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 148.070971 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 287.068931 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 250512 44.42% 44.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 146974 26.06% 70.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 49960 8.86% 79.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 27236 4.83% 84.16% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 18139 3.22% 87.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 12170 2.16% 89.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8948 1.59% 91.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 7660 1.36% 92.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 42410 7.52% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 564009 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 65824 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 14.242267 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 106.817618 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 65819 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 65697 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 65697 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.702878 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.053855 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 6.999985 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 137 0.21% 0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 78 0.12% 0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 60 0.09% 0.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 99 0.15% 0.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 51857 78.93% 79.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 9705 14.77% 94.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 1082 1.65% 95.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 596 0.91% 96.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 852 1.30% 98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 335 0.51% 98.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 83 0.13% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 33 0.05% 98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 55 0.08% 98.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 34 0.05% 98.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 40 0.06% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 30 0.05% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 421 0.64% 99.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 37 0.06% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 32 0.05% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 35 0.05% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 21 0.03% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 5 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.00% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.00% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 4 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 65824 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 65824 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.697481 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.054439 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 6.954009 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 139 0.21% 0.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 76 0.12% 0.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 52 0.08% 0.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 125 0.19% 0.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 51932 78.90% 79.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 9755 14.82% 94.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 1068 1.62% 95.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 579 0.88% 96.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 868 1.32% 98.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 349 0.53% 98.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 83 0.13% 98.79% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::48-51 49 0.07% 98.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 50 0.08% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 24 0.04% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 26 0.04% 99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 422 0.64% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 35 0.05% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 36 0.05% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 31 0.05% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 19 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 4 0.01% 99.89% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 14 0.02% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.00% 99.93% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::128-131 17 0.03% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 8 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 16 0.02% 99.94% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::140-143 6 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 3 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-163 4 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 3 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 65697 # Writes before turning the bus around for reads
-system.physmem.totQLat 12237400086 # Total ticks spent queuing
-system.physmem.totMemAccLat 29820400086 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4688800000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13049.61 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 65824 # Writes before turning the bus around for reads
+system.physmem.totQLat 12248455604 # Total ticks spent queuing
+system.physmem.totMemAccLat 29826355604 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4687440000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 13065.19 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31799.61 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31815.19 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.16 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.52 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s
@@ -317,42 +318,42 @@ system.physmem.busUtil 0.02 # Da
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 7.91 # Average write queue length when enqueuing
-system.physmem.readRowHits 705929 # Number of row buffer hits during reads
-system.physmem.writeRowHits 897152 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.28 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.01 # Row buffer hit rate for writes
-system.physmem.avgGap 23888305.63 # Average gap between requests
+system.physmem.avgWrQLen 9.53 # Average write queue length when enqueuing
+system.physmem.readRowHits 705562 # Number of row buffer hits during reads
+system.physmem.writeRowHits 898659 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.02 # Row buffer hit rate for writes
+system.physmem.avgGap 23869819.32 # Average gap between requests
system.physmem.pageHitRate 73.99 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2146397400 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1171149375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3510585000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3998568240 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1301998363920 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29950494857250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34648015573185 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.609580 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49824747021214 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1730417000000 # Time in different power states
+system.physmem_0.actEnergy 2151787680 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1174090500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3516442800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4008858480 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1301405336775 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29951001041250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34647951683805 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.608648 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49825590774964 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1730416220000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 265835434786 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 264967468786 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2112914160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1152879750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3803904000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3963556800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3384695652000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1301510416275 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29950922881500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34648162204485 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.612409 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49825423536265 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1730417000000 # Time in different power states
+system.physmem_1.actEnergy 2112120360 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1152446625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3795924600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3966356160 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3384694126320 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1300719308715 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29951602820250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34648043103030 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.610412 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49826557272121 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1730416220000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 265157286235 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 264000971629 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory
@@ -369,9 +370,9 @@ system.realview.nvmem.bw_inst_read::total 2 # I
system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s)
-system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.bridge.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.bridge.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
@@ -379,7 +380,7 @@ system.cf0.dma_write_full_pages 1666 # Nu
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -409,66 +410,66 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.cpu0.dtb.walker.walks 133030 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 133030 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 21129 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 95696 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 133019 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 133019 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 133019 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 116836 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 25679.131432 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 22619.213536 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 13703.555245 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 115888 99.19% 99.19% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 821 0.70% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 61 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 31 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.walker.walks 134174 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 134174 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20899 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96911 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 134161 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 134161 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 134161 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 117823 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 25678.780883 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 22579.177668 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 13711.855097 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 116916 99.23% 99.23% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 782 0.66% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 40 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 26 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 116836 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 9230012852 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.024648 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -227501296 -2.46% -2.46% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 9457514148 102.46% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 9230012852 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 95697 81.91% 81.91% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 21129 18.09% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 116826 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 133030 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 117823 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 4912294556 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.048082 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -236192296 -4.81% -4.81% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 5148486852 104.81% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 4912294556 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 96912 82.26% 82.26% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 20899 17.74% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 117811 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 134174 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 133030 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116826 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 134174 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 117811 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116826 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 249856 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 117811 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 251985 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 83528271 # DTB read hits
-system.cpu0.dtb.read_misses 101098 # DTB read misses
-system.cpu0.dtb.write_hits 76299925 # DTB write hits
-system.cpu0.dtb.write_misses 31932 # DTB write misses
+system.cpu0.dtb.read_hits 83610055 # DTB read hits
+system.cpu0.dtb.read_misses 101997 # DTB read misses
+system.cpu0.dtb.write_hits 76232981 # DTB write hits
+system.cpu0.dtb.write_misses 32177 # DTB write misses
system.cpu0.dtb.flush_tlb 51828 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 73224 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 74001 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4644 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 4744 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 9926 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 83629369 # DTB read accesses
-system.cpu0.dtb.write_accesses 76331857 # DTB write accesses
+system.cpu0.dtb.perms_faults 10268 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 83712052 # DTB read accesses
+system.cpu0.dtb.write_accesses 76265158 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 159828196 # DTB hits
-system.cpu0.dtb.misses 133030 # DTB misses
-system.cpu0.dtb.accesses 159961226 # DTB accesses
-system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.cpu0.dtb.hits 159843036 # DTB hits
+system.cpu0.dtb.misses 134174 # DTB misses
+system.cpu0.dtb.accesses 159977210 # DTB accesses
+system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -498,68 +499,74 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.cpu0.itb.walker.walks 78025 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 78025 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4409 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67964 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 78025 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 78025 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 78025 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 72373 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 28767.572161 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 25800.961773 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 15890.832899 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 71328 98.56% 98.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 906 1.25% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 58 0.08% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 43 0.06% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 72373 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.cpu0.itb.walker.walks 79618 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 79618 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4423 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 69406 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 79618 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 79618 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 79618 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 73829 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 28640.046594 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 25708.417232 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 15347.109309 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 36310 49.18% 49.18% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 36530 49.48% 98.66% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 322 0.44% 99.10% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 541 0.73% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 9 0.01% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 50 0.07% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 20 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 14 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 73829 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -294749296 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -294749296 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -294749296 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 67964 93.91% 93.91% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 4409 6.09% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 72373 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 69406 94.01% 94.01% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 4423 5.99% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 73829 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78025 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78025 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79618 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79618 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72373 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72373 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 150398 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 446488504 # ITB inst hits
-system.cpu0.itb.inst_misses 78025 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73829 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73829 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 153447 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 446783848 # ITB inst hits
+system.cpu0.itb.inst_misses 79618 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 51828 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 21506 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 536 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 53747 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 22117 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 537 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 55085 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 446566529 # ITB inst accesses
-system.cpu0.itb.hits 446488504 # DTB hits
-system.cpu0.itb.misses 78025 # DTB misses
-system.cpu0.itb.accesses 446566529 # DTB accesses
-system.cpu0.numPwrStateTransitions 16564 # Number of power state transitions
-system.cpu0.pwrStateClkGateDist::samples 8282 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::mean 6000025981.117725 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::stdev 124621883322.639465 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::underflows 3529 42.61% 42.61% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::1000-5e+10 4688 56.60% 99.22% # Distribution of time spent in the clock gated state
+system.cpu0.itb.inst_accesses 446863466 # ITB inst accesses
+system.cpu0.itb.hits 446783848 # DTB hits
+system.cpu0.itb.misses 79618 # DTB misses
+system.cpu0.itb.accesses 446863466 # DTB accesses
+system.cpu0.numPwrStateTransitions 16584 # Number of power state transitions
+system.cpu0.pwrStateClkGateDist::samples 8292 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::mean 5987638231.190425 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::stdev 124545672847.091751 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::underflows 3540 42.69% 42.69% # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::1000-5e+10 4687 56.52% 99.22% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.23% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 5 0.06% 99.29% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 45 0.54% 99.83% # Distribution of time spent in the clock gated state
@@ -568,510 +575,510 @@ system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.86
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 10 0.12% 100.00% # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::max_value 5700356796932 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateClkGateDist::total 8282 # Distribution of time spent in the clock gated state
-system.cpu0.pwrStateResidencyTicks::ON 2128784691883 # Cumulative time (in ticks) in various power states
-system.cpu0.pwrStateResidencyTicks::CLK_GATED 49692215175617 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 51821574278 # number of cpu cycles simulated
+system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::max_value 5700356716960 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateClkGateDist::total 8292 # Distribution of time spent in the clock gated state
+system.cpu0.pwrStateResidencyTicks::ON 2171478662469 # Cumulative time (in ticks) in various power states
+system.cpu0.pwrStateResidencyTicks::CLK_GATED 49649496213031 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 51821531497 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 16348 # number of quiesce instructions executed
-system.cpu0.committedInsts 446216062 # Number of instructions committed
-system.cpu0.committedOps 524400051 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 481388306 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 440832 # Number of float alu accesses
-system.cpu0.num_func_calls 26357525 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 68205669 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 481388306 # number of integer instructions
-system.cpu0.num_fp_insts 440832 # number of float instructions
-system.cpu0.num_int_register_reads 703333504 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 381971540 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 708271 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 380080 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 117540708 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 117236412 # number of times the CC registers were written
-system.cpu0.num_mem_refs 159819450 # number of memory refs
-system.cpu0.num_load_insts 83525533 # Number of load instructions
-system.cpu0.num_store_insts 76293917 # Number of store instructions
-system.cpu0.num_idle_cycles 50236144373.803871 # Number of idle cycles
-system.cpu0.num_busy_cycles 1585429904.196130 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.030594 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.969406 # Percentage of idle cycles
-system.cpu0.Branches 99643757 # Number of branches fetched
+system.cpu0.kern.inst.quiesce 16350 # number of quiesce instructions executed
+system.cpu0.committedInsts 446506838 # Number of instructions committed
+system.cpu0.committedOps 524620955 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 481485743 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 439185 # Number of float alu accesses
+system.cpu0.num_func_calls 26339620 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 68267650 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 481485743 # number of integer instructions
+system.cpu0.num_fp_insts 439185 # number of float instructions
+system.cpu0.num_int_register_reads 703915697 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 382127275 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 705229 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 378788 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 117675600 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 117367653 # number of times the CC registers were written
+system.cpu0.num_mem_refs 159834987 # number of memory refs
+system.cpu0.num_load_insts 83607531 # Number of load instructions
+system.cpu0.num_store_insts 76227456 # Number of store instructions
+system.cpu0.num_idle_cycles 50234015072.883141 # Number of idle cycles
+system.cpu0.num_busy_cycles 1587516424.116865 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.030634 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.969366 # Percentage of idle cycles
+system.cpu0.Branches 99742938 # Number of branches fetched
system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 363667031 69.31% 69.31% # Class of executed instruction
-system.cpu0.op_class::IntMult 1107197 0.21% 69.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv 49205 0.01% 69.53% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 55532 0.01% 69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction
-system.cpu0.op_class::MemRead 83525533 15.92% 85.46% # Class of executed instruction
-system.cpu0.op_class::MemWrite 76293917 14.54% 100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 363863642 69.32% 69.32% # Class of executed instruction
+system.cpu0.op_class::IntMult 1121256 0.21% 69.53% # Class of executed instruction
+system.cpu0.op_class::IntDiv 48514 0.01% 69.54% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 55488 0.01% 69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction
+system.cpu0.op_class::MemRead 83607531 15.93% 85.48% # Class of executed instruction
+system.cpu0.op_class::MemWrite 76227456 14.52% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 524698416 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.tags.replacements 10234473 # number of replacements
+system.cpu0.op_class::total 524923888 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.replacements 10233133 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.965653 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 310064662 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 10234985 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 30.294589 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.total_refs 310246690 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 10233645 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 30.316343 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 3504381500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 238.684462 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 273.281191 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.466181 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.533752 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 237.355546 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 274.610106 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.463585 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.536348 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 406 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 415 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 1291899613 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 1291899613 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 78014225 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 78760782 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 156775007 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 72354151 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 72480719 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 144834870 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 196883 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 197851 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 394734 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 165349 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data 170410 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 335759 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1859357 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1826349 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 3685706 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2010395 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1982201 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 3992596 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 150533725 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 151411911 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 301945636 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 150730608 # number of overall hits
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-system.cpu0.dcache.overall_hits::total 302340370 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 2625385 # number of ReadReq misses
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-system.cpu0.dcache.WriteReq_misses::cpu0.data 1122925 # number of WriteReq misses
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-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 663805 # number of SoftPFReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total 1312837 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 621975 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data 610318 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 1232293 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 151866 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 156716 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 308582 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses 1292621561 # Number of tag accesses
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system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
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system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 82000 # average StoreCondReq mshr miss latency
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12432.231409 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.077008 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12432.384326 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12432.231409 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015397 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.015397 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015345 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015448 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.015397 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12430.042586 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12432.822270 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12427.291049 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12430.042586 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75674.898551 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75588.315846 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 75805.389222 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75674.898551 # average overall mshr uncacheable latency
-system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1101,75 +1108,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.cpu1.dtb.walker.walks 133445 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 133445 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20908 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 96452 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 13 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 133432 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.299778 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 83.395537 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047 133430 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.walker.walks 131388 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 131388 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20694 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94767 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 12 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 131376 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.304470 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 84.045560 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047 131374 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 133432 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 117373 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 25894.485955 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 22861.122715 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13849.356083 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 74140 63.17% 63.17% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 42199 35.95% 99.12% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303 555 0.47% 99.59% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071 343 0.29% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-163839 6 0.01% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607 48 0.04% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375 11 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143 29 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911 23 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 117373 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 6007861436 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 1.129422 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 -777548296 -12.94% -12.94% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 6785409732 112.94% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 6007861436 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 96452 82.18% 82.18% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 20908 17.82% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 117360 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 133445 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 131376 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 115473 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 25989.651260 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 22881.227305 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14446.882730 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 114392 99.06% 99.06% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 917 0.79% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 63 0.05% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 52 0.05% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 33 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 115473 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 5991401436 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 1.130704 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 -783101296 -13.07% -13.07% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 6774502732 113.07% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 5991401436 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 94767 82.08% 82.08% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 20694 17.92% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 115461 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 131388 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 133445 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 117360 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 131388 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 115461 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 117360 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 250805 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 115461 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 246849 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 84301684 # DTB read hits
-system.cpu1.dtb.read_misses 101780 # DTB read misses
-system.cpu1.dtb.write_hits 76371214 # DTB write hits
-system.cpu1.dtb.write_misses 31665 # DTB write misses
+system.cpu1.dtb.read_hits 84308595 # DTB read hits
+system.cpu1.dtb.read_misses 100203 # DTB read misses
+system.cpu1.dtb.write_hits 76530288 # DTB write hits
+system.cpu1.dtb.write_misses 31185 # DTB write misses
system.cpu1.dtb.flush_tlb 51822 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 73965 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 73106 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4498 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 4660 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 10027 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 84403464 # DTB read accesses
-system.cpu1.dtb.write_accesses 76402879 # DTB write accesses
+system.cpu1.dtb.perms_faults 9685 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 84408798 # DTB read accesses
+system.cpu1.dtb.write_accesses 76561473 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 160672898 # DTB hits
-system.cpu1.dtb.misses 133445 # DTB misses
-system.cpu1.dtb.accesses 160806343 # DTB accesses
-system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.cpu1.dtb.hits 160838883 # DTB hits
+system.cpu1.dtb.misses 131388 # DTB misses
+system.cpu1.dtb.accesses 160970271 # DTB accesses
+system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -1199,150 +1201,144 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.cpu1.itb.walker.walks 78111 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 78111 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 68231 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 78111 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 78111 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 78111 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 72561 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28942.620692 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25930.573552 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 16143.079615 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 35934 49.52% 49.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 35483 48.90% 98.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 386 0.53% 98.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 612 0.84% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 10 0.01% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 47 0.06% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 20 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 12 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 72561 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.cpu1.itb.walker.walks 76510 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 76510 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4384 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66713 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 76510 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 76510 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 76510 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 71097 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29111.284583 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 26008.835767 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 16533.926039 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 69890 98.30% 98.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 1057 1.49% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 63 0.09% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.08% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 18 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 71097 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples -850152296 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 -850152296 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total -850152296 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 68231 94.03% 94.03% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 4330 5.97% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 72561 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 66713 93.83% 93.83% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 4384 6.17% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 71097 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 78111 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 78111 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 76510 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 76510 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72561 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72561 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 150672 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 448183312 # ITB inst hits
-system.cpu1.itb.inst_misses 78111 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71097 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71097 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 147607 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 448364539 # ITB inst hits
+system.cpu1.itb.inst_misses 76510 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 51822 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 21521 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 531 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 53921 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 20910 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 530 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 52840 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 448261423 # ITB inst accesses
-system.cpu1.itb.hits 448183312 # DTB hits
-system.cpu1.itb.misses 78111 # DTB misses
-system.cpu1.itb.accesses 448261423 # DTB accesses
-system.cpu1.numPwrStateTransitions 16084 # Number of power state transitions
-system.cpu1.pwrStateClkGateDist::samples 8042 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::mean 6194937221.007833 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::stdev 118254200557.171326 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::underflows 3517 43.73% 43.73% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::1000-5e+10 4458 55.43% 99.17% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.06% 99.23% # Distribution of time spent in the clock gated state
+system.cpu1.itb.inst_accesses 448441049 # ITB inst accesses
+system.cpu1.itb.hits 448364539 # DTB hits
+system.cpu1.itb.misses 76510 # DTB misses
+system.cpu1.itb.accesses 448441049 # DTB accesses
+system.cpu1.numPwrStateTransitions 16068 # Number of power state transitions
+system.cpu1.pwrStateClkGateDist::samples 8034 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::mean 6192978089.022779 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::stdev 118311828609.490631 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::underflows 3509 43.68% 43.68% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::1000-5e+10 4459 55.50% 99.18% # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.05% 99.23% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 45 0.56% 99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 13 0.16% 100.00% # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::max_value 3977581677820 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateClkGateDist::total 8042 # Distribution of time spent in the clock gated state
-system.cpu1.pwrStateResidencyTicks::ON 2001314736155 # Cumulative time (in ticks) in various power states
-system.cpu1.pwrStateResidencyTicks::CLK_GATED 49819685131345 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 51820425457 # number of cpu cycles simulated
+system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::max_value 3977581604528 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateClkGateDist::total 8034 # Distribution of time spent in the clock gated state
+system.cpu1.pwrStateResidencyTicks::ON 2066588908291 # Cumulative time (in ticks) in various power states
+system.cpu1.pwrStateResidencyTicks::CLK_GATED 49754385967209 # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles 51820418254 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.committedInsts 447903186 # Number of instructions committed
-system.cpu1.committedOps 526302841 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 483164392 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 453837 # Number of float alu accesses
-system.cpu1.num_func_calls 26485275 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 68482317 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 483164392 # number of integer instructions
-system.cpu1.num_fp_insts 453837 # number of float instructions
-system.cpu1.num_int_register_reads 704985819 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 383399771 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 733419 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 379508 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 118000089 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 117710485 # number of times the CC registers were written
-system.cpu1.num_mem_refs 160666503 # number of memory refs
-system.cpu1.num_load_insts 84298667 # Number of load instructions
-system.cpu1.num_store_insts 76367836 # Number of store instructions
-system.cpu1.num_idle_cycles 50233099437.419525 # Number of idle cycles
-system.cpu1.num_busy_cycles 1587326019.580469 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.030631 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.969369 # Percentage of idle cycles
-system.cpu1.Branches 100046269 # Number of branches fetched
+system.cpu1.committedInsts 448088743 # Number of instructions committed
+system.cpu1.committedOps 526628545 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 483582453 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 455004 # Number of float alu accesses
+system.cpu1.num_func_calls 26546962 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 68480445 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 483582453 # number of integer instructions
+system.cpu1.num_fp_insts 455004 # number of float instructions
+system.cpu1.num_int_register_reads 705060671 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 383633333 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 735821 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 380160 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 117946404 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 117660346 # number of times the CC registers were written
+system.cpu1.num_mem_refs 160831979 # number of memory refs
+system.cpu1.num_load_insts 84305574 # Number of load instructions
+system.cpu1.num_store_insts 76526405 # Number of store instructions
+system.cpu1.num_idle_cycles 50231588268.978668 # Number of idle cycles
+system.cpu1.num_busy_cycles 1588829985.021333 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.030660 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.969340 # Percentage of idle cycles
+system.cpu1.Branches 100054364 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 364713411 69.26% 69.26% # Class of executed instruction
-system.cpu1.op_class::IntMult 1116791 0.21% 69.47% # Class of executed instruction
-system.cpu1.op_class::IntDiv 48530 0.01% 69.48% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 54891 0.01% 69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction
-system.cpu1.op_class::MemRead 84298667 16.01% 85.50% # Class of executed instruction
-system.cpu1.op_class::MemWrite 76367836 14.50% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 364882138 69.25% 69.25% # Class of executed instruction
+system.cpu1.op_class::IntMult 1103160 0.21% 69.46% # Class of executed instruction
+system.cpu1.op_class::IntDiv 49288 0.01% 69.47% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 54935 0.01% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::MemRead 84305574 16.00% 85.48% # Class of executed instruction
+system.cpu1.op_class::MemWrite 76526405 14.52% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 526600168 # Class of executed instruction
-system.iobus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.iobus.trans_dist::ReadReq 40318 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40318 # Transaction distribution
+system.cpu1.op_class::total 526921542 # Class of executed instruction
+system.iobus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.iobus.trans_dist::ReadReq 40309 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40309 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
@@ -1359,11 +1355,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230994 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230994 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230976 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230976 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353778 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353760 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
@@ -1378,16 +1374,16 @@ system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334408 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334408 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334336 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334336 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492328 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 42147500 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7492256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 42146500 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 323000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
@@ -1405,75 +1401,75 @@ system.iobus.reqLayer16.occupancy 17000 # La
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 25749000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 25738000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 38609000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.occupancy 38603500 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 568885533 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 568948940 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147754000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147736000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.iocache.tags.replacements 115478 # number of replacements
-system.iocache.tags.tagsinuse 10.457315 # Cycle average of tags in use
+system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.iocache.tags.replacements 115469 # number of replacements
+system.iocache.tags.tagsinuse 10.457310 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115494 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115485 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13153888090000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.warmup_cycle 13153887286000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 3.511180 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.946135 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.946130 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.219449 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.434133 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.653582 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.009922 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.779536 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.784165 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.781844 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.245375 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.241261 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.243340 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005704 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041166 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040639 # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.416724 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.409113 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.412955 # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007732 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011743 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.090803 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009312 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012201 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.087625 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.037673 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007732 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011743 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005687 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.090803 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009312 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012201 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005721 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.087625 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.037673 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 76900.975786 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18924.669801 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18923.291377 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18923.975877 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 36166.666667 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.242388 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.244614 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.243487 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.005673 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.041323 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.039844 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.040577 # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.416990 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.409972 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total 0.413518 # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007652 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.037667 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007652 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011143 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005701 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.090294 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.009426 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012829 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005644 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.088178 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.037667 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 77153.623538 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18916.583027 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18919.496014 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18918.039642 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 44500 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 70500 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 44750 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72050.491966 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71881.386450 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 71967.562553 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72781.640257 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74479.073353 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74378.277580 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74428.910610 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18671.781922 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18663.857839 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18667.893869 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76169.880146 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78131.965552 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72959.780575 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72883.868824 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75604.388581 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77879.184862 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72606.251420 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72754.639228 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 72854.824694 # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 53166.666667 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 72001.797054 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71983.378667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 71992.661792 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 72797.017293 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 74403.995372 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 74590.725350 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74496.407757 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 18670.722173 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 18670.205788 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 18670.468860 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76887.787056 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78477.987421 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72910.283960 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 72833.398851 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76587.179487 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76828.558008 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72683.762214 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72883.433794 # average overall mshr miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173784.623188 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174050.071960 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171027.320470 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.538572 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170778.479154 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 111091.017948 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63088.315846 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91362.585482 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 91655.635204 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63305.389222 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81557.769149 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.649234 # average overall mshr uncacheable latency
-system.membus.snoop_filter.tot_requests 2972233 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 1487104 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 3352 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81354.933005 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 77213.287378 # average overall mshr uncacheable latency
+system.membus.snoop_filter.tot_requests 2973114 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 1487263 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 3311 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 76831 # Transaction distribution
-system.membus.trans_dist::ReadResp 450834 # Transaction distribution
+system.membus.trans_dist::ReadResp 449832 # Transaction distribution
system.membus.trans_dist::WriteReq 33710 # Transaction distribution
system.membus.trans_dist::WriteResp 33710 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 1228413 # Transaction distribution
-system.membus.trans_dist::CleanEvict 193324 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 36554 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution
+system.membus.trans_dist::WritebackDirty 1230432 # Transaction distribution
+system.membus.trans_dist::CleanEvict 191908 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36440 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
-system.membus.trans_dist::ReadExReq 524356 # Transaction distribution
-system.membus.trans_dist::ReadExResp 524356 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 374003 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 615538 # Transaction distribution
+system.membus.trans_dist::ReadExReq 524978 # Transaction distribution
+system.membus.trans_dist::ReadExResp 524978 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 373001 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 616319 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721390 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 3851094 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237382 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 237382 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4088476 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3721926 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 3851630 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237395 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 237395 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4089025 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128872672 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 129042522 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7231808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7231808 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 136274330 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3165 # Total snoops (count)
-system.membus.snoop_fanout::samples 1660996 # Request fanout histogram
-system.membus.snoop_fanout::mean 0.019349 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.137749 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 128978144 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 129147994 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7233792 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 136381786 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3125 # Total snoops (count)
+system.membus.snoopTraffic 199488 # Total snoop traffic (bytes)
+system.membus.snoop_fanout::samples 1661282 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.019128 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.136975 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1628857 98.07% 98.07% # Request fanout histogram
-system.membus.snoop_fanout::1 32139 1.93% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1629505 98.09% 98.09% # Request fanout histogram
+system.membus.snoop_fanout::1 31777 1.91% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 1660996 # Request fanout histogram
-system.membus.reqLayer0.occupancy 106934500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 1661282 # Request fanout histogram
+system.membus.reqLayer0.occupancy 106916500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5678000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5690500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8069625955 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 8079257005 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4926078787 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4924178426 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 44722660 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 44658046 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
-system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
@@ -2173,85 +2170,86 @@ system.realview.ethernet.totalRxOrn 0 # to
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
+system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
-system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.snoop_filter.tot_requests 48668708 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 24647917 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1743 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 2076 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 2076 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.snoop_filter.tot_requests 48659442 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 24643437 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 1748 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 2028 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 2028 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820999867500 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadReq 1292402 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 21924695 # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51820974875500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadReq 1290012 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 21916025 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackDirty 9016681 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 13785272 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2525177 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 45989 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 45993 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 2157137 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 2157137 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 13785789 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 6848293 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1261037 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1232293 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41443100 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30932231 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796412 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1256395 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 74428138 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764720404 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081696966 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2696152 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 4001736 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2853115258 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1718109 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 26731746 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.021922 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.146427 # Request fanout histogram
+system.toL2Bus.trans_dist::WritebackDirty 9018905 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 13781825 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2522217 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 45883 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 45886 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2158380 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2158380 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 13782342 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 6845459 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1260926 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1232503 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 41432759 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 30927957 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 796484 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1252515 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 74409715 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1764279188 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1081608326 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2697464 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3989080 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2852574058 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1717339 # Total snoops (count)
+system.toL2Bus.snoopTraffic 74998872 # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples 26724704 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.021941 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.146492 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 26145745 97.81% 97.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 586001 2.19% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 26138332 97.81% 97.81% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 586372 2.19% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 26731746 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 46403347500 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 26724704 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 46394070000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1695386 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 1633889 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 20721808500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 20716638000 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 14193795462 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 14191518968 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 459393000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 459301000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 756178000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 753880000 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
index b028e910d..d74b75b2a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/system.terminal
@@ -32,135 +32,135 @@
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
-[ 0.000045] Console: colour dummy device 80x25
-[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
-[ 0.000051] pid_max: default: 32768 minimum: 301
-[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
-[ 0.000352] hw perfevents: no hardware support available
-[ 1.060142] CPU1: failed to come online
-[ 2.080279] CPU2: failed to come online
-[ 3.100417] CPU3: failed to come online
-[ 3.100422] Brought up 1 CPUs
-[ 3.100424] SMP: Total of 1 processors activated.
-[ 3.100540] devtmpfs: initialized
-[ 3.101655] atomic64_test: passed
-[ 3.101743] regulator-dummy: no parameters
-[ 3.102586] NET: Registered protocol family 16
-[ 3.102876] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
-[ 3.102889] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
-[ 3.105209] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
-[ 3.105217] Serial: AMBA PL011 UART driver
-[ 3.105613] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
-[ 3.105686] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
-[ 3.106271] console [ttyAMA0] enabled
-[ 3.106418] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
-[ 3.106468] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
-[ 3.106518] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
-[ 3.106564] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
-[ 3.130865] 3V3: 3300 mV
-[ 3.130952] vgaarb: loaded
-[ 3.131049] SCSI subsystem initialized
-[ 3.131123] libata version 3.00 loaded.
-[ 3.131214] usbcore: registered new interface driver usbfs
-[ 3.131242] usbcore: registered new interface driver hub
-[ 3.131299] usbcore: registered new device driver usb
-[ 3.131346] pps_core: LinuxPPS API ver. 1 registered
-[ 3.131356] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
-[ 3.131380] PTP clock support registered
-[ 3.131622] Switched to clocksource arch_sys_counter
-[ 3.133833] NET: Registered protocol family 2
-[ 3.133999] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
-[ 3.134032] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
-[ 3.134072] TCP: Hash tables configured (established 2048 bind 2048)
-[ 3.134126] TCP: reno registered
-[ 3.134134] UDP hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134154] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
-[ 3.134230] NET: Registered protocol family 1
-[ 3.134310] RPC: Registered named UNIX socket transport module.
-[ 3.134320] RPC: Registered udp transport module.
-[ 3.134329] RPC: Registered tcp transport module.
-[ 3.134338] RPC: Registered tcp NFSv4.1 backchannel transport module.
-[ 3.134352] PCI: CLS 0 bytes, default 64
-[ 3.134697] futex hash table entries: 1024 (order: 4, 65536 bytes)
-[ 3.134933] HugeTLB registered 2 MB page size, pre-allocated 0 pages
-[ 3.138705] fuse init (API version 7.23)
-[ 3.138877] msgmni has been set to 469
-[ 3.143640] io scheduler noop registered
-[ 3.143737] io scheduler cfq registered (default)
-[ 3.144797] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
-[ 3.144812] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
-[ 3.144825] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
-[ 3.144839] pci_bus 0000:00: root bus resource [bus 00-ff]
-[ 3.144850] pci_bus 0000:00: scanning bus
-[ 3.144865] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
-[ 3.144880] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
-[ 3.144898] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.144963] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
-[ 3.144977] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
-[ 3.144989] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
-[ 3.145002] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
-[ 3.145014] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
-[ 3.145027] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
-[ 3.145041] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
-[ 3.145103] pci_bus 0000:00: fixups for bus
-[ 3.145112] pci_bus 0000:00: bus scan returning with max=00
-[ 3.145127] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
-[ 3.145154] pci 0000:00:00.0: fixup irq: got 33
-[ 3.145164] pci 0000:00:00.0: assigning IRQ 33
-[ 3.145178] pci 0000:00:01.0: fixup irq: got 34
-[ 3.145188] pci 0000:00:01.0: assigning IRQ 34
-[ 3.145202] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
-[ 3.145217] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
-[ 3.145232] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
-[ 3.145246] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
-[ 3.145260] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
-[ 3.145273] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
-[ 3.145286] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
-[ 3.145300] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
-[ 3.146216] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
-[ 3.146745] ata_piix 0000:00:01.0: version 2.13
-[ 3.146757] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
-[ 3.146801] ata_piix 0000:00:01.0: enabling bus mastering
-[ 3.147406] scsi0 : ata_piix
-[ 3.147592] scsi1 : ata_piix
-[ 3.147648] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
-[ 3.147661] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
-[ 3.147864] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
-[ 3.147877] e1000: Copyright (c) 1999-2006 Intel Corporation.
-[ 3.147899] e1000 0000:00:00.0: enabling device (0000 -> 0002)
-[ 3.147912] e1000 0000:00:00.0: enabling bus mastering
-[ 3.301659] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
-[ 3.301670] ata1.00: 2096640 sectors, multi 0: LBA
-[ 3.301706] ata1.00: configured for UDMA/33
-[ 3.301793] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
-[ 3.301991] sd 0:0:0:0: Attached scsi generic sg0 type 0
-[ 3.302026] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
-[ 3.302084] sd 0:0:0:0: [sda] Write Protect is off
-[ 3.302095] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
-[ 3.302124] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
-[ 3.302327] sda: sda1
-[ 3.302534] sd 0:0:0:0: [sda] Attached SCSI disk
-[ 3.421985] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
-[ 3.422000] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
-[ 3.422029] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
-[ 3.422040] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
-[ 3.422072] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
-[ 3.422084] igb: Copyright (c) 2007-2014 Intel Corporation.
-[ 3.422216] usbcore: registered new interface driver usb-storage
-[ 3.422310] mousedev: PS/2 mouse device common for all mice
-[ 3.422604] usbcore: registered new interface driver usbhid
-[ 3.422615] usbhid: USB HID core driver
-[ 3.422670] TCP: cubic registered
-[ 3.422680] NET: Registered protocol family 17
-
-[ 3.423358] devtmpfs: mounted
-[ 3.423483] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
+[ 0.000039] Console: colour dummy device 80x25
+[ 0.000042] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
+[ 0.000044] pid_max: default: 32768 minimum: 301
+[ 0.000065] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000067] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)
+[ 0.000247] hw perfevents: no hardware support available
+[ 1.060141] CPU1: failed to come online
+[ 2.080278] CPU2: failed to come online
+[ 3.100415] CPU3: failed to come online
+[ 3.100420] Brought up 1 CPUs
+[ 3.100422] SMP: Total of 1 processors activated.
+[ 3.100519] devtmpfs: initialized
+[ 3.101579] atomic64_test: passed
+[ 3.101653] regulator-dummy: no parameters
+[ 3.102392] NET: Registered protocol family 16
+[ 3.102653] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000
+[ 3.102663] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.
+[ 3.103271] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]
+[ 3.103277] Serial: AMBA PL011 UART driver
+[ 3.103628] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000
+[ 3.103692] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3
+[ 3.104278] console [ttyAMA0] enabled
+[ 3.104379] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000
+[ 3.104429] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000
+[ 3.104479] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000
+[ 3.104525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000
+[ 3.131020] 3V3: 3300 mV
+[ 3.131093] vgaarb: loaded
+[ 3.131183] SCSI subsystem initialized
+[ 3.131252] libata version 3.00 loaded.
+[ 3.131332] usbcore: registered new interface driver usbfs
+[ 3.131358] usbcore: registered new interface driver hub
+[ 3.131413] usbcore: registered new device driver usb
+[ 3.131456] pps_core: LinuxPPS API ver. 1 registered
+[ 3.131466] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
+[ 3.131488] PTP clock support registered
+[ 3.131706] Switched to clocksource arch_sys_counter
+[ 3.133706] NET: Registered protocol family 2
+[ 3.133856] TCP established hash table entries: 2048 (order: 2, 16384 bytes)
+[ 3.133884] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)
+[ 3.133918] TCP: Hash tables configured (established 2048 bind 2048)
+[ 3.133940] TCP: reno registered
+[ 3.133948] UDP hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.133966] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
+[ 3.134029] NET: Registered protocol family 1
+[ 3.134094] RPC: Registered named UNIX socket transport module.
+[ 3.134105] RPC: Registered udp transport module.
+[ 3.134113] RPC: Registered tcp transport module.
+[ 3.134122] RPC: Registered tcp NFSv4.1 backchannel transport module.
+[ 3.134136] PCI: CLS 0 bytes, default 64
+[ 3.134445] futex hash table entries: 1024 (order: 4, 65536 bytes)
+[ 3.134644] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 3.138048] fuse init (API version 7.23)
+[ 3.138207] msgmni has been set to 469
+[ 3.142619] io scheduler noop registered
+[ 3.142717] io scheduler cfq registered (default)
+[ 3.143500] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00
+[ 3.143514] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
+[ 3.143527] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]
+[ 3.143541] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 3.143553] pci_bus 0000:00: scanning bus
+[ 3.143566] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000
+[ 3.143581] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]
+[ 3.143598] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143658] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185
+[ 3.143672] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]
+[ 3.143684] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]
+[ 3.143697] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]
+[ 3.143710] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]
+[ 3.143722] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]
+[ 3.143736] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]
+[ 3.143793] pci_bus 0000:00: fixups for bus
+[ 3.143803] pci_bus 0000:00: bus scan returning with max=00
+[ 3.143817] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc
+[ 3.143842] pci 0000:00:00.0: fixup irq: got 33
+[ 3.143852] pci 0000:00:00.0: assigning IRQ 33
+[ 3.143866] pci 0000:00:01.0: fixup irq: got 34
+[ 3.143875] pci 0000:00:01.0: assigning IRQ 34
+[ 3.143889] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]
+[ 3.143904] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]
+[ 3.143919] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]
+[ 3.143933] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]
+[ 3.143946] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]
+[ 3.143960] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]
+[ 3.143973] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]
+[ 3.143986] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]
+[ 3.144848] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+[ 3.145335] ata_piix 0000:00:01.0: version 2.13
+[ 3.145347] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)
+[ 3.145377] ata_piix 0000:00:01.0: enabling bus mastering
+[ 3.145943] scsi0 : ata_piix
+[ 3.146120] scsi1 : ata_piix
+[ 3.146172] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34
+[ 3.146185] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34
+[ 3.146369] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI
+[ 3.146383] e1000: Copyright (c) 1999-2006 Intel Corporation.
+[ 3.146404] e1000 0000:00:00.0: enabling device (0000 -> 0002)
+[ 3.146418] e1000 0000:00:00.0: enabling bus mastering
+[ 3.301739] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66
+[ 3.301750] ata1.00: 2096640 sectors, multi 0: LBA
+[ 3.301784] ata1.00: configured for UDMA/33
+[ 3.301855] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
+[ 3.302047] sd 0:0:0:0: Attached scsi generic sg0 type 0
+[ 3.302082] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)
+[ 3.302139] sd 0:0:0:0: [sda] Write Protect is off
+[ 3.302150] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
+[ 3.302179] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
+[ 3.302375] sda: sda1
+[ 3.302573] sd 0:0:0:0: [sda] Attached SCSI disk
+[ 3.422060] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01
+[ 3.422074] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection
+[ 3.422104] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k
+[ 3.422115] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.
+[ 3.422145] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k
+[ 3.422158] igb: Copyright (c) 2007-2014 Intel Corporation.
+[ 3.422288] usbcore: registered new interface driver usb-storage
+[ 3.422377] mousedev: PS/2 mouse device common for all mice
+[ 3.422663] usbcore: registered new interface driver usbhid
+[ 3.422673] usbhid: USB HID core driver
+[ 3.422723] TCP: cubic registered
+[ 3.422732] NET: Registered protocol family 17
+
+[ 3.423356] devtmpfs: mounted
+[ 3.423405] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)
-[ 3.470485] udevd[607]: starting version 182
+[ 3.470207] udevd[607]: starting version 182
Starting Bootlog daemon: bootlogd.
-[ 3.586582] random: dd urandom read with 21 bits of entropy available
+[ 3.606569] random: dd urandom read with 21 bits of entropy available
Populating dev cache
net.ipv4.conf.default.rp_filter = 1
net.ipv4.conf.all.rp_filter = 1
@@ -168,8 +168,8 @@ hwclock: can't open '/dev/misc/rtc': No such file or directory
Mon Jan 27 08:00:00 UTC 2014
hwclock: can't open '/dev/misc/rtc': No such file or directory
INIT: Entering runlevel: 5
-Configuring network interfaces... udhcpc (v1.21.1) started
-[ 3.781859] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+Configuring network interfaces... [ 3.791940] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
+udhcpc (v1.21.1) started
Sending discover...
Sending discover...
Sending discover...
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-05 16:14:57 +0000