diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:50 -0400 |
| commit | 57e5401d954d46fea45ca3eaafa8ae655659da39 (patch) | |
| tree | 7108ae4d529338b13daa49308c85bb7a680f7b58 /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | aa329f4757639820f921bf4152c21e79da74c034 (diff) | |
| download | gem5-57e5401d954d46fea45ca3eaafa8ae655659da39.tar.xz | |
stats: Bump stats for the fixes, and mostly DRAM controller changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
6 files changed, 7950 insertions, 7723 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 5f9799ffe..2c9e78fdf 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526170 # Number of seconds simulated -sim_ticks 2526169857500 # Number of ticks simulated -final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526192 # Number of seconds simulated +sim_ticks 2526192217500 # Number of ticks simulated +final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46796 # Simulator instruction rate (inst/s) -host_op_rate 60213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1960134913 # Simulator tick rate (ticks/s) -host_mem_usage 468616 # Number of bytes of host memory used -host_seconds 1288.77 # Real time elapsed on the host -sim_insts 60309637 # Number of instructions simulated -sim_ops 77601213 # Number of ops (including micro ops) simulated +host_inst_rate 45758 # Simulator instruction rate (inst/s) +host_op_rate 58877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1916680323 # Simulator tick rate (ticks/s) +host_mem_usage 469072 # Number of bytes of host memory used +host_seconds 1318.00 # Real time elapsed on the host +sim_insts 60309034 # Number of instructions simulated +sim_ops 77600502 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096868 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943297 # Per bank write bursts -system.physmem.perBankRdBursts::1 937033 # Per bank write bursts -system.physmem.perBankRdBursts::2 936962 # Per bank write bursts -system.physmem.perBankRdBursts::3 936535 # Per bank write bursts -system.physmem.perBankRdBursts::4 942693 # Per bank write bursts -system.physmem.perBankRdBursts::5 936569 # Per bank write bursts -system.physmem.perBankRdBursts::6 936319 # Per bank write bursts -system.physmem.perBankRdBursts::7 936043 # Per bank write bursts -system.physmem.perBankRdBursts::8 943596 # Per bank write bursts -system.physmem.perBankRdBursts::9 936992 # Per bank write bursts -system.physmem.perBankRdBursts::10 936414 # Per bank write bursts -system.physmem.perBankRdBursts::11 935912 # Per bank write bursts -system.physmem.perBankRdBursts::12 943556 # Per bank write bursts -system.physmem.perBankRdBursts::13 937007 # Per bank write bursts -system.physmem.perBankRdBursts::14 937039 # Per bank write bursts -system.physmem.perBankRdBursts::15 936676 # Per bank write bursts -system.physmem.perBankWrBursts::0 6606 # Per bank write bursts -system.physmem.perBankWrBursts::1 6375 # Per bank write bursts -system.physmem.perBankWrBursts::2 6521 # Per bank write bursts -system.physmem.perBankWrBursts::3 6552 # Per bank write bursts -system.physmem.perBankWrBursts::4 6461 # Per bank write bursts -system.physmem.perBankWrBursts::5 6711 # Per bank write bursts -system.physmem.perBankWrBursts::6 6720 # Per bank write bursts -system.physmem.perBankWrBursts::7 6668 # Per bank write bursts -system.physmem.perBankWrBursts::8 7045 # Per bank write bursts -system.physmem.perBankWrBursts::9 6826 # Per bank write bursts -system.physmem.perBankWrBursts::10 6497 # Per bank write bursts -system.physmem.perBankWrBursts::11 6136 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 6672 # Per bank write bursts -system.physmem.perBankWrBursts::14 6956 # Per bank write bursts -system.physmem.perBankWrBursts::15 6819 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096864 # Number of read requests accepted +system.physmem.writeReqs 813148 # Number of write requests accepted +system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue +system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943480 # Per bank write bursts +system.physmem.perBankRdBursts::1 937980 # Per bank write bursts +system.physmem.perBankRdBursts::2 937559 # Per bank write bursts +system.physmem.perBankRdBursts::3 937528 # Per bank write bursts +system.physmem.perBankRdBursts::4 943087 # Per bank write bursts +system.physmem.perBankRdBursts::5 937982 # Per bank write bursts +system.physmem.perBankRdBursts::6 937070 # Per bank write bursts +system.physmem.perBankRdBursts::7 936990 # Per bank write bursts +system.physmem.perBankRdBursts::8 943982 # Per bank write bursts +system.physmem.perBankRdBursts::9 938303 # Per bank write bursts +system.physmem.perBankRdBursts::10 937119 # Per bank write bursts +system.physmem.perBankRdBursts::11 936407 # Per bank write bursts +system.physmem.perBankRdBursts::12 943924 # Per bank write bursts +system.physmem.perBankRdBursts::13 938214 # Per bank write bursts +system.physmem.perBankRdBursts::14 937241 # Per bank write bursts +system.physmem.perBankRdBursts::15 937211 # Per bank write bursts +system.physmem.perBankWrBursts::0 6601 # Per bank write bursts +system.physmem.perBankWrBursts::1 6388 # Per bank write bursts +system.physmem.perBankWrBursts::2 6528 # Per bank write bursts +system.physmem.perBankWrBursts::3 6554 # Per bank write bursts +system.physmem.perBankWrBursts::4 6464 # Per bank write bursts +system.physmem.perBankWrBursts::5 6726 # Per bank write bursts +system.physmem.perBankWrBursts::6 6713 # Per bank write bursts +system.physmem.perBankWrBursts::7 6652 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 6461 # Per bank write bursts +system.physmem.perBankWrBursts::11 6104 # Per bank write bursts +system.physmem.perBankWrBursts::12 7064 # Per bank write bursts +system.physmem.perBankWrBursts::13 6684 # Per bank write bursts +system.physmem.perBankWrBursts::14 6965 # Per bank write bursts +system.physmem.perBankWrBursts::15 6836 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526168741500 # Total gap between requests +system.physmem.totGap 2526191083500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154622 # Read request sizes (log2) +system.physmem.readPktSize::6 154618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59130 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,47 +159,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 534 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -208,67 +208,50 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads -system.physmem.totQLat 571195583500 # Total ticks spent queuing -system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks -system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads +system.physmem.totQLat 389908010000 # Total ticks spent queuing +system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -276,15 +259,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing -system.physmem.readRowHits 14041195 # Number of row buffer hits during reads -system.physmem.writeRowHits 91389 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes -system.physmem.avgGap 158778.41 # Average gap between requests -system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing +system.physmem.readRowHits 14044000 # Number of row buffer hits during reads +system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes +system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states +system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -297,50 +284,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54878638 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149508 # Transaction distribution -system.membus.trans_dist::ReadResp 16149508 # Transaction distribution +system.membus.throughput 54877773 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149486 # Transaction distribution +system.membus.trans_dist::ReadResp 16149486 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59130 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution +system.membus.trans_dist::ReadExReq 131451 # Transaction distribution +system.membus.trans_dist::ReadExResp 131451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138632762 # Total data (bytes) +system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631802 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -348,7 +335,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266001 # Throughput (bytes/s) +system.iobus.throughput 48265574 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution @@ -458,18 +445,18 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14755327 # Number of BP lookups -system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits +system.cpu.branchPred.lookups 14753661 # Number of BP lookups +system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -493,9 +480,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987589 # DTB read hits -system.cpu.checker.dtb.read_misses 7306 # DTB read misses -system.cpu.checker.dtb.write_hits 11227681 # DTB write hits +system.cpu.checker.dtb.read_hits 14987453 # DTB read hits +system.cpu.checker.dtb.read_misses 7308 # DTB read misses +system.cpu.checker.dtb.write_hits 11227597 # DTB write hits system.cpu.checker.dtb.write_misses 2191 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -506,12 +493,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994895 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229872 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994761 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229788 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215270 # DTB hits -system.cpu.checker.dtb.misses 9497 # DTB misses -system.cpu.checker.dtb.accesses 26224767 # DTB accesses +system.cpu.checker.dtb.hits 26215050 # DTB hits +system.cpu.checker.dtb.misses 9499 # DTB misses +system.cpu.checker.dtb.accesses 26224549 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -533,7 +520,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61483612 # ITB inst hits +system.cpu.checker.itb.inst_hits 61483008 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -550,11 +537,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61488085 # ITB inst accesses -system.cpu.checker.itb.hits 61483612 # DTB hits +system.cpu.checker.itb.inst_accesses 61487481 # ITB inst accesses +system.cpu.checker.itb.hits 61483008 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61488085 # DTB accesses -system.cpu.checker.numCycles 77887007 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61487481 # DTB accesses +system.cpu.checker.numCycles 77886295 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -580,25 +567,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51187284 # DTB read hits -system.cpu.dtb.read_misses 65383 # DTB read misses -system.cpu.dtb.write_hits 11703682 # DTB write hits -system.cpu.dtb.write_misses 15916 # DTB write misses +system.cpu.dtb.read_hits 51183231 # DTB read hits +system.cpu.dtb.read_misses 65223 # DTB read misses +system.cpu.dtb.write_hits 11700953 # DTB write hits +system.cpu.dtb.write_misses 15725 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252667 # DTB read accesses -system.cpu.dtb.write_accesses 11719598 # DTB write accesses +system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51248454 # DTB read accesses +system.cpu.dtb.write_accesses 11716678 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62890966 # DTB hits -system.cpu.dtb.misses 81299 # DTB misses -system.cpu.dtb.accesses 62972265 # DTB accesses +system.cpu.dtb.hits 62884184 # DTB hits +system.cpu.dtb.misses 80948 # DTB misses +system.cpu.dtb.accesses 62965132 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -620,8 +607,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11527099 # ITB inst hits -system.cpu.itb.inst_misses 11249 # ITB inst misses +system.cpu.itb.inst_hits 11525561 # ITB inst hits +system.cpu.itb.inst_misses 11159 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -630,113 +617,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11538348 # ITB inst accesses -system.cpu.itb.hits 11527099 # DTB hits -system.cpu.itb.misses 11249 # DTB misses -system.cpu.itb.accesses 11538348 # DTB accesses -system.cpu.numCycles 477119451 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536720 # ITB inst accesses +system.cpu.itb.hits 11525561 # DTB hits +system.cpu.itb.misses 11159 # DTB misses +system.cpu.itb.accesses 11536720 # DTB accesses +system.cpu.numCycles 477128882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -765,13 +752,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued @@ -784,11 +771,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued @@ -797,404 +784,440 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued -system.cpu.iq.rate 0.257655 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued +system.cpu.iq.rate 0.257622 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221278 # number of nop insts executed -system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed -system.cpu.iew.exec_branches 11821235 # Number of branches executed -system.cpu.iew.exec_stores 12215513 # Number of stores executed -system.cpu.iew.exec_rate 0.253301 # Inst execution rate -system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47029089 # num instructions producing a value -system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value +system.cpu.iew.exec_nop 222849 # number of nop insts executed +system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed +system.cpu.iew.exec_branches 11822089 # Number of branches executed +system.cpu.iew.exec_stores 12212847 # Number of stores executed +system.cpu.iew.exec_rate 0.253272 # Inst execution rate +system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47017508 # num instructions producing a value +system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60460018 # Number of instructions committed -system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459415 # Number of instructions committed +system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386851 # Number of memory references committed -system.cpu.commit.loads 15654790 # Number of loads committed -system.cpu.commit.membars 403577 # Number of memory barriers committed -system.cpu.commit.branches 10306380 # Number of branches committed +system.cpu.commit.refs 27386618 # Number of memory references committed +system.cpu.commit.loads 15654647 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 10306311 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. -system.cpu.commit.function_calls 991253 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. +system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction +system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242979782 # The number of ROB reads -system.cpu.rob.rob_writes 196005989 # The number of ROB writes -system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309637 # Number of Instructions Simulated -system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated -system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548698002 # number of integer regfile reads -system.cpu.int_regfile_writes 87552826 # number of integer regfile writes -system.cpu.fp_regfile_reads 8408 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution +system.cpu.rob.rob_reads 243007370 # The number of ROB reads +system.cpu.rob.rob_writes 195993770 # The number of ROB writes +system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309034 # Number of Instructions Simulated +system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309034 # Number of Instructions Simulated +system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548643018 # number of integer regfile reads +system.cpu.int_regfile_writes 87545925 # number of integer regfile writes +system.cpu.fp_regfile_reads 8332 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980897 # number of replacements -system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 981488 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits -system.cpu.icache.overall_hits::total 10462766 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses -system.cpu.icache.overall_misses::total 1060743 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits +system.cpu.icache.overall_hits::total 10460581 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1061360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1061360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1061360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1061360 # number of overall misses +system.cpu.icache.overall_misses::total 1061360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14265779687 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14265779687 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14265779687 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14265779687 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14265779687 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14265779687 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11521941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11521941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11521941 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11521941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11521941 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11521941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092116 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092116 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092116 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092116 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092116 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092116 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13441.037619 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13441.037619 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13441.037619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13441.037619 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13441.037619 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 7028 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 344 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 352 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.668605 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.965909 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79293 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79293 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79293 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79293 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79293 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79293 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981450 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981450 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981450 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981450 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981450 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981450 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11587546773 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11587546773 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587546773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587546773 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587546773 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587546773 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9345000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9345000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9345000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9345000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085169 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.085169 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085169 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085169 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11806.558432 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11806.558432 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11806.558432 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11806.558432 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79319 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79319 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79319 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79319 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79319 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79319 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 982041 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 982041 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 982041 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 982041 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 982041 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 982041 # 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number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085232 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085232 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085232 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11795.548480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11795.548480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11795.548480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11795.548480 # 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number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184399054729 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184405489728 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015971 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.984828 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.984828 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541161 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092514 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000982 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012572 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223476 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092514 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 202750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59907.517029 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62695.679707 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61238.056496 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.342349 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.342349 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61342.279193 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61342.279193 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75944.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 193750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60703.107276 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61467.157893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61412.672268 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61479.110215 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61479.110215 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72339.622642 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 202750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59907.517029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61569.236181 # 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Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643832 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.407056 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 42989250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.993245 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # 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average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015072 # number of overall hits +system.cpu.dcache.overall_hits::total 21015072 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 735153 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 735153 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2964059 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2964059 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13525 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13525 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3699212 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3699212 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3699212 # number of overall misses +system.cpu.dcache.overall_misses::total 3699212 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9975087313 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9975087313 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 139822431498 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 139822431498 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185099999 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185099999 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 149797518811 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 149797518811 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 149797518811 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714284 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714284 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714284 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050728 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050728 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289963 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289963 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052772 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052772 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149679 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks -system.cpu.dcache.writebacks::total 607635 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634572 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967633608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967633608 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11307381788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11307381788 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145644250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145644250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 213497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 213497 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16275015396 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16275015396 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16275015396 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16275015396 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182336207250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182336207250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26867769000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26867769000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209203976250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209203976250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025671 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.831616 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.831616 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45421.934466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45421.934466 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11959.619806 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11959.619806 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13343.562500 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13343.562500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25647.232144 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 25647.232144 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607456 # number of writebacks +system.cpu.dcache.writebacks::total 607456 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 349595 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 349595 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715007 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2715007 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1337 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1337 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1500,16 +1523,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 7d13ac1ec..97a804211 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,156 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.605649 # Number of seconds simulated -sim_ticks 2605649343000 # Number of ticks simulated -final_tick 2605649343000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.605644 # Number of seconds simulated +sim_ticks 2605643988500 # Number of ticks simulated +final_tick 2605643988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57764 # Simulator instruction rate (inst/s) -host_op_rate 74374 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2397402056 # Simulator tick rate (ticks/s) -host_mem_usage 474764 # Number of bytes of host memory used -host_seconds 1086.86 # Real time elapsed on the host -sim_insts 62781325 # Number of instructions simulated -sim_ops 80834116 # Number of ops (including micro ops) simulated +host_inst_rate 56388 # Simulator instruction rate (inst/s) +host_op_rate 72604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2339801960 # Simulator tick rate (ticks/s) +host_mem_usage 475216 # Number of bytes of host memory used +host_seconds 1113.62 # Real time elapsed on the host +sim_insts 62794806 # Number of instructions simulated +sim_ops 80853196 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 383680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5448188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 438080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4125688 # Number of bytes read from this memory -system.physmem.bytes_read::total 131508276 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 383680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 438080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4229952 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 394240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4377212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 429184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5246712 # Number of bytes read from this memory +system.physmem.bytes_read::total 131559796 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 429184 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 823424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4275584 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7259088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5995 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 85202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6845 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64492 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301383 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66093 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68468 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82008 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302188 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66806 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823377 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46479979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 824090 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46480075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 147249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2090914 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 368 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 168127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1583363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50470443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 147249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 168127 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1623377 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1679896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2013595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50490319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151302 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316016 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1640893 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1156002 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2785904 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1623377 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46479979 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1156004 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2803422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1640893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46480075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 147249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2097438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 368 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 168127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2739365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53256346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15301383 # Number of read requests accepted -system.physmem.writeReqs 823377 # Number of write requests accepted -system.physmem.readBursts 15301383 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823377 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 973889408 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5399104 # Total number of bytes read from write queue -system.physmem.bytesWritten 7284800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131508276 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7259088 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 84361 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709522 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14082 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956098 # Per bank write bursts -system.physmem.perBankRdBursts::1 950020 # Per bank write bursts -system.physmem.perBankRdBursts::2 950090 # Per bank write bursts -system.physmem.perBankRdBursts::3 949980 # Per bank write bursts -system.physmem.perBankRdBursts::4 956223 # Per bank write bursts -system.physmem.perBankRdBursts::5 949119 # Per bank write bursts -system.physmem.perBankRdBursts::6 948884 # Per bank write bursts -system.physmem.perBankRdBursts::7 948711 # Per bank write bursts -system.physmem.perBankRdBursts::8 956337 # Per bank write bursts -system.physmem.perBankRdBursts::9 950158 # Per bank write bursts -system.physmem.perBankRdBursts::10 948908 # Per bank write bursts -system.physmem.perBankRdBursts::11 948900 # Per bank write bursts -system.physmem.perBankRdBursts::12 955944 # Per bank write bursts -system.physmem.perBankRdBursts::13 949314 # Per bank write bursts -system.physmem.perBankRdBursts::14 949393 # Per bank write bursts -system.physmem.perBankRdBursts::15 948943 # Per bank write bursts -system.physmem.perBankWrBursts::0 7119 # Per bank write bursts -system.physmem.perBankWrBursts::1 7037 # Per bank write bursts -system.physmem.perBankWrBursts::2 7071 # Per bank write bursts -system.physmem.perBankWrBursts::3 7168 # Per bank write bursts -system.physmem.perBankWrBursts::4 7696 # Per bank write bursts -system.physmem.perBankWrBursts::5 7220 # Per bank write bursts -system.physmem.perBankWrBursts::6 7070 # Per bank write bursts -system.physmem.perBankWrBursts::7 6913 # Per bank write bursts -system.physmem.perBankWrBursts::8 7415 # Per bank write bursts -system.physmem.perBankWrBursts::9 7415 # Per bank write bursts -system.physmem.perBankWrBursts::10 6887 # Per bank write bursts -system.physmem.perBankWrBursts::11 6788 # Per bank write bursts -system.physmem.perBankWrBursts::12 7071 # Per bank write bursts -system.physmem.perBankWrBursts::13 6872 # Per bank write bursts -system.physmem.perBankWrBursts::14 7197 # Per bank write bursts -system.physmem.perBankWrBursts::15 6886 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 151302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1686421 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3169600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53293741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302188 # Number of read requests accepted +system.physmem.writeReqs 824090 # Number of write requests accepted +system.physmem.readBursts 15302188 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 824090 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 974626176 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4713856 # Total number of bytes read from write queue +system.physmem.bytesWritten 7328128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131559796 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7304720 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 73654 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709569 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14159 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 956238 # Per bank write bursts +system.physmem.perBankRdBursts::1 951013 # Per bank write bursts +system.physmem.perBankRdBursts::2 950196 # Per bank write bursts +system.physmem.perBankRdBursts::3 950464 # Per bank write bursts +system.physmem.perBankRdBursts::4 956634 # Per bank write bursts +system.physmem.perBankRdBursts::5 950822 # Per bank write bursts +system.physmem.perBankRdBursts::6 949869 # Per bank write bursts +system.physmem.perBankRdBursts::7 949811 # Per bank write bursts +system.physmem.perBankRdBursts::8 956681 # Per bank write bursts +system.physmem.perBankRdBursts::9 951277 # Per bank write bursts +system.physmem.perBankRdBursts::10 949961 # Per bank write bursts +system.physmem.perBankRdBursts::11 949024 # Per bank write bursts +system.physmem.perBankRdBursts::12 956331 # Per bank write bursts +system.physmem.perBankRdBursts::13 950586 # Per bank write bursts +system.physmem.perBankRdBursts::14 950041 # Per bank write bursts +system.physmem.perBankRdBursts::15 949586 # Per bank write bursts +system.physmem.perBankWrBursts::0 7062 # Per bank write bursts +system.physmem.perBankWrBursts::1 6963 # Per bank write bursts +system.physmem.perBankWrBursts::2 7126 # Per bank write bursts +system.physmem.perBankWrBursts::3 7116 # Per bank write bursts +system.physmem.perBankWrBursts::4 7811 # Per bank write bursts +system.physmem.perBankWrBursts::5 7409 # Per bank write bursts +system.physmem.perBankWrBursts::6 7013 # Per bank write bursts +system.physmem.perBankWrBursts::7 7004 # Per bank write bursts +system.physmem.perBankWrBursts::8 7458 # Per bank write bursts +system.physmem.perBankWrBursts::9 7561 # Per bank write bursts +system.physmem.perBankWrBursts::10 6914 # Per bank write bursts +system.physmem.perBankWrBursts::11 6583 # Per bank write bursts +system.physmem.perBankWrBursts::12 7179 # Per bank write bursts +system.physmem.perBankWrBursts::13 7101 # Per bank write bursts +system.physmem.perBankWrBursts::14 7219 # Per bank write bursts +system.physmem.perBankWrBursts::15 6983 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2605648115500 # Total gap between requests +system.physmem.totGap 2605642823000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 109 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 162458 # Read request sizes (log2) +system.physmem.readPktSize::6 163263 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66093 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1062706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 998935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950903 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 959607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 945820 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 946342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2754714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2746120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3637640 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 38272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 34182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 34523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 32360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66806 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1074226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1009957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 967065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1078396 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 970167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1034458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2664402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2566961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3342237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 136100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 116220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 107345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 103465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -176,47 +176,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 549 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6844 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7248 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -225,85 +225,74 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 965097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1010.691593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 992.992769 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 104.599429 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5712 0.59% 0.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4413 0.46% 1.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2116 0.22% 1.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1499 0.16% 1.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1121 0.12% 1.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 815 0.08% 1.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 661 0.07% 1.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 851 0.09% 1.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 947909 98.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 965097 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5955 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2555.332662 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 92927.024688 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 5949 99.90% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5955 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5955 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.114190 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.218740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.431880 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3971 66.68% 66.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 19 0.32% 67.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 175 2.94% 69.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1141 19.16% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 44 0.74% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.32% 90.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.35% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.17% 90.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 6 0.10% 90.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.05% 90.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.07% 90.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 90.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 90.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 90.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 146 2.45% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 311 5.22% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 13 0.22% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 13 0.22% 99.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 16 0.27% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 22 0.37% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 9 0.15% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 4 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5955 # Writes before turning the bus around for reads -system.physmem.totQLat 579051796250 # Total ticks spent queuing -system.physmem.totMemAccLat 683715373750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76085110000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28578467500 # Total ticks spent accessing banks -system.physmem.avgQLat 38052.90 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1878.06 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 1012463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 969.866853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 900.909804 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 207.662919 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24967 2.47% 2.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21104 2.08% 4.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8681 0.86% 5.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2506 0.25% 5.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2720 0.27% 5.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2029 0.20% 6.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8638 0.85% 6.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1014 0.10% 7.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 940804 92.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1012463 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6706 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2270.880853 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 84552.226363 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6700 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 1 0.01% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.88358e+06-3.14573e+06 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5.24288e+06-5.50502e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6706 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6706 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.074560 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.020748 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.396636 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3829 57.10% 57.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 48 0.72% 57.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1779 26.53% 84.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 878 13.09% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 53 0.79% 98.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 31 0.46% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 34 0.51% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 40 0.60% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.18% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6706 # Writes before turning the bus around for reads +system.physmem.totQLat 395588666000 # Total ticks spent queuing +system.physmem.totMemAccLat 681123678500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76142670000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25976.81 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44930.96 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 373.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.47 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44726.81 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.04 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.81 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.94 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.53 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14231578 # Number of row buffer hits during reads -system.physmem.writeRowHits 96073 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.38 # Row buffer hit rate for writes -system.physmem.avgGap 161592.99 # Average gap between requests -system.physmem.pageHitRate 93.46 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.22 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.05 # Average write queue length when enqueuing +system.physmem.readRowHits 14234195 # Number of row buffer hits during reads +system.physmem.writeRowHits 96378 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 84.16 # Row buffer hit rate for writes +system.physmem.avgGap 161577.45 # Average gap between requests +system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2260536385250 # Time in different power states +system.physmem.memoryStateTime::REF 87007960000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 258093332250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -322,300 +311,299 @@ system.realview.nvmem.bw_inst_read::total 172 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54186995 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352581 # Transaction distribution -system.membus.trans_dist::ReadResp 16352581 # Transaction distribution -system.membus.trans_dist::WriteReq 769189 # Transaction distribution -system.membus.trans_dist::WriteResp 769189 # Transaction distribution -system.membus.trans_dist::Writeback 66093 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35785 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18271 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14082 # Transaction distribution -system.membus.trans_dist::ReadExReq 137406 # Transaction distribution -system.membus.trans_dist::ReadExResp 137045 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384396 # Packet count per connected master and slave (bytes) +system.membus.throughput 54224369 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16352672 # Transaction distribution +system.membus.trans_dist::ReadResp 16352672 # Transaction distribution +system.membus.trans_dist::WriteReq 769183 # Transaction distribution +system.membus.trans_dist::WriteResp 769183 # Transaction distribution +system.membus.trans_dist::Writeback 66806 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35949 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 18292 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14159 # Transaction distribution +system.membus.trans_dist::ReadExReq 138125 # Transaction distribution +system.membus.trans_dist::ReadExResp 137746 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384364 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13840 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13834 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2042 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1974294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4374590 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976897 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4377155 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34652222 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392725 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34654787 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27680 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27668 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4084 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17656836 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20081781 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17753988 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20178873 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141192309 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141192309 # Total data (bytes) +system.membus.tot_pkt_size::total 141289401 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 141289401 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1488242000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1487962500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11807000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11808000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1798000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1796000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17652470999 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17659548997 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4843604815 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4847870095 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37703679634 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37379122644 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 72164 # number of replacements -system.l2c.tags.tagsinuse 53016.131060 # Cycle average of tags in use -system.l2c.tags.total_refs 1876966 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137304 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.670148 # Average number of references to valid blocks. +system.l2c.tags.replacements 72974 # number of replacements +system.l2c.tags.tagsinuse 53023.948009 # Cycle average of tags in use +system.l2c.tags.total_refs 1873330 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 138152 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.559920 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37702.356015 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 7.377107 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000365 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4186.473555 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2957.675740 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.683393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4035.806716 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4115.758170 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.575292 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000113 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 37706.296895 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.412172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000364 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4169.126027 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2962.597547 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 11.621110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4061.748879 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 4107.145016 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.575352 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063881 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.045131 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000163 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.061582 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.062801 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.808962 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.063616 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045206 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000177 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.061977 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.062670 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154881314980 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167226422467 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1073382998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16528122341 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17601505339 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6890749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13408755986 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2843750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171409437321 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184827927806 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036526 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030475 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017358 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835192 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859190 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.845537 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787474 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.788487 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.787914 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571900 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564152 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567632 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246610 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.241754 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097067 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000528 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000450 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015101 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246610 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000482 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010842 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241754 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097067 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61613.343253 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63513.847089 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61249.930888 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.625198 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.796889 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10049.668510 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10014.033898 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.541596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10009.476401 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57729.104367 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65666.928730 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62074.834549 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83479.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59589.463221 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58078.651935 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60176.947321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65502.964994 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61948.689556 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -806,62 +794,62 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58721934 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2742702 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2742701 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769189 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769189 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 582434 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 35028 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18623 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53651 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259025 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259025 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831060 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2542800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15169 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56113 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1201524 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 3348368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 16175 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 77084 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8088293 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26573504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 39205457 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 22316 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 94444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38427456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 43600612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148080029 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148080029 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4928740 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4918843977 # Layer occupancy (ticks) +system.toL2Bus.throughput 58718575 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2740966 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2740965 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769183 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769183 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 583128 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 35123 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 53780 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 259272 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 259272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 800244 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13760 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 56807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1229764 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4820581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 15635 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 75586 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8085518 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25589824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34686241 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17772 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 90896 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 39333696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 48239320 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 23208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 132848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148113805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148113805 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4885896 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4921313376 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872939397 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1803473389 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2324821689 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514355955 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9616940 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9338456 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 32646700 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34226949 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2706859206 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 2770248418 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2444231662 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 3257977460 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 10370957 # Layer occupancy (ticks) +system.toL2Bus.respLayer8.occupancy 9851958 # Layer occupancy (ticks) system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 44131664 # Layer occupancy (ticks) +system.toL2Bus.respLayer9.occupancy 42643941 # Layer occupancy (ticks) system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47398263 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322928 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322928 # Transaction distribution -system.iobus.trans_dist::WriteReq 8086 # Transaction distribution -system.iobus.trans_dist::WriteResp 8086 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30960 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8852 # Packet count per connected master and slave (bytes) +system.iobus.throughput 47398342 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322915 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322915 # Transaction distribution +system.iobus.trans_dist::WriteReq 8083 # Transaction distribution +system.iobus.trans_dist::WriteResp 8083 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8836 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -883,12 +871,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384396 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32662028 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40729 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 32661996 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17672 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -910,14 +898,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392725 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503253 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21724000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123503205 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4432000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4424000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -963,19 +951,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376310000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376281000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37739478366 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu0.branchPred.lookups 6715650 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5214611 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 297509 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4164563 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3259277 # Number of BTB hits +system.iobus.respLayer1.occupancy 38174483356 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 6117114 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4670626 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296157 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3842728 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2949969 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 78.262161 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 722080 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28659 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.767572 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 683314 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28361 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -999,25 +987,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 30314049 # DTB read hits -system.cpu0.dtb.read_misses 28675 # DTB read misses -system.cpu0.dtb.write_hits 5612279 # DTB write hits -system.cpu0.dtb.write_misses 4120 # DTB write misses +system.cpu0.dtb.read_hits 8969403 # DTB read hits +system.cpu0.dtb.read_misses 29343 # DTB read misses +system.cpu0.dtb.write_hits 5210557 # DTB write hits +system.cpu0.dtb.write_misses 5731 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1934 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1024 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1050 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 278 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 30342724 # DTB read accesses -system.cpu0.dtb.write_accesses 5616399 # DTB write accesses +system.cpu0.dtb.perms_faults 596 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8998746 # DTB read accesses +system.cpu0.dtb.write_accesses 5216288 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 35926328 # DTB hits -system.cpu0.dtb.misses 32795 # DTB misses -system.cpu0.dtb.accesses 35959123 # DTB accesses +system.cpu0.dtb.hits 14179960 # DTB hits +system.cpu0.dtb.misses 35074 # DTB misses +system.cpu0.dtb.accesses 14215034 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1039,8 +1027,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 4601822 # ITB inst hits -system.cpu0.itb.inst_misses 5333 # ITB inst misses +system.cpu0.itb.inst_hits 4277605 # ITB inst hits +system.cpu0.itb.inst_misses 5145 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1049,544 +1037,584 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1359 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1531 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1426 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4607155 # ITB inst accesses -system.cpu0.itb.hits 4601822 # DTB hits -system.cpu0.itb.misses 5333 # DTB misses -system.cpu0.itb.accesses 4607155 # DTB accesses -system.cpu0.numCycles 298758505 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4282750 # ITB inst accesses +system.cpu0.itb.hits 4277605 # DTB hits +system.cpu0.itb.misses 5145 # DTB misses +system.cpu0.itb.accesses 4282750 # DTB accesses +system.cpu0.numCycles 70248238 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 12556555 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 35349888 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6715650 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3981357 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 8343175 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1485021 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 73668 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 62934939 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 43768 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1358657 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 326 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4600051 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 159705 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 86381436 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.526874 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.794731 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11931842 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32451975 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6117114 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3633283 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7612739 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1460869 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60951 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20309232 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 6063 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46682 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1377400 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 299 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4276074 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 156796 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2089 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42393450 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.988978 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.370199 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 78045507 90.35% 90.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 675063 0.78% 91.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 847046 0.98% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 783211 0.91% 93.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1013921 1.17% 94.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 572462 0.66% 94.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 659407 0.76% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 359642 0.42% 96.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3425177 3.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34788183 82.06% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 572054 1.35% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 825907 1.95% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686377 1.62% 86.98% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 779180 1.84% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 565083 1.33% 90.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 677221 1.60% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 357838 0.84% 92.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3141607 7.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 86381436 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.022479 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.118323 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13622847 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 63604727 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7412124 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 742617 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 999121 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974392 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66422 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 44125799 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 218867 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 999121 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14363042 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 26099881 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 33731509 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7356267 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3831616 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 43013829 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 321 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 629927 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2476084 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 94 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 43352703 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 198103413 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178854732 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5396 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 34867311 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8485392 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 643580 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 598183 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 7434614 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8769305 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6206849 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1218439 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1296110 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 40716219 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1133567 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61584494 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 78672 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6465857 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13399979 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 300001 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 86381436 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.712937 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.420531 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42393450 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.087079 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461961 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12487890 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21493629 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6874468 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 552722 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 984741 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 950951 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64626 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40558878 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212020 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 984741 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13064503 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5883311 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13498743 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6804692 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2157460 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39446559 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 311 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 442642 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1180293 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 145 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39856275 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 180582545 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 163877057 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4135 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31488132 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8368142 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 460013 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 416638 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5509006 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7758217 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5771757 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1123661 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1193308 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37348678 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 906063 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37718806 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82800 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6312476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13233696 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257258 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42393450 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.889732 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.506737 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 63313818 73.30% 73.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8088215 9.36% 82.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3310781 3.83% 86.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2721682 3.15% 89.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 7122842 8.25% 97.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1038791 1.20% 99.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 532976 0.62% 99.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 192156 0.22% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 60175 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27027469 63.75% 63.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5904750 13.93% 77.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3167008 7.47% 85.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2470651 5.83% 90.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2117188 4.99% 95.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 941206 2.22% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 520081 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 187957 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 57140 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 86381436 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42393450 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26298 0.46% 0.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.01% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5416194 95.59% 96.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 223026 3.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26875 2.51% 2.51% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 458 0.04% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 836202 77.98% 80.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208765 19.47% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15923 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 24790294 40.25% 40.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50109 0.08% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 806 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 40.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 30788025 49.99% 90.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5939307 9.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14551 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22694630 60.17% 60.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47979 0.13% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 10 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.33% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9430195 25.00% 85.34% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5530734 14.66% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61584494 # Type of FU issued -system.cpu0.iq.rate 0.206135 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 5665970 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.092003 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 215315704 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 48322789 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38367249 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11842 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6226 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5089 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67228191 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6350 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 325894 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37718806 # Type of FU issued +system.cpu0.iq.rate 0.536936 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1072300 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028429 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119012569 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44575137 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34852276 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8350 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38772197 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4358 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316382 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1367932 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2587 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13911 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 563678 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1375838 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2694 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13105 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538991 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 22510150 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5899 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149907 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5937 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 999121 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 20412775 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 272757 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 41952562 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83343 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8769305 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6206849 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 796686 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 50755 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3694 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13911 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151015 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116203 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267218 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61206576 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 30649831 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377918 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 984741 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4273547 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 99764 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38372810 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83727 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7758217 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5771757 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 578717 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40350 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3282 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13105 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151036 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117828 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268864 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37337135 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9286340 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 381671 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 102776 # number of nop insts executed -system.cpu0.iew.exec_refs 36543183 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5550332 # Number of branches executed -system.cpu0.iew.exec_stores 5893352 # Number of stores executed -system.cpu0.iew.exec_rate 0.204870 # Inst execution rate -system.cpu0.iew.wb_sent 61019070 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38372338 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 20674113 # num instructions producing a value -system.cpu0.iew.wb_consumers 38142518 # num instructions consuming a value +system.cpu0.iew.exec_nop 118069 # number of nop insts executed +system.cpu0.iew.exec_refs 14769450 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4962843 # Number of branches executed +system.cpu0.iew.exec_stores 5483110 # Number of stores executed +system.cpu0.iew.exec_rate 0.531503 # Inst execution rate +system.cpu0.iew.wb_sent 37142523 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34856145 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18592748 # num instructions producing a value +system.cpu0.iew.wb_consumers 35683758 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.128439 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.542023 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496185 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521042 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6195680 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 833566 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232261 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 85382315 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.412432 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.299663 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6125993 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 648805 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232656 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41408709 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.767702 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.726975 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 71262923 83.46% 83.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7740236 9.07% 92.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2004904 2.35% 94.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1114217 1.30% 96.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 806577 0.94% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 503262 0.59% 97.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 497454 0.58% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 227564 0.27% 98.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1225178 1.43% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29445863 71.11% 71.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5939620 14.34% 85.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940870 4.69% 90.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1013361 2.45% 92.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 759448 1.83% 94.42% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 515426 1.24% 95.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 408347 0.99% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 223076 0.54% 97.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1162698 2.81% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 85382315 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 26835114 # Number of instructions committed -system.cpu0.commit.committedOps 35214409 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41408709 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24071577 # Number of instructions committed +system.cpu0.commit.committedOps 31789563 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13044544 # Number of memory references committed -system.cpu0.commit.loads 7401373 # Number of loads committed -system.cpu0.commit.membars 236456 # Number of memory barriers committed -system.cpu0.commit.branches 4918099 # Number of branches committed -system.cpu0.commit.fp_insts 5062 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 31243705 # Number of committed integer instructions. -system.cpu0.commit.function_calls 531450 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1225178 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11615145 # Number of memory references committed +system.cpu0.commit.loads 6382379 # Number of loads committed +system.cpu0.commit.membars 231812 # Number of memory barriers committed +system.cpu0.commit.branches 4351457 # Number of branches committed +system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 28135168 # Number of committed integer instructions. +system.cpu0.commit.function_calls 498959 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 20133954 63.34% 63.34% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39784 0.13% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 680 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6382379 20.08% 83.54% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5232766 16.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 31789563 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1162698 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124649951 # The number of ROB reads -system.cpu0.rob.rob_writes 83821170 # The number of ROB writes -system.cpu0.timesIdled 1018994 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 212377069 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 4911896145 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 26765511 # Number of Instructions Simulated -system.cpu0.committedOps 35144806 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 26765511 # Number of Instructions Simulated -system.cpu0.cpi 11.162070 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 11.162070 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.089589 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.089589 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 273626518 # number of integer regfile reads -system.cpu0.int_regfile_writes 37917674 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4695 # number of floating regfile reads -system.cpu0.fp_regfile_writes 986 # number of floating regfile writes -system.cpu0.misc_regfile_reads 148789996 # number of misc regfile reads -system.cpu0.misc_regfile_writes 678362 # number of misc regfile writes -system.cpu0.icache.tags.replacements 415188 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.568306 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 4152259 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 415700 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.988595 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7103550250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.568306 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999157 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999157 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 77292791 # The number of ROB reads +system.cpu0.rob.rob_writes 76817595 # The number of ROB writes +system.cpu0.timesIdled 365665 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27854788 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5140997105 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23990835 # Number of Instructions Simulated +system.cpu0.committedOps 31708821 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23990835 # Number of Instructions Simulated +system.cpu0.cpi 2.928128 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.928128 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341515 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341515 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174285855 # number of integer regfile reads +system.cpu0.int_regfile_writes 34604955 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3294 # number of floating regfile reads +system.cpu0.fp_regfile_writes 912 # number of floating regfile writes +system.cpu0.misc_regfile_reads 79299010 # number of misc regfile reads +system.cpu0.misc_regfile_writes 500883 # number of misc regfile writes +system.cpu0.icache.tags.replacements 399739 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.543627 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3844274 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 400251 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.604658 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7097393250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.543627 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999109 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999109 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 5015647 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 5015647 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 4152259 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 4152259 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 4152259 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 4152259 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 4152259 # number of overall hits -system.cpu0.icache.overall_hits::total 4152259 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 447663 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 447663 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 447663 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 447663 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 447663 # number of overall misses -system.cpu0.icache.overall_misses::total 447663 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6158685000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6158685000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6158685000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6158685000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6158685000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6158685000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4599922 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4599922 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4599922 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4599922 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4599922 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4599922 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097320 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.097320 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097320 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.097320 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097320 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.097320 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13757.413501 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13757.413501 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13757.413501 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13757.413501 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13757.413501 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4464 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 4676219 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 4676219 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 3844274 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3844274 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3844274 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3844274 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3844274 # number of overall hits +system.cpu0.icache.overall_hits::total 3844274 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431668 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431668 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431668 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431668 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431668 # number of overall misses +system.cpu0.icache.overall_misses::total 431668 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5966691765 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5966691765 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5966691765 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5966691765 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5966691765 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5966691765 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4275942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4275942 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4275942 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4275942 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4275942 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4275942 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100953 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100953 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100953 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100953 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100953 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100953 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13822.409271 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13822.409271 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13822.409271 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13822.409271 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13822.409271 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4149 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 26.730539 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 24.122093 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31938 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 31938 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 31938 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 31938 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 31938 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 31938 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 415725 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 415725 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 415725 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 415725 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 415725 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415725 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5022987594 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5022987594 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5022987594 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5022987594 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5022987594 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5022987594 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9487250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9487250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9487250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9487250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090377 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090377 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090377 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090377 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12082.476623 # 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number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400278 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400278 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400278 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400278 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400278 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400278 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4859637603 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4859637603 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4859637603 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4859637603 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4859637603 # 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Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 384 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 48541082 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 48541082 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6144970 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6144970 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3563655 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3563655 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 144672 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 144672 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142233 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 142233 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9708625 # 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number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2038506 # number of overall misses -system.cpu0.dcache.overall_misses::total 2038506 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5542234631 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5542234631 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 82471404032 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 82471404032 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 94602484 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 94602484 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50293768 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 50293768 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 88013638663 # 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number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11747131 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11747131 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11747131 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11747131 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.060244 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.060244 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.315765 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.315765 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060059 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.060059 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052405 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052405 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173532 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.173532 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.173532 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.173532 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.120656 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.120656 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50147.487185 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50147.487185 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10233.933795 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10233.933795 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6393.817442 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6393.817442 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43175.560270 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43175.560270 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43175.560270 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10878 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5936 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 678 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 116 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.044248 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 51.172414 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 275002 # number of replacements +system.cpu0.dcache.tags.tagsinuse 479.873805 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9429051 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 275514 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 34.223491 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43985250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 479.873805 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937254 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.937254 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 45805638 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45805638 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 5875796 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5875796 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3229179 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3229179 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139566 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139566 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137212 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137212 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9104975 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9104975 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9104975 # number of overall hits +system.cpu0.dcache.overall_hits::total 9104975 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392540 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392540 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582550 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582550 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8878 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8878 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7747 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7747 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975090 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975090 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975090 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975090 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5503316358 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5503316358 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80403947306 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 80403947306 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 91149731 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 91149731 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49845761 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 49845761 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85907263664 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85907263664 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85907263664 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85907263664 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6268336 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6268336 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4811729 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4811729 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148444 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148444 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144959 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144959 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11080065 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11080065 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11080065 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11080065 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062623 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062623 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328894 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.328894 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053443 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053443 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178256 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178256 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178256 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178256 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14019.759408 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14019.759408 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50806.576289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50806.576289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10266.921717 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10266.921717 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6434.201756 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6434.201756 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43495.366623 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43495.366623 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43495.366623 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9513 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7748 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 587 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 136 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.206133 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 56.970588 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 278268 # number of writebacks -system.cpu0.dcache.writebacks::total 278268 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201648 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 201648 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1493557 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1493557 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 632 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 632 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1695205 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1695205 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1695205 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1695205 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 192281 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 192281 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 151020 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 151020 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8612 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8612 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7866 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7866 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 343301 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 343301 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 343301 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 343301 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2438332267 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2438332267 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6681240000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6681240000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70543016 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70543016 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34562232 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34562232 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.writebacks::writebacks 255347 # number of writebacks +system.cpu0.dcache.writebacks::total 255347 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203411 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203411 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451593 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451593 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 468 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 468 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655004 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1655004 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655004 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1655004 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189129 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189129 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130957 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130957 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8410 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8410 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7747 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7747 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320086 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320086 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320086 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320086 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2397985131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2397985131 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5338215866 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5338215866 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69513767 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69513767 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34349239 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34349239 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9119572267 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9119572267 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9119572267 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9119572267 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 120538982283 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 120538982283 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1232045382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1232045382 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 121771027665 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 121771027665 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029406 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029406 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028996 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028996 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055953 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052405 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052405 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029224 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029224 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029224 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12681.087923 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12681.087923 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44240.762813 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44240.762813 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8191.246633 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8191.246633 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4393.876430 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4393.876430 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7736200997 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7736200997 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7736200997 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7736200997 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13434640527 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13434640527 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1206086382 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1206086382 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14640726909 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14640726909 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030172 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030172 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027216 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027216 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056654 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056654 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053443 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053443 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028888 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028888 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028888 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12679.098028 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12679.098028 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40763.119696 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40763.119696 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8265.608442 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8265.608442 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4433.876210 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4433.876210 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26564.362664 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26564.362664 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24169.132661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24169.132661 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1594,15 +1622,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8689698 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7082612 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 415349 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5570453 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4730059 # Number of BTB hits +system.cpu1.branchPred.lookups 9293378 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7631598 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 415998 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5889507 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5046361 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.913363 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 759549 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43595 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.683929 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 797302 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43622 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1626,25 +1654,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 21626734 # DTB read hits -system.cpu1.dtb.read_misses 38691 # DTB read misses -system.cpu1.dtb.write_hits 6575784 # DTB write hits -system.cpu1.dtb.write_misses 12298 # DTB write misses +system.cpu1.dtb.read_hits 42971422 # DTB read hits +system.cpu1.dtb.read_misses 37905 # DTB read misses +system.cpu1.dtb.write_hits 6976449 # DTB write hits +system.cpu1.dtb.write_misses 10883 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1712 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3023 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 279 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1918 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2893 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 296 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 600 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 21665425 # DTB read accesses -system.cpu1.dtb.write_accesses 6588082 # DTB write accesses +system.cpu1.dtb.perms_faults 686 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43009327 # DTB read accesses +system.cpu1.dtb.write_accesses 6987332 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 28202518 # DTB hits -system.cpu1.dtb.misses 50989 # DTB misses -system.cpu1.dtb.accesses 28253507 # DTB accesses +system.cpu1.dtb.hits 49947871 # DTB hits +system.cpu1.dtb.misses 48788 # DTB misses +system.cpu1.dtb.accesses 49996659 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1666,8 +1694,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7394895 # ITB inst hits -system.cpu1.itb.inst_misses 5860 # ITB inst misses +system.cpu1.itb.inst_hits 7719787 # ITB inst hits +system.cpu1.itb.inst_misses 5634 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1676,546 +1704,575 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1207 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1369 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1503 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1538 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7400755 # ITB inst accesses -system.cpu1.itb.hits 7394895 # DTB hits -system.cpu1.itb.misses 5860 # DTB misses -system.cpu1.itb.accesses 7400755 # DTB accesses -system.cpu1.numCycles 185247782 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7725421 # ITB inst accesses +system.cpu1.itb.hits 7719787 # DTB hits +system.cpu1.itb.misses 5634 # DTB misses +system.cpu1.itb.accesses 7725421 # DTB accesses +system.cpu1.numCycles 413693823 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18767441 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 58413381 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8689698 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5489608 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 12630025 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3326163 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 70879 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 38401480 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5864 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 46813 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1518730 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7393189 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 549179 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3073 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 73717325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.969397 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.351920 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19372544 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61318271 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9293378 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5843663 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13362487 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3346253 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69736 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 80999073 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5941 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42062 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1494344 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 284 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7717920 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 551887 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2996 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117635394 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.638004 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.959630 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 61095045 82.88% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 712004 0.97% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939814 1.27% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1614257 2.19% 87.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1180828 1.60% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 579149 0.79% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1971485 2.67% 92.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 418985 0.57% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5205758 7.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 104280280 88.65% 88.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 814710 0.69% 89.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 961160 0.82% 90.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1713171 1.46% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1415249 1.20% 92.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 586962 0.50% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1954597 1.66% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 422243 0.36% 95.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5487022 4.66% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 73717325 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.046909 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.315326 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 19856835 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 39689565 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11370888 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 621997 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2178040 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1113164 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 99384 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 67504859 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 329486 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2178040 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 20884497 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 13732674 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 23091492 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 10921071 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2909551 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63553177 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 150 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 495727 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 1775459 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 454 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 67243012 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 295535307 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 271726361 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4962 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 47019288 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20223723 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 581683 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 523637 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6484055 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11835207 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7683859 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 982260 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1485488 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 58475771 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 951228 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 65019700 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 99369 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13400197 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36106127 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236520 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 73717325 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.882014 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.585621 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117635394 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022464 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.148221 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20963679 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 81759193 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11913295 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 809519 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2189708 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1137363 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100954 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71089276 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 336011 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2189708 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22156707 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33902507 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 43325786 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11473545 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4587141 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67137864 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 137 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 682095 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3075433 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1010 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70763032 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 313108743 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 286757803 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6623 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50416422 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20346610 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 765987 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 705836 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8420477 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12843204 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8115826 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1055497 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1512633 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 61850161 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1179252 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 88896986 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93979 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13548762 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36246660 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 279849 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117635394 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.755699 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.498688 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 50542925 68.56% 68.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7121407 9.66% 78.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4031042 5.47% 83.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3362905 4.56% 88.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 5367239 7.28% 95.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1894348 2.57% 98.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1048738 1.42% 99.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 275398 0.37% 99.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73323 0.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86772303 73.76% 73.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9298113 7.90% 81.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4175598 3.55% 85.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3594840 3.06% 88.27% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10374006 8.82% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1994938 1.70% 98.79% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1065613 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 281099 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 78884 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 73717325 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117635394 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 33869 1.02% 1.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.03% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 2994112 90.44% 91.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 281623 8.51% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32152 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 986 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7573471 95.70% 96.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 306947 3.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12895 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 35505233 54.61% 54.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59031 0.09% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1556 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.72% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 22501549 34.61% 89.33% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6939400 10.67% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14268 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37614404 42.31% 42.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1706 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.40% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43858329 49.34% 91.74% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7347048 8.26% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 65019700 # Type of FU issued -system.cpu1.iq.rate 0.350988 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 3310600 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.050917 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 207206368 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 72837982 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 50730101 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11167 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5978 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5058 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 68311542 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5863 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343642 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 88896986 # Type of FU issued +system.cpu1.iq.rate 0.214886 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7913556 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089019 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303469985 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 76586992 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54255274 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15534 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8108 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6874 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96788024 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8250 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 355713 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2877094 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3994 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17361 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1094953 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2862172 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4122 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17485 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1111950 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 11606945 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 675630 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965671 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675853 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2178040 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 10295917 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 191116 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 59545170 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 114100 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11835207 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7683859 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 664311 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 56460 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4454 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17361 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 204103 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 160517 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 364620 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 63283569 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 21990431 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1736131 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2189708 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26386476 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 363440 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63133555 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 115239 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12843204 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8115826 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 883054 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 66097 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4286 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17485 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 204520 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 158639 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 363159 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87164207 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43354058 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1732779 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 118171 # number of nop insts executed -system.cpu1.iew.exec_refs 28863200 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6787528 # Number of branches executed -system.cpu1.iew.exec_stores 6872769 # Number of stores executed -system.cpu1.iew.exec_rate 0.341616 # Inst execution rate -system.cpu1.iew.wb_sent 62514610 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 50735159 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 28199774 # num instructions producing a value -system.cpu1.iew.wb_consumers 51433237 # num instructions consuming a value +system.cpu1.iew.exec_nop 104142 # number of nop insts executed +system.cpu1.iew.exec_refs 50636612 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7376811 # Number of branches executed +system.cpu1.iew.exec_stores 7282554 # Number of stores executed +system.cpu1.iew.exec_rate 0.210697 # Inst execution rate +system.cpu1.iew.wb_sent 86400335 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54262148 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30287291 # num instructions producing a value +system.cpu1.iew.wb_consumers 53873069 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.273877 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.548279 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131165 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.562197 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13377367 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 714708 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 317605 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 71539285 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.639790 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.672504 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13443206 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899403 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 316783 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 115445686 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.426296 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.378874 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 55665383 77.81% 77.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7811223 10.92% 88.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2101815 2.94% 91.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1189986 1.66% 93.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 946066 1.32% 94.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 613597 0.86% 95.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 912617 1.28% 96.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531458 0.74% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1767140 2.47% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97421932 84.39% 84.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 9594899 8.31% 92.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2172227 1.88% 94.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1301741 1.13% 95.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 988993 0.86% 96.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 587152 0.51% 97.07% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1008803 0.87% 97.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 534624 0.46% 98.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1835315 1.59% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 71539285 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 36096592 # Number of instructions committed -system.cpu1.commit.committedOps 45770088 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 115445686 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38873610 # Number of instructions committed +system.cpu1.commit.committedOps 49214014 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 15547019 # Number of memory references committed -system.cpu1.commit.loads 8958113 # Number of loads committed -system.cpu1.commit.membars 191016 # Number of memory barriers committed -system.cpu1.commit.branches 5856523 # Number of branches committed -system.cpu1.commit.fp_insts 5022 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 40800338 # Number of committed integer instructions. -system.cpu1.commit.function_calls 520894 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1767140 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16984908 # Number of memory references committed +system.cpu1.commit.loads 9981032 # Number of loads committed +system.cpu1.commit.membars 195536 # Number of memory barriers committed +system.cpu1.commit.branches 6424997 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43926362 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553376 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 32169137 65.37% 65.37% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58263 0.12% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.48% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1706 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.49% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9981032 20.28% 85.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 7003876 14.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 49214014 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1835315 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 127901171 # The number of ROB reads -system.cpu1.rob.rob_writes 120555711 # The number of ROB writes -system.cpu1.timesIdled 777241 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 111530457 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5026003021 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 36015814 # Number of Instructions Simulated -system.cpu1.committedOps 45689310 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 36015814 # Number of Instructions Simulated -system.cpu1.cpi 5.143512 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 5.143512 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.194420 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.194420 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 292255401 # number of integer regfile reads -system.cpu1.int_regfile_writes 53047565 # number of integer regfile writes -system.cpu1.fp_regfile_reads 3797 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1766 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133121160 # number of misc regfile reads -system.cpu1.misc_regfile_writes 545345 # number of misc regfile writes -system.cpu1.icache.tags.replacements 600500 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.750005 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6745926 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 601012 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.224278 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74974413000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.750005 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974121 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974121 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 175201017 # The number of ROB reads +system.cpu1.rob.rob_writes 127586843 # The number of ROB writes +system.cpu1.timesIdled 1428644 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 296058429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796946974 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38803971 # Number of Instructions Simulated +system.cpu1.committedOps 49144375 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38803971 # Number of Instructions Simulated +system.cpu1.cpi 10.661121 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.661121 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093799 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093799 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391634066 # number of integer regfile reads +system.cpu1.int_regfile_writes 56368159 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5144 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 202762353 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723009 # number of misc regfile writes +system.cpu1.icache.tags.replacements 614589 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.738252 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7056364 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 615101 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.471879 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74953244500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.738252 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974098 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974098 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 7994182 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 7994182 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6745926 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6745926 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6745926 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6745926 # 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number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8801556837 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8801556837 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7393137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7393137 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7393137 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7393137 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7393137 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7393137 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.087542 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.087542 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.087542 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.087542 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.087542 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.087542 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13599.207734 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13599.207734 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13599.207734 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13599.207734 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13599.207734 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3107 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 341 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 199 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.613065 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 341 # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 8332995 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8332995 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7056364 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7056364 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7056364 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7056364 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7056364 # number of overall hits +system.cpu1.icache.overall_hits::total 7056364 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661505 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661505 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661505 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661505 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661505 # number of overall misses +system.cpu1.icache.overall_misses::total 661505 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8964922762 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8964922762 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8964922762 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8964922762 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8964922762 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8964922762 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7717869 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7717869 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7717869 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7717869 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7717869 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7717869 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085711 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085711 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085711 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085711 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085711 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085711 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13552.312926 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13552.312926 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13552.312926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13552.312926 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13552.312926 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3582 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 212 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # 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number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 601046 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 601046 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 601046 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 601046 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7178040035 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7178040035 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7178040035 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7178040035 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7178040035 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7178040035 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3605250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3605250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3605250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3605250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.081298 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.081298 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.081298 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.081298 # 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number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46379 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615126 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615126 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615126 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615126 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615126 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615126 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7320744820 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7320744820 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7320744820 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7320744820 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7320744820 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7320744820 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3847250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3847250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3847250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3847250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079702 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079702 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079702 # 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average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 339082 # number of replacements -system.cpu1.dcache.tags.tagsinuse 482.965075 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 12423447 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 339594 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.583235 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 71024759250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.965075 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.943291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.943291 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 57544569 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 57544569 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 8247311 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8247311 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3935666 # 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number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13642 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13642 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10758 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10758 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1901363 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1901363 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1901363 # number of overall misses -system.cpu1.dcache.overall_misses::total 1901363 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6052529769 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6052529769 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75305143416 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 75305143416 # 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number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5436993 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 108095 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 108095 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102795 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 102795 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14084340 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14084340 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14084340 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14084340 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046261 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046261 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.276132 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.276132 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126204 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126204 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104655 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104655 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134998 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134998 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134998 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134998 # 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average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42789.132420 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 42789.132420 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 27478 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17677 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked +system.cpu1.dcache.tags.replacements 363297 # number of replacements +system.cpu1.dcache.tags.tagsinuse 486.117445 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 13019165 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 363645 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.801853 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 71011321250 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.117445 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949448 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.949448 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 60291027 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 60291027 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 8513196 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8513196 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4271027 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4271027 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99804 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 99804 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97081 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 97081 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12784223 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12784223 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12784223 # number of overall hits +system.cpu1.dcache.overall_hits::total 12784223 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 403038 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 403038 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1566274 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1566274 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14187 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14187 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10911 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10911 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1969312 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1969312 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1969312 # number of overall misses +system.cpu1.dcache.overall_misses::total 1969312 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6108097691 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6108097691 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 77891341203 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 77891341203 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131130743 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 131130743 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58206088 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 58206088 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 83999438894 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 83999438894 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 83999438894 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 83999438894 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8916234 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8916234 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5837301 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5837301 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 113991 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 113991 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107992 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 107992 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14753535 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14753535 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14753535 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14753535 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045203 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045203 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268322 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.268322 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124457 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124457 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101035 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101035 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.133481 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.133481 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.133481 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.133481 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15155.140932 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15155.140932 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 49730.341692 # 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number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18156 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3287 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 175 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.517669 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 101.011429 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.003042 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 103.748571 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 304166 # number of writebacks -system.cpu1.dcache.writebacks::total 304166 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172051 # 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number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 142863 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12398 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12398 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10758 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10758 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 370848 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 370848 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 370848 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 370848 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2835218608 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2835218608 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5632564954 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5632564954 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86730259 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86730259 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35684430 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35684430 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8467783562 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 8467783562 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8467783562 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 8467783562 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 62130810008 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 62130810008 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25850406364 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25850406364 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 87981216372 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 87981216372 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026365 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026365 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026276 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026276 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.114695 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.114695 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104655 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104655 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026331 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026331 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026331 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12435.987490 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12435.987490 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39426.338198 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 39426.338198 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6995.504033 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6995.504033 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3317.013385 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3317.013385 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22833.569446 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22833.569446 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327781 # number of writebacks +system.cpu1.dcache.writebacks::total 327781 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171674 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171674 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1403027 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1403027 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1467 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1467 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1574701 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1574701 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1574701 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1574701 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231364 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231364 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163247 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163247 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12720 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10911 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10911 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394611 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394611 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394611 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394611 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2878773157 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2878773157 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7001686259 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7001686259 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89753005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89753005 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36382912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36382912 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9880459416 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9880459416 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9880459416 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9880459416 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169231749012 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169231749012 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25869959988 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25869959988 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 195101709000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 195101709000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025949 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025949 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027966 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027966 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111588 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111588 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101035 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101035 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026747 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026747 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026747 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12442.614914 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12442.614914 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42890.137393 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 42890.137393 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7056.053852 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7056.053852 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3334.516726 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3334.516726 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25038.479454 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25038.479454 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2239,18 +2296,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1737834287366 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737834287366 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1737834287366 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1735350782356 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1735350782356 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1735350782356 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 45161 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42636 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 47884 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50408 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 0d3018ad7..d345e80f2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.526170 # Number of seconds simulated -sim_ticks 2526169857500 # Number of ticks simulated -final_tick 2526169857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.526192 # Number of seconds simulated +sim_ticks 2526192217500 # Number of ticks simulated +final_tick 2526192217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58326 # Simulator instruction rate (inst/s) -host_op_rate 75048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2443063970 # Simulator tick rate (ticks/s) -host_mem_usage 467448 # Number of bytes of host memory used -host_seconds 1034.02 # Real time elapsed on the host -sim_insts 60309637 # Number of instructions simulated -sim_ops 77601213 # Number of ops (including micro ops) simulated +host_inst_rate 56578 # Simulator instruction rate (inst/s) +host_op_rate 72800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2369913329 # Simulator tick rate (ticks/s) +host_mem_usage 467016 # Number of bytes of host memory used +host_seconds 1065.94 # Real time elapsed on the host +sim_insts 60309034 # Number of instructions simulated +sim_ops 77600502 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095320 # Number of bytes read from this memory -system.physmem.bytes_read::total 129433624 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785024 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095192 # Number of bytes read from this memory +system.physmem.bytes_read::total 129433368 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784320 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801096 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800392 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 53 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12463 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142150 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096868 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59141 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142148 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096864 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59130 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1140 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813148 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47319307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1343 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3600439 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51237103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315748 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1193931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692256 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315491 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3600356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51236548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315491 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498033 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1193920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2691954 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47319307 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1343 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315748 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4794370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53929359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096868 # Number of read requests accepted -system.physmem.writeReqs 813159 # Number of write requests accepted -system.physmem.readBursts 15096868 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 960809152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5390400 # Total number of bytes read from write queue -system.physmem.bytesWritten 6824768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 129433624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801096 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 84225 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706499 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943297 # Per bank write bursts -system.physmem.perBankRdBursts::1 937033 # Per bank write bursts -system.physmem.perBankRdBursts::2 936962 # Per bank write bursts -system.physmem.perBankRdBursts::3 936535 # Per bank write bursts -system.physmem.perBankRdBursts::4 942693 # Per bank write bursts -system.physmem.perBankRdBursts::5 936569 # Per bank write bursts -system.physmem.perBankRdBursts::6 936319 # Per bank write bursts -system.physmem.perBankRdBursts::7 936043 # Per bank write bursts -system.physmem.perBankRdBursts::8 943596 # Per bank write bursts -system.physmem.perBankRdBursts::9 936992 # Per bank write bursts -system.physmem.perBankRdBursts::10 936414 # Per bank write bursts -system.physmem.perBankRdBursts::11 935912 # Per bank write bursts -system.physmem.perBankRdBursts::12 943556 # Per bank write bursts -system.physmem.perBankRdBursts::13 937007 # Per bank write bursts -system.physmem.perBankRdBursts::14 937039 # Per bank write bursts -system.physmem.perBankRdBursts::15 936676 # Per bank write bursts -system.physmem.perBankWrBursts::0 6606 # Per bank write bursts -system.physmem.perBankWrBursts::1 6375 # Per bank write bursts -system.physmem.perBankWrBursts::2 6521 # Per bank write bursts -system.physmem.perBankWrBursts::3 6552 # Per bank write bursts -system.physmem.perBankWrBursts::4 6461 # Per bank write bursts -system.physmem.perBankWrBursts::5 6711 # Per bank write bursts -system.physmem.perBankWrBursts::6 6720 # Per bank write bursts -system.physmem.perBankWrBursts::7 6668 # Per bank write bursts -system.physmem.perBankWrBursts::8 7045 # Per bank write bursts -system.physmem.perBankWrBursts::9 6826 # Per bank write bursts -system.physmem.perBankWrBursts::10 6497 # Per bank write bursts -system.physmem.perBankWrBursts::11 6136 # Per bank write bursts -system.physmem.perBankWrBursts::12 7072 # Per bank write bursts -system.physmem.perBankWrBursts::13 6672 # Per bank write bursts -system.physmem.perBankWrBursts::14 6956 # Per bank write bursts -system.physmem.perBankWrBursts::15 6819 # Per bank write bursts +system.physmem.bw_total::cpu.inst 315491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4794277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53928501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096864 # Number of read requests accepted +system.physmem.writeReqs 813148 # Number of write requests accepted +system.physmem.readBursts 15096864 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813148 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 961540928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4658368 # Total number of bytes read from write queue +system.physmem.bytesWritten 6820736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 129433368 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6800392 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 72787 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706544 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4695 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943480 # Per bank write bursts +system.physmem.perBankRdBursts::1 937980 # Per bank write bursts +system.physmem.perBankRdBursts::2 937559 # Per bank write bursts +system.physmem.perBankRdBursts::3 937528 # Per bank write bursts +system.physmem.perBankRdBursts::4 943087 # Per bank write bursts +system.physmem.perBankRdBursts::5 937982 # Per bank write bursts +system.physmem.perBankRdBursts::6 937070 # Per bank write bursts +system.physmem.perBankRdBursts::7 936990 # Per bank write bursts +system.physmem.perBankRdBursts::8 943982 # Per bank write bursts +system.physmem.perBankRdBursts::9 938303 # Per bank write bursts +system.physmem.perBankRdBursts::10 937119 # Per bank write bursts +system.physmem.perBankRdBursts::11 936407 # Per bank write bursts +system.physmem.perBankRdBursts::12 943924 # Per bank write bursts +system.physmem.perBankRdBursts::13 938214 # Per bank write bursts +system.physmem.perBankRdBursts::14 937241 # Per bank write bursts +system.physmem.perBankRdBursts::15 937211 # Per bank write bursts +system.physmem.perBankWrBursts::0 6601 # Per bank write bursts +system.physmem.perBankWrBursts::1 6388 # Per bank write bursts +system.physmem.perBankWrBursts::2 6528 # Per bank write bursts +system.physmem.perBankWrBursts::3 6554 # Per bank write bursts +system.physmem.perBankWrBursts::4 6464 # Per bank write bursts +system.physmem.perBankWrBursts::5 6726 # Per bank write bursts +system.physmem.perBankWrBursts::6 6713 # Per bank write bursts +system.physmem.perBankWrBursts::7 6652 # Per bank write bursts +system.physmem.perBankWrBursts::8 7031 # Per bank write bursts +system.physmem.perBankWrBursts::9 6803 # Per bank write bursts +system.physmem.perBankWrBursts::10 6461 # Per bank write bursts +system.physmem.perBankWrBursts::11 6104 # Per bank write bursts +system.physmem.perBankWrBursts::12 7064 # Per bank write bursts +system.physmem.perBankWrBursts::13 6684 # Per bank write bursts +system.physmem.perBankWrBursts::14 6965 # Per bank write bursts +system.physmem.perBankWrBursts::15 6836 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2526168741500 # Total gap between requests +system.physmem.totGap 2526191083500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 14942208 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154622 # Read request sizes (log2) +system.physmem.readPktSize::6 154618 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59141 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1044851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 985737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938636 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 933228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 933834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2717841 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2709185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3589675 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 37568 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33871 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 34960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 32201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 30053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59130 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1056388 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996212 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 954030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1063517 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 957350 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1019929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2630220 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2535649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3302007 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 132277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114408 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 104766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 100921 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,47 +159,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6376 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5648 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 595 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 544 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6741 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6338 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -208,67 +208,50 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 949853 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1012.832967 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 998.129194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 95.600820 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4614 0.49% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3555 0.37% 0.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1868 0.20% 1.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1270 0.13% 1.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 998 0.11% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 697 0.07% 1.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 628 0.07% 1.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 802 0.08% 1.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 935421 98.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 949853 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5541 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2709.372676 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121858.968991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 5537 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.04% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 995555 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 972.685250 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 907.127186 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 202.423056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22972 2.31% 2.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19885 2.00% 4.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8241 0.83% 5.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2302 0.23% 5.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2369 0.24% 5.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1811 0.18% 5.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8514 0.86% 6.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 964 0.10% 6.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 928497 93.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 995555 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2413.115644 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 115125.420570 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6222 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2.09715e+06-2.62144e+06 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5541 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5541 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.245082 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.302826 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 7.619957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3691 66.61% 66.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 16 0.29% 66.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 178 3.21% 70.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1008 18.19% 88.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 44 0.79% 89.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 25 0.45% 89.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.36% 89.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 16 0.29% 90.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 5 0.09% 90.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 2 0.04% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 90.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.02% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.02% 90.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 2 0.04% 90.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 1 0.02% 90.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 143 2.58% 93.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 305 5.50% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 21 0.38% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 14 0.25% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 20 0.36% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 15 0.27% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 5 0.09% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 3 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5541 # Writes before turning the bus around for reads -system.physmem.totQLat 571195583500 # Total ticks spent queuing -system.physmem.totMemAccLat 674382869750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 75063215000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28124071250 # Total ticks spent accessing banks -system.physmem.avgQLat 38047.64 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1873.36 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6226 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6226 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.117571 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.060113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.446555 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3515 56.46% 56.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 41 0.66% 57.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1615 25.94% 83.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 842 13.52% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 76 1.22% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 41 0.66% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 38 0.61% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 41 0.66% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.26% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6226 # Writes before turning the bus around for reads +system.physmem.totQLat 389908010000 # Total ticks spent queuing +system.physmem.totMemAccLat 671609453750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 75120385000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25952.21 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44921.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44702.21 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.63 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.69 # Average system write bandwidth in MiByte/s @@ -276,15 +259,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.99 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.53 # Average write queue length when enqueuing -system.physmem.readRowHits 14041195 # Number of row buffer hits during reads -system.physmem.writeRowHits 91389 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.53 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.68 # Row buffer hit rate for writes -system.physmem.avgGap 158778.41 # Average gap between requests -system.physmem.pageHitRate 93.47 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.34 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 6.80 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.01 # Average write queue length when enqueuing +system.physmem.readRowHits 14044000 # Number of row buffer hits during reads +system.physmem.writeRowHits 91096 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.45 # Row buffer hit rate for writes +system.physmem.avgGap 158779.96 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2186359463750 # Time in different power states +system.physmem.memoryStateTime::REF 84354920000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 255472398750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -297,50 +284,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54878638 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149508 # Transaction distribution -system.membus.trans_dist::ReadResp 16149508 # Transaction distribution +system.membus.throughput 54877773 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149486 # Transaction distribution +system.membus.trans_dist::ReadResp 16149486 # Transaction distribution system.membus.trans_dist::WriteReq 763349 # Transaction distribution system.membus.trans_dist::WriteResp 763349 # Transaction distribution -system.membus.trans_dist::Writeback 59141 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59130 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4692 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131433 # Transaction distribution -system.membus.trans_dist::ReadExResp 131433 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4695 # Transaction distribution +system.membus.trans_dist::ReadExReq 131451 # Transaction distribution +system.membus.trans_dist::ReadExResp 131451 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272676 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34157069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34157092 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095098 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16696096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19094138 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138632762 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138632762 # Total data (bytes) +system.membus.tot_pkt_size::total 138631802 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138631802 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487078000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486816000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3653000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3620500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17362845500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17362899000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737809043 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4734189076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37210156152 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 36898450149 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -348,7 +335,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48266001 # Throughput (bytes/s) +system.iobus.throughput 48265574 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125556 # Transaction distribution system.iobus.trans_dist::ReadResp 16125556 # Transaction distribution system.iobus.trans_dist::WriteReq 8174 # Transaction distribution @@ -458,18 +445,18 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374870000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37245686848 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 37675624851 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 14755327 # Number of BP lookups -system.cpu.branchPred.condPredicted 11837490 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 706705 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9530563 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7665782 # Number of BTB hits +system.cpu.branchPred.lookups 14753661 # Number of BP lookups +system.cpu.branchPred.condPredicted 11836576 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705670 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9513727 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7668660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.433674 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1400618 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72971 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.606265 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1399145 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72578 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -493,25 +480,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51187284 # DTB read hits -system.cpu.dtb.read_misses 65383 # DTB read misses -system.cpu.dtb.write_hits 11703682 # DTB write hits -system.cpu.dtb.write_misses 15916 # DTB write misses +system.cpu.dtb.read_hits 51183231 # DTB read hits +system.cpu.dtb.read_misses 65223 # DTB read misses +system.cpu.dtb.write_hits 11700953 # DTB write hits +system.cpu.dtb.write_misses 15725 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2464 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3479 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2504 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1363 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51252667 # DTB read accesses -system.cpu.dtb.write_accesses 11719598 # DTB write accesses +system.cpu.dtb.perms_faults 1339 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51248454 # DTB read accesses +system.cpu.dtb.write_accesses 11716678 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62890966 # DTB hits -system.cpu.dtb.misses 81299 # DTB misses -system.cpu.dtb.accesses 62972265 # DTB accesses +system.cpu.dtb.hits 62884184 # DTB hits +system.cpu.dtb.misses 80948 # DTB misses +system.cpu.dtb.accesses 62965132 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -533,8 +520,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 11527099 # ITB inst hits -system.cpu.itb.inst_misses 11249 # ITB inst misses +system.cpu.itb.inst_hits 11525561 # ITB inst hits +system.cpu.itb.inst_misses 11159 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -543,113 +530,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2509 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 2978 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11538348 # ITB inst accesses -system.cpu.itb.hits 11527099 # DTB hits -system.cpu.itb.misses 11249 # DTB misses -system.cpu.itb.accesses 11538348 # DTB accesses -system.cpu.numCycles 477119451 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11536720 # ITB inst accesses +system.cpu.itb.hits 11525561 # DTB hits +system.cpu.itb.misses 11159 # DTB misses +system.cpu.itb.accesses 11536720 # DTB accesses +system.cpu.numCycles 477128882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745347 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90343663 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14755327 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9066400 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20160515 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4659374 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 121718 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 98274067 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2638 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 88444 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2690508 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 430 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11523637 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 709778 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5230 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.730147 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.081756 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29759197 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90327124 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14753661 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9067805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20158177 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4657193 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122600 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 98301886 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2694 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86268 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2686675 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 550 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11522069 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 710692 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5197 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.729776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.081128 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134149007 86.94% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1305162 0.85% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712027 1.11% 88.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2298089 1.49% 90.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2109453 1.37% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1103374 0.72% 92.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555030 1.66% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 746204 0.48% 94.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8315700 5.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 134184573 86.95% 86.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304702 0.85% 87.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713961 1.11% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295969 1.49% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2111581 1.37% 91.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1105061 0.72% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2556088 1.66% 94.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 746376 0.48% 94.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8308877 5.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 154294046 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.189352 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31777956 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100129696 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18080387 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1265250 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3040757 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958128 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172070 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107328179 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 570705 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3040757 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33516419 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38693091 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 55142047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17591419 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6310313 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102323009 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 472 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1000039 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4066050 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 733 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106393961 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 474042454 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432890289 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10421 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78727775 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27666185 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1171025 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1077190 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12642564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19725934 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13308899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965192 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2472766 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95138203 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1987496 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122932074 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165549 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18954995 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47273204 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 505173 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 154294046 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.796739 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.515436 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154327188 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030922 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.189314 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31784305 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100158613 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18079626 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1265080 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3039564 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958546 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172069 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107310478 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 569843 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3039564 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33522780 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38730372 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 55131073 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17590016 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6313383 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102310347 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 498 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 999968 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4068660 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 821 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106387059 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 473967662 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432826370 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10390 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78726997 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27660061 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1170574 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1076856 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12635163 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19719056 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13304976 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1944651 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2472247 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95130107 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1987847 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122918672 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165693 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18947879 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47268855 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 505540 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154327188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.796481 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.515149 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 109928517 71.25% 71.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14405522 9.34% 80.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6874407 4.46% 85.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5677816 3.68% 88.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12311103 7.98% 96.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2805861 1.82% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1693952 1.10% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 468083 0.30% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128785 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 109964387 71.25% 71.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14401004 9.33% 80.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6880878 4.46% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5675452 3.68% 88.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12310168 7.98% 96.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2806019 1.82% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1694480 1.10% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 466491 0.30% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128309 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 154294046 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154327188 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 61713 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61903 0.70% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 4 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available @@ -678,13 +665,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365366 94.65% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411034 4.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364845 94.62% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 413343 4.68% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57971139 47.16% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93360 0.08% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57967032 47.16% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93290 0.08% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.26% # Type of FU issued @@ -697,11 +684,11 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 25 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.26% # Type of FU issued @@ -710,404 +697,440 @@ system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.26% # Ty system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 19 0.00% 47.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.26% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52513425 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12323457 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507324 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12320347 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122932074 # Type of FU issued -system.cpu.iq.rate 0.257655 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8838117 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071894 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409219406 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116097301 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85490758 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23382 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131729199 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12474 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624027 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122918672 # Type of FU issued +system.cpu.iq.rate 0.257622 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8840095 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071918 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409227562 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116082546 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85482417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23345 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12482 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10295 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131717793 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12456 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625155 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4071144 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6793 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30196 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1576838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4064409 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6818 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30381 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1573005 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107946 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 680806 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107982 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 680619 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3040757 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30225758 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434257 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97346977 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205962 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19725934 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13308899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1415361 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3429 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30196 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 351437 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 270055 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 621492 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120854906 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51874598 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2077168 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3039564 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30259815 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434333 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97340803 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205354 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19719056 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13304976 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1415400 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113322 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3328 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30381 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350453 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269952 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 620405 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120843569 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51870507 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2075103 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221278 # number of nop insts executed -system.cpu.iew.exec_refs 64090111 # number of memory reference insts executed -system.cpu.iew.exec_branches 11821235 # Number of branches executed -system.cpu.iew.exec_stores 12215513 # Number of stores executed -system.cpu.iew.exec_rate 0.253301 # Inst execution rate -system.cpu.iew.wb_sent 119911072 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85501046 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47029089 # num instructions producing a value -system.cpu.iew.wb_consumers 87607932 # num instructions consuming a value +system.cpu.iew.exec_nop 222849 # number of nop insts executed +system.cpu.iew.exec_refs 64083354 # number of memory reference insts executed +system.cpu.iew.exec_branches 11822089 # Number of branches executed +system.cpu.iew.exec_stores 12212847 # Number of stores executed +system.cpu.iew.exec_rate 0.253272 # Inst execution rate +system.cpu.iew.wb_sent 119902421 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85492712 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47017508 # num instructions producing a value +system.cpu.iew.wb_consumers 87566112 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.536813 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179182 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.536937 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18687715 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482323 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 537083 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 151253289 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.514049 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.489960 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18682974 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 536093 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151287624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.513928 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.489816 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122784132 81.18% 81.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14644365 9.68% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3917692 2.59% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2132798 1.41% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1620432 1.07% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 975760 0.65% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1598249 1.06% 97.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 715459 0.47% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864402 1.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122817908 81.18% 81.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14643914 9.68% 90.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3918754 2.59% 93.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2134639 1.41% 94.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1621396 1.07% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 973729 0.64% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595383 1.05% 97.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 716191 0.47% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2865710 1.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 151253289 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60460018 # Number of instructions committed -system.cpu.commit.committedOps 77751594 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151287624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60459415 # Number of instructions committed +system.cpu.commit.committedOps 77750883 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386851 # Number of memory references committed -system.cpu.commit.loads 15654790 # Number of loads committed -system.cpu.commit.membars 403577 # Number of memory barriers committed -system.cpu.commit.branches 10306380 # Number of branches committed +system.cpu.commit.refs 27386618 # Number of memory references committed +system.cpu.commit.loads 15654647 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 10306311 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69191623 # Number of committed integer instructions. -system.cpu.commit.function_calls 991253 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864402 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69190973 # Number of committed integer instructions. +system.cpu.commit.function_calls 991245 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 50274217 64.66% 64.66% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87935 0.11% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.77% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 2113 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.78% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 15654647 20.13% 84.91% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731971 15.09% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::total 77750883 # Class of committed instruction +system.cpu.commit.bw_lim_events 2865710 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242979782 # The number of ROB reads -system.cpu.rob.rob_writes 196005989 # The number of ROB writes -system.cpu.timesIdled 1777234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322825405 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575137230 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60309637 # Number of Instructions Simulated -system.cpu.committedOps 77601213 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60309637 # Number of Instructions Simulated -system.cpu.cpi 7.911164 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.911164 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126404 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126404 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 548697999 # number of integer regfile reads -system.cpu.int_regfile_writes 87552825 # number of integer regfile writes -system.cpu.fp_regfile_reads 8408 # number of floating regfile reads -system.cpu.fp_regfile_writes 2932 # number of floating regfile writes -system.cpu.misc_regfile_reads 268236665 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173235 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58867266 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2659080 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2659079 # Transaction distribution +system.cpu.rob.rob_reads 243007370 # The number of ROB reads +system.cpu.rob.rob_writes 195993770 # The number of ROB writes +system.cpu.timesIdled 1776375 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322801694 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575172520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60309034 # Number of Instructions Simulated +system.cpu.committedOps 77600502 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60309034 # Number of Instructions Simulated +system.cpu.cpi 7.911400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.911400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126400 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126400 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 548643015 # number of integer regfile reads +system.cpu.int_regfile_writes 87545924 # number of integer regfile writes +system.cpu.fp_regfile_reads 8332 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 268108891 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173224 # number of misc regfile writes +system.cpu.toL2Bus.throughput 58876928 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658785 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763349 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763349 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607635 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2959 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2975 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246069 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961962 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796085 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30498 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 129069 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917614 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62744960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85505466 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 40992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214572 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148505990 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148505990 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 202724 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3129185667 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607456 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2978 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246178 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246178 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1963155 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5795994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30467 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128822 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7918438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62783488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85496634 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 41888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 148537842 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148537842 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 196596 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128822166 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1474638965 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1475557763 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2549207556 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2549946762 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20255489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19999491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75530794 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74967796 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 980897 # number of replacements -system.cpu.icache.tags.tagsinuse 511.570903 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 10462766 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 981409 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.660964 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 6958078250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.570903 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999162 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999162 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 981488 # number of replacements +system.cpu.icache.tags.tagsinuse 511.574363 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 10460581 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 982000 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10.652323 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6957426250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.574363 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999169 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999169 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 12504958 # Number of tag accesses -system.cpu.icache.tags.data_accesses 12504958 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 10462766 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10462766 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10462766 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10462766 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10462766 # number of overall hits -system.cpu.icache.overall_hits::total 10462766 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060743 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060743 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060743 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060743 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060743 # number of overall misses -system.cpu.icache.overall_misses::total 1060743 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14268635888 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14268635888 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14268635888 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14268635888 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14268635888 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14268635888 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11523509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11523509 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11523509 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11523509 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11523509 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11523509 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092050 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092050 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092050 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092050 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092050 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13451.548479 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13451.548479 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13451.548479 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13451.548479 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7798 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 12503981 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12503981 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 10460581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10460581 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10460581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10460581 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10460581 # number of overall hits +system.cpu.icache.overall_hits::total 10460581 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1061360 # 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number of overall misses -system.cpu.dcache.overall_misses::total 3698776 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9982812336 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9982812336 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 139744433579 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 139744433579 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185287000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185287000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 245503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 245503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 149727245915 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 149727245915 # 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number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24719289 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24719289 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24719289 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050794 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050794 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289800 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289800 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052732 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052732 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000065 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000065 # 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average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15343.937500 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40480.214513 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40480.214513 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 31777 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 23524 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2637 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 274 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.050436 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 85.854015 # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 101516564 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101516564 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13756930 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13756930 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258142 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258142 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242767 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242767 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21015072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21015072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21015072 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 149797518811 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492083 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222201 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256292 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714284 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149679 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149679 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149679 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13568.722855 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13568.722855 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47172.620888 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47172.620888 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13685.767024 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40494.440116 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40494.440116 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32269 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 24322 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2609 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 289 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.368340 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 84.159170 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607635 # number of writebacks -system.cpu.dcache.writebacks::total 607635 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350728 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 350728 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713476 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1349 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3064204 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3064204 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3064204 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385631 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385631 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248941 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248941 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12178 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634572 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634572 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026601 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047473 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000065 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025671 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025671 # 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number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064602 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064602 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064602 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385558 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249052 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249052 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12188 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634610 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634610 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634610 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4962813125 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11330760273 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 145614251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 169497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16293573398 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16293573398 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182335819750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26860394736 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209196214486 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026605 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024364 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047555 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025678 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025678 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12871.767996 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45495.560256 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11947.345832 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25674.939566 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25674.939566 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1413,16 +1436,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1715151162848 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1715151162848 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1715151162848 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1712402234851 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1712402234851 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1712402234851 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83034 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 8e01cba8d..8f1b31c18 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,172 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403854 # Number of seconds simulated -sim_ticks 2403853586500 # Number of ticks simulated -final_tick 2403853586500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403852 # Number of seconds simulated +sim_ticks 2403852457500 # Number of ticks simulated +final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 171159 # Simulator instruction rate (inst/s) -host_op_rate 219830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6819657603 # Simulator tick rate (ticks/s) -host_mem_usage 469520 # Number of bytes of host memory used -host_seconds 352.49 # Real time elapsed on the host -sim_insts 60331708 # Number of instructions simulated -sim_ops 77487722 # Number of ops (including micro ops) simulated +host_inst_rate 165592 # Simulator instruction rate (inst/s) +host_op_rate 212680 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6597855857 # Simulator tick rate (ticks/s) +host_mem_usage 469068 # Number of bytes of host memory used +host_seconds 364.34 # Real time elapsed on the host +sim_insts 60331653 # Number of instructions simulated +sim_ops 77487544 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7053720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 63616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 681152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1342304 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 63616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 762760 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298364 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558196 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759176 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10643 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2912 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20981 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512403 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58490 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324591 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389549 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812444 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764586 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2934338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 283358 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 558397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213314 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26464 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77529 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317307 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557233 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540118 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648208 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811809 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557233 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3474456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 349609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77529 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1206604 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54670195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446822 # Number of read requests accepted -system.physmem.writeReqs 446449 # Number of write requests accepted -system.physmem.readBursts 13446822 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860596480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue -system.physmem.bytesWritten 2823168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109564448 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2810956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402307 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2362 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835680 # Per bank write bursts -system.physmem.perBankRdBursts::1 835344 # Per bank write bursts -system.physmem.perBankRdBursts::2 835508 # Per bank write bursts -system.physmem.perBankRdBursts::3 835965 # Per bank write bursts -system.physmem.perBankRdBursts::4 837088 # Per bank write bursts -system.physmem.perBankRdBursts::5 837779 # Per bank write bursts -system.physmem.perBankRdBursts::6 837907 # Per bank write bursts -system.physmem.perBankRdBursts::7 839147 # Per bank write bursts -system.physmem.perBankRdBursts::8 840641 # Per bank write bursts -system.physmem.perBankRdBursts::9 843268 # Per bank write bursts -system.physmem.perBankRdBursts::10 843373 # Per bank write bursts -system.physmem.perBankRdBursts::11 843869 # Per bank write bursts -system.physmem.perBankRdBursts::12 845852 # Per bank write bursts -system.physmem.perBankRdBursts::13 846016 # Per bank write bursts -system.physmem.perBankRdBursts::14 844806 # Per bank write bursts -system.physmem.perBankRdBursts::15 844577 # Per bank write bursts -system.physmem.perBankWrBursts::0 2668 # Per bank write bursts -system.physmem.perBankWrBursts::1 2526 # Per bank write bursts -system.physmem.perBankWrBursts::2 2530 # Per bank write bursts -system.physmem.perBankWrBursts::3 3005 # Per bank write bursts -system.physmem.perBankWrBursts::4 3419 # Per bank write bursts -system.physmem.perBankWrBursts::5 3167 # Per bank write bursts -system.physmem.perBankWrBursts::6 2515 # Per bank write bursts -system.physmem.perBankWrBursts::7 2303 # Per bank write bursts -system.physmem.perBankWrBursts::8 2186 # Per bank write bursts -system.physmem.perBankWrBursts::9 2396 # Per bank write bursts -system.physmem.perBankWrBursts::10 2346 # Per bank write bursts -system.physmem.perBankWrBursts::11 2792 # Per bank write bursts -system.physmem.perBankWrBursts::12 3710 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446501 # Number of read requests accepted +system.physmem.writeReqs 446412 # Number of write requests accepted +system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue +system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835689 # Per bank write bursts +system.physmem.perBankRdBursts::1 835334 # Per bank write bursts +system.physmem.perBankRdBursts::2 835514 # Per bank write bursts +system.physmem.perBankRdBursts::3 835992 # Per bank write bursts +system.physmem.perBankRdBursts::4 837083 # Per bank write bursts +system.physmem.perBankRdBursts::5 837766 # Per bank write bursts +system.physmem.perBankRdBursts::6 837910 # Per bank write bursts +system.physmem.perBankRdBursts::7 839140 # Per bank write bursts +system.physmem.perBankRdBursts::8 840643 # Per bank write bursts +system.physmem.perBankRdBursts::9 843328 # Per bank write bursts +system.physmem.perBankRdBursts::10 843395 # Per bank write bursts +system.physmem.perBankRdBursts::11 843892 # Per bank write bursts +system.physmem.perBankRdBursts::12 845429 # Per bank write bursts +system.physmem.perBankRdBursts::13 846004 # Per bank write bursts +system.physmem.perBankRdBursts::14 844795 # Per bank write bursts +system.physmem.perBankRdBursts::15 844586 # Per bank write bursts +system.physmem.perBankWrBursts::0 2674 # Per bank write bursts +system.physmem.perBankWrBursts::1 2534 # Per bank write bursts +system.physmem.perBankWrBursts::2 2538 # Per bank write bursts +system.physmem.perBankWrBursts::3 3024 # Per bank write bursts +system.physmem.perBankWrBursts::4 3410 # Per bank write bursts +system.physmem.perBankWrBursts::5 3131 # Per bank write bursts +system.physmem.perBankWrBursts::6 2493 # Per bank write bursts +system.physmem.perBankWrBursts::7 2267 # Per bank write bursts +system.physmem.perBankWrBursts::8 2164 # Per bank write bursts +system.physmem.perBankWrBursts::9 2378 # Per bank write bursts +system.physmem.perBankWrBursts::10 2328 # Per bank write bursts +system.physmem.perBankWrBursts::11 2803 # Per bank write bursts +system.physmem.perBankWrBursts::12 3718 # Per bank write bursts system.physmem.perBankWrBursts::13 3446 # Per bank write bursts -system.physmem.perBankWrBursts::14 2600 # Per bank write bursts -system.physmem.perBankWrBursts::15 2503 # Per bank write bursts +system.physmem.perBankWrBursts::14 2595 # Per bank write bursts +system.physmem.perBankWrBursts::15 2507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402817511500 # Total gap between requests +system.physmem.totGap 2402816386500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13411280 # Read request sizes (log2) +system.physmem.readPktSize::2 0 # Read request sizes (log2) +system.physmem.readPktSize::3 13410864 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35534 # Read request sizes (log2) +system.physmem.readPktSize::6 35637 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429363 # Write request sizes (log2) +system.physmem.writePktSize::2 429313 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17086 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 867414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 844196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 838512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 839224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 838671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 838847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2475363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2475187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3292199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 20391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 19694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 19741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 19565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17099 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -184,8 +180,8 @@ system.physmem.rdQLenPdf::30 0 # Wh system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see @@ -196,48 +192,48 @@ system.physmem.wrQLenPdf::10 93 # Wh system.physmem.wrQLenPdf::11 93 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1625 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 1860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 1651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 1601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 1586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 683 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -246,79 +242,63 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 844644 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1019.942660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1014.395909 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 58.300980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1516 0.18% 0.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 1237 0.15% 0.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 570 0.07% 0.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 375 0.04% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 256 0.03% 0.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 198 0.02% 0.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 155 0.02% 0.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 158 0.02% 0.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 840179 99.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 844644 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 1621 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 8295.373226 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 315033.644502 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 1620 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.06% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 1621 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 1621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.212832 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 24.563019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.121341 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 1 0.06% 0.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.12% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 1 0.06% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.06% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.06% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.06% 0.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.12% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 6 0.37% 0.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 488 30.10% 31.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 27 1.67% 32.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 60 3.70% 36.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 333 20.54% 57.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 10 0.62% 57.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.19% 57.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.12% 57.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.19% 58.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.12% 58.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.19% 58.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.31% 58.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 4 0.25% 58.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.31% 59.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.43% 59.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 3 0.19% 59.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 2 0.12% 60.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 8 0.49% 60.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.12% 60.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.06% 60.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 50 3.08% 63.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 4 0.25% 64.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 167 10.30% 74.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 328 20.23% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 16 0.99% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 15 0.93% 96.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 23 1.42% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 17 1.05% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 13 0.80% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 2 0.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 1621 # Writes before turning the bus around for reads -system.physmem.totQLat 510864117000 # Total ticks spent queuing -system.physmem.totMemAccLat 601782495750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67234100000 # Total ticks spent in databus transfers -system.physmem.totBankLat 23684278750 # Total ticks spent accessing banks -system.physmem.avgQLat 37991.44 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1761.33 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads +system.physmem.totQLat 345783645500 # Total ticks spent queuing +system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44752.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s @@ -326,15 +306,19 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 8.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 5.41 # Average write queue length when enqueuing -system.physmem.readRowHits 12595156 # Number of row buffer hits during reads -system.physmem.writeRowHits 38053 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.21 # Row buffer hit rate for writes -system.physmem.avgGap 172948.29 # Average gap between requests -system.physmem.pageHitRate 93.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 2.74 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing +system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing +system.physmem.readRowHits 12586631 # Number of row buffer hits during reads +system.physmem.writeRowHits 37847 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes +system.physmem.avgGap 172952.67 # Average gap between requests +system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states +system.physmem.memoryStateTime::REF 80269800000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -347,341 +331,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55667457 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13781916 # Transaction distribution -system.membus.trans_dist::ReadResp 13781916 # Transaction distribution -system.membus.trans_dist::WriteReq 432200 # Transaction distribution -system.membus.trans_dist::WriteResp 432200 # Transaction distribution -system.membus.trans_dist::Writeback 17086 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2361 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2362 # Transaction distribution -system.membus.trans_dist::ReadExReq 27973 # Transaction distribution -system.membus.trans_dist::ReadExResp 27973 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951620 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683428 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26822560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26822560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28505988 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5085164 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5821052 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107290240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107290240 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113111292 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816415 # Total data (bytes) +system.membus.throughput 55667977 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13781620 # Transaction distribution +system.membus.trans_dist::ReadResp 13781620 # Transaction distribution +system.membus.trans_dist::WriteReq 432153 # Transaction distribution +system.membus.trans_dist::WriteResp 432153 # Transaction distribution +system.membus.trans_dist::Writeback 17099 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution +system.membus.trans_dist::ReadExReq 28041 # Transaction distribution +system.membus.trans_dist::ReadExResp 28041 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817603 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416850000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 198000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14576843000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1595419615 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1596663785 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33523642000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33229062000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63235 # number of replacements -system.l2c.tags.tagsinuse 50381.174231 # Cycle average of tags in use -system.l2c.tags.total_refs 1749008 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128627 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.597518 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375559570500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36838.397677 # Average occupied blocks per requestor +system.l2c.tags.replacements 63248 # number of replacements +system.l2c.tags.tagsinuse 50398.234461 # Cycle average of tags in use +system.l2c.tags.total_refs 1749256 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128641 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.597966 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5238.516596 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3833.196793 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 493.229672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 688.317801 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.879272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1684.639749 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1594.998425 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562109 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079933 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007526 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010503 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000135 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024338 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768756 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6490 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55882 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17681539 # Number of tag accesses -system.l2c.tags.data_accesses 17681539 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8692 # number of ReadReq hits +system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17683113 # Number of tag accesses +system.l2c.tags.data_accesses 17683113 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468000 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177035 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2622 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 129681 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18896 # 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average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58128.521127 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61687.954375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -854,52 +799,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805312 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019677 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019676 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432200 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432200 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1507 # Transaction distribution +system.toL2Bus.throughput 58808825 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432153 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80476 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80476 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830192 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419562 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15560 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52654 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3317968 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26544384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37373820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21604 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86116 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64025924 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141258487 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176910263 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1508 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80528 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80528 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830481 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419466 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15414 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52803 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3318164 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26553408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37366366 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21516 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64027794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141267007 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100732 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870334166 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845880168 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10179455 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31260469 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758934 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13774305 # Transaction distribution -system.iobus.trans_dist::ReadResp 13774305 # Transaction distribution -system.iobus.trans_dist::WriteReq 2774 # Transaction distribution -system.iobus.trans_dist::WriteResp 2774 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3022 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758959 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution +system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution +system.iobus.trans_dist::WriteReq 2776 # Transaction distribution +system.iobus.trans_dist::WriteResp 2776 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716614 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -915,18 +860,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731598 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26822560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26822560 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27554158 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6044 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712940 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -942,18 +887,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735468 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107290240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107290240 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108025708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209339 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209343 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1511000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 126000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -961,7 +906,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358810000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -993,11 +938,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13411280000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 728824000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33525822000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -1022,25 +967,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7997782 # DTB read hits -system.cpu0.dtb.read_misses 6203 # DTB read misses -system.cpu0.dtb.write_hits 6595987 # DTB write hits -system.cpu0.dtb.write_misses 1983 # DTB write misses +system.cpu0.dtb.read_hits 7995700 # DTB read hits +system.cpu0.dtb.read_misses 6195 # DTB read misses +system.cpu0.dtb.write_hits 6594454 # DTB write hits +system.cpu0.dtb.write_misses 1984 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5673 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8003985 # DTB read accesses -system.cpu0.dtb.write_accesses 6597970 # DTB write accesses +system.cpu0.dtb.read_accesses 8001895 # DTB read accesses +system.cpu0.dtb.write_accesses 6596438 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14593769 # DTB hits -system.cpu0.dtb.misses 8186 # DTB misses -system.cpu0.dtb.accesses 14601955 # DTB accesses +system.cpu0.dtb.hits 14590154 # DTB hits +system.cpu0.dtb.misses 8179 # DTB misses +system.cpu0.dtb.accesses 14598333 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1062,433 +1007,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32336935 # ITB inst hits -system.cpu0.itb.inst_misses 3451 # ITB inst misses +system.cpu0.itb.inst_hits 32327896 # ITB inst hits +system.cpu0.itb.inst_misses 3449 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32340386 # ITB inst accesses -system.cpu0.itb.hits 32336935 # DTB hits -system.cpu0.itb.misses 3451 # DTB misses -system.cpu0.itb.accesses 32340386 # DTB accesses -system.cpu0.numCycles 113724377 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses +system.cpu0.itb.hits 32327896 # DTB hits +system.cpu0.itb.misses 3449 # DTB misses +system.cpu0.itb.accesses 32331345 # DTB accesses +system.cpu0.numCycles 113683212 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31861763 # Number of instructions committed -system.cpu0.committedOps 42032224 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37415212 # Number of integer alu accesses +system.cpu0.committedInsts 31852389 # Number of instructions committed +system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1199152 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4246542 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37415212 # number of integer instructions +system.cpu0.num_func_calls 1199046 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37405417 # number of integer instructions system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193939915 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39523913 # number of times the integer registers were written +system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15261638 # number of memory refs -system.cpu0.num_load_insts 8366552 # Number of load instructions -system.cpu0.num_store_insts 6895086 # Number of store instructions -system.cpu0.num_idle_cycles 110931893.434026 # Number of idle cycles -system.cpu0.num_busy_cycles 2792483.565974 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024555 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975445 # Percentage of idle cycles -system.cpu0.Branches 5615139 # Number of branches fetched +system.cpu0.num_mem_refs 15257672 # number of memory refs +system.cpu0.num_load_insts 8364380 # Number of load instructions +system.cpu0.num_store_insts 6893292 # Number of store instructions +system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles +system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles +system.cpu0.Branches 5614656 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction +system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction +system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction +system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction +system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 42097264 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891249 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602369 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43668526 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891761 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.968867 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8187850250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.923201 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.626935 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.052233 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966647 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014896 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017680 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999223 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891512 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602542 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43658005 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892024 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.942635 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8184230000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.829489 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.587272 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.185782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966464 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014819 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017941 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45475856 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45475856 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31863243 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8064619 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3740664 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43668526 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31863243 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8064619 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3740664 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43668526 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31863243 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8064619 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3740664 # number of overall hits -system.cpu0.icache.overall_hits::total 43668526 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476340 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130939 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 308276 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915555 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476340 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130939 # 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number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1766616750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4157487812 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5924104562 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32339583 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8195558 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4048940 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 44584081 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32339583 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8195558 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4048940 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 44584081 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32339583 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8195558 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4048940 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 44584081 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014729 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015977 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076137 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020535 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014729 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015977 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076137 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8190394 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4052904 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44573840 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014737 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015992 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076094 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020546 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014737 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015992 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076094 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020546 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014737 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015992 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076094 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020546 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13494.680607 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13494.116747 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6474.062303 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13494.680607 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13494.116747 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6474.062303 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13494.680607 # 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number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 130939 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 284497 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 415436 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1504362250 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3384633315 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4888995565 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1504362250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3384633315 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4888995565 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1504362250 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970799 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015829 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013367 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.042290 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.061376 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.893452 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970786 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015745 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013464 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026683 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 92428 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 184316 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 276744 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 92428 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 184316 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 276744 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779830000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1694363864 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2474193864 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 934250758 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1848694495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2782945253 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19406250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38393502 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70751306863 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033859 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026666 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014074 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008021 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050558 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042958 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019443 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008026 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050186 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043054 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020255 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011508 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011508 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011505 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011505 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1522,25 +1502,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2097642 # DTB read hits +system.cpu1.dtb.read_hits 2096038 # DTB read hits system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1419704 # DTB write hits -system.cpu1.dtb.write_misses 373 # DTB write misses +system.cpu1.dtb.write_hits 1418402 # DTB write hits +system.cpu1.dtb.write_misses 376 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1767 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2099731 # DTB read accesses -system.cpu1.dtb.write_accesses 1420077 # DTB write accesses +system.cpu1.dtb.read_accesses 2098127 # DTB read accesses +system.cpu1.dtb.write_accesses 1418778 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3517346 # DTB hits -system.cpu1.dtb.misses 2462 # DTB misses -system.cpu1.dtb.accesses 3519808 # DTB accesses +system.cpu1.dtb.hits 3514440 # DTB hits +system.cpu1.dtb.misses 2465 # DTB misses +system.cpu1.dtb.accesses 3516905 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1562,8 +1542,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8195558 # ITB inst hits -system.cpu1.itb.inst_misses 1195 # ITB inst misses +system.cpu1.itb.inst_hits 8190394 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1572,51 +1552,86 @@ system.cpu1.itb.flush_tlb 554 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8196753 # ITB inst accesses -system.cpu1.itb.hits 8195558 # DTB hits -system.cpu1.itb.misses 1195 # DTB misses -system.cpu1.itb.accesses 8196753 # DTB accesses -system.cpu1.numCycles 584703165 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses +system.cpu1.itb.hits 8190394 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8191594 # DTB accesses +system.cpu1.numCycles 584767176 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7984738 # Number of instructions committed -system.cpu1.committedOps 10135701 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9107037 # Number of integer alu accesses +system.cpu1.committedInsts 7979697 # Number of instructions committed +system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304651 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1115193 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9107037 # number of integer instructions +system.cpu1.num_func_calls 304592 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9101420 # number of integer instructions system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 53092313 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9899825 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684662 # number of memory refs -system.cpu1.num_load_insts 2190856 # Number of load instructions -system.cpu1.num_store_insts 1493806 # Number of store instructions -system.cpu1.num_idle_cycles 548865377.428164 # Number of idle cycles -system.cpu1.num_busy_cycles 35837787.571836 # Number of busy cycles -system.cpu1.not_idle_fraction 0.061292 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.938708 # Percentage of idle cycles -system.cpu1.Branches 1448177 # Number of branches fetched +system.cpu1.num_mem_refs 3681879 # number of memory refs +system.cpu1.num_load_insts 2189240 # Number of load instructions +system.cpu1.num_store_insts 1492639 # Number of store instructions +system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles +system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles +system.cpu1.Branches 1446987 # Number of branches fetched +system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction +system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction +system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction +system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 10316152 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4782343 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3901882 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223184 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3184465 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528356 # Number of BTB hits +system.cpu2.branchPred.lookups 4788852 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.396571 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413120 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21664 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1640,25 +1655,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10925413 # DTB read hits -system.cpu2.dtb.read_misses 23157 # DTB read misses -system.cpu2.dtb.write_hits 3347832 # DTB write hits -system.cpu2.dtb.write_misses 6500 # DTB write misses +system.cpu2.dtb.read_hits 10930564 # DTB read hits +system.cpu2.dtb.read_misses 23215 # DTB read misses +system.cpu2.dtb.write_hits 3350483 # DTB write hits +system.cpu2.dtb.write_misses 6482 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 739 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 476 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10948570 # DTB read accesses -system.cpu2.dtb.write_accesses 3354332 # DTB write accesses +system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10953779 # DTB read accesses +system.cpu2.dtb.write_accesses 3356965 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14273245 # DTB hits -system.cpu2.dtb.misses 29657 # DTB misses -system.cpu2.dtb.accesses 14302902 # DTB accesses +system.cpu2.dtb.hits 14281047 # DTB hits +system.cpu2.dtb.misses 29697 # DTB misses +system.cpu2.dtb.accesses 14310744 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1680,159 +1695,159 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4050371 # ITB inst hits -system.cpu2.itb.inst_misses 4655 # ITB inst misses +system.cpu2.itb.inst_hits 4054306 # ITB inst hits +system.cpu2.itb.inst_misses 4589 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1717 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 991 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4055026 # ITB inst accesses -system.cpu2.itb.hits 4050371 # DTB hits -system.cpu2.itb.misses 4655 # DTB misses -system.cpu2.itb.accesses 4055026 # DTB accesses -system.cpu2.numCycles 88306923 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses +system.cpu2.itb.hits 4054306 # DTB hits +system.cpu2.itb.misses 4589 # DTB misses +system.cpu2.itb.accesses 4058895 # DTB accesses +system.cpu2.numCycles 88316329 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9346989 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32490356 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4782343 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2941476 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6854845 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758076 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51100 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19188137 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 924 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33833 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 718254 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4048944 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289644 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2020 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37402774 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.043825 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431125 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30553136 81.69% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385541 1.03% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516309 1.38% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819811 2.19% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 629209 1.68% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341976 0.91% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1043472 2.79% 91.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229749 0.61% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2883571 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37402774 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054156 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367925 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9974482 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19754417 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6192036 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 324676 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1156258 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608942 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 52938 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36945008 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178323 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1156258 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10522715 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6823267 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11427905 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5953488 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1518249 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34855169 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324878 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 884563 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 125 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37394312 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160859531 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148302897 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3365 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26531284 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10863027 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285247 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261616 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3319534 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6621271 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899723 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 529692 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 779693 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32174765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 504636 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34747602 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55361 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7180763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19089893 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148627 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37402774 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929011 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.590003 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24715445 66.08% 66.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3980638 10.64% 76.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2310084 6.18% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974798 5.28% 88.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2777209 7.43% 95.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 968528 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496348 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144954 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34770 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37402774 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19778 1.30% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1391818 91.56% 92.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 108581 7.14% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8338 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19786480 56.94% 56.97% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28071 0.08% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued @@ -1845,129 +1860,164 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11408808 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3515506 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34747602 # Type of FU issued -system.cpu2.iq.rate 0.393487 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1520177 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043749 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108495492 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39865371 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28048299 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7541 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3951 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3361 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36255412 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4029 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205816 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued +system.cpu2.iq.rate 0.393736 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533232 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1949 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9487 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562230 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5287398 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344554 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1156258 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5195373 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88422 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32761739 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61550 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6621271 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899723 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362828 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29785 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2577 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9487 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107399 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89296 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196695 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33832847 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11137918 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914755 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82338 # number of nop insts executed -system.cpu2.iew.exec_refs 14620271 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3761250 # Number of branches executed -system.cpu2.iew.exec_stores 3482353 # Number of stores executed -system.cpu2.iew.exec_rate 0.383128 # Inst execution rate -system.cpu2.iew.wb_sent 33431998 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28051660 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16098716 # num instructions producing a value -system.cpu2.iew.wb_consumers 29087027 # num instructions consuming a value +system.cpu2.iew.exec_nop 82169 # number of nop insts executed +system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3765120 # Number of branches executed +system.cpu2.iew.exec_stores 3485223 # Number of stores executed +system.cpu2.iew.exec_rate 0.383361 # Inst execution rate +system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16112995 # num instructions producing a value +system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317661 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553467 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7131660 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356009 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171002 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36246314 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700075 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.737192 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27334959 75.41% 75.41% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4433375 12.23% 87.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1255912 3.46% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639801 1.77% 92.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 511761 1.41% 94.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317445 0.88% 95.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418775 1.16% 96.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 310656 0.86% 97.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1023630 2.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36246314 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20540563 # Number of instructions committed -system.cpu2.commit.committedOps 25375153 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20554943 # Number of instructions committed +system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8425532 # Number of memory references committed -system.cpu2.commit.loads 5088039 # Number of loads committed -system.cpu2.commit.membars 94081 # Number of memory barriers committed -system.cpu2.commit.branches 3238597 # Number of branches committed +system.cpu2.commit.refs 8432259 # Number of memory references committed +system.cpu2.commit.loads 5091796 # Number of loads committed +system.cpu2.commit.membars 94283 # Number of memory barriers committed +system.cpu2.commit.branches 3240263 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22633154 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295425 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1023630 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295510 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67208837 # The number of ROB reads -system.cpu2.rob.rob_writes 66213984 # The number of ROB writes -system.cpu2.timesIdled 359252 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50904149 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3546216081 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20485207 # Number of Instructions Simulated -system.cpu2.committedOps 25319797 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20485207 # Number of Instructions Simulated -system.cpu2.cpi 4.310765 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.310765 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231977 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231977 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156999830 # number of integer regfile reads -system.cpu2.int_regfile_writes 29869338 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46882 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes -system.cpu2.misc_regfile_reads 67020139 # number of misc regfile reads -system.cpu2.misc_regfile_writes 296788 # number of misc regfile writes +system.cpu2.rob.rob_reads 67255841 # The number of ROB reads +system.cpu2.rob.rob_writes 66282532 # The number of ROB writes +system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20499567 # Number of Instructions Simulated +system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20499567 # Number of Instructions Simulated +system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads +system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes +system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1984,10 +2034,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1539425711000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index ef9bf74a4..2ae3638d8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,166 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.550648 # Number of seconds simulated -sim_ticks 2550647964000 # Number of ticks simulated -final_tick 2550647964000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.550603 # Number of seconds simulated +sim_ticks 2550603285500 # Number of ticks simulated +final_tick 2550603285500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57676 # Simulator instruction rate (inst/s) -host_op_rate 74213 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2439007396 # Simulator tick rate (ticks/s) -host_mem_usage 470664 # Number of bytes of host memory used -host_seconds 1045.77 # Real time elapsed on the host -sim_insts 60315890 # Number of instructions simulated -sim_ops 77609880 # Number of ops (including micro ops) simulated +host_inst_rate 56179 # Simulator instruction rate (inst/s) +host_op_rate 72287 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2375661490 # Simulator tick rate (ticks/s) +host_mem_usage 471120 # Number of bytes of host memory used +host_seconds 1073.64 # Real time elapsed on the host +sim_insts 60315997 # Number of instructions simulated +sim_ops 77609994 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1984 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 483008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5043284 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 315584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4051356 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 483008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 315584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798592 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3785856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1521376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1494724 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801956 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 487168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5091220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 310848 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4002308 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 487168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 310848 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1521388 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1494684 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801544 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 31 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7547 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 78836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 63309 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293483 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59154 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380344 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373681 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813179 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47482259 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 803 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7612 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 79585 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4857 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 62537 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293452 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59148 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380347 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 373671 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813166 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47483091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 778 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 189367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1977256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123727 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1588363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51362077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 189367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123727 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313094 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 596466 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 586017 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2666756 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484272 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47482259 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 803 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 191001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1996085 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 121872 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1569161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51362340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 191001 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 121872 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 312873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 596482 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 586012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2666641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484148 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47483091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 778 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 189367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2573722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2174381 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54028833 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293483 # Number of read requests accepted -system.physmem.writeReqs 813179 # Number of write requests accepted -system.physmem.readBursts 15293483 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813179 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976671488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2111424 # Total number of bytes read from write queue -system.physmem.bytesWritten 6834624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131006576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6801956 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 32991 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706366 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4694 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955809 # Per bank write bursts -system.physmem.perBankRdBursts::1 953120 # Per bank write bursts -system.physmem.perBankRdBursts::2 953063 # Per bank write bursts -system.physmem.perBankRdBursts::3 953290 # Per bank write bursts -system.physmem.perBankRdBursts::4 955524 # Per bank write bursts -system.physmem.perBankRdBursts::5 952811 # Per bank write bursts -system.physmem.perBankRdBursts::6 952747 # Per bank write bursts -system.physmem.perBankRdBursts::7 952554 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts -system.physmem.perBankRdBursts::9 953015 # Per bank write bursts -system.physmem.perBankRdBursts::10 952848 # Per bank write bursts -system.physmem.perBankRdBursts::11 952579 # Per bank write bursts -system.physmem.perBankRdBursts::12 956184 # Per bank write bursts -system.physmem.perBankRdBursts::13 953741 # Per bank write bursts -system.physmem.perBankRdBursts::14 953594 # Per bank write bursts -system.physmem.perBankRdBursts::15 953459 # Per bank write bursts -system.physmem.perBankWrBursts::0 6616 # Per bank write bursts -system.physmem.perBankWrBursts::1 6407 # Per bank write bursts -system.physmem.perBankWrBursts::2 6542 # Per bank write bursts -system.physmem.perBankWrBursts::3 6564 # Per bank write bursts -system.physmem.perBankWrBursts::4 6491 # Per bank write bursts -system.physmem.perBankWrBursts::5 6761 # Per bank write bursts -system.physmem.perBankWrBursts::6 6753 # Per bank write bursts -system.physmem.perBankWrBursts::7 6706 # Per bank write bursts -system.physmem.perBankWrBursts::8 7029 # Per bank write bursts -system.physmem.perBankWrBursts::9 6806 # Per bank write bursts -system.physmem.perBankWrBursts::10 6476 # Per bank write bursts -system.physmem.perBankWrBursts::11 6118 # Per bank write bursts -system.physmem.perBankWrBursts::12 7056 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 191001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2592566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 121872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2155173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54028981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293452 # Number of read requests accepted +system.physmem.writeReqs 813166 # Number of write requests accepted +system.physmem.readBursts 15293452 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 977025792 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1755136 # Total number of bytes read from write queue +system.physmem.bytesWritten 6829888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131004952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6801544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 27424 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706426 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4680 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955870 # Per bank write bursts +system.physmem.perBankRdBursts::1 953353 # Per bank write bursts +system.physmem.perBankRdBursts::2 953267 # Per bank write bursts +system.physmem.perBankRdBursts::3 953402 # Per bank write bursts +system.physmem.perBankRdBursts::4 955744 # Per bank write bursts +system.physmem.perBankRdBursts::5 953745 # Per bank write bursts +system.physmem.perBankRdBursts::6 953482 # Per bank write bursts +system.physmem.perBankRdBursts::7 953247 # Per bank write bursts +system.physmem.perBankRdBursts::8 956258 # Per bank write bursts +system.physmem.perBankRdBursts::9 953771 # Per bank write bursts +system.physmem.perBankRdBursts::10 953551 # Per bank write bursts +system.physmem.perBankRdBursts::11 953111 # Per bank write bursts +system.physmem.perBankRdBursts::12 956206 # Per bank write bursts +system.physmem.perBankRdBursts::13 953857 # Per bank write bursts +system.physmem.perBankRdBursts::14 953612 # Per bank write bursts +system.physmem.perBankRdBursts::15 953552 # Per bank write bursts +system.physmem.perBankWrBursts::0 6609 # Per bank write bursts +system.physmem.perBankWrBursts::1 6381 # Per bank write bursts +system.physmem.perBankWrBursts::2 6537 # Per bank write bursts +system.physmem.perBankWrBursts::3 6560 # Per bank write bursts +system.physmem.perBankWrBursts::4 6488 # Per bank write bursts +system.physmem.perBankWrBursts::5 6754 # Per bank write bursts +system.physmem.perBankWrBursts::6 6745 # Per bank write bursts +system.physmem.perBankWrBursts::7 6685 # Per bank write bursts +system.physmem.perBankWrBursts::8 7023 # Per bank write bursts +system.physmem.perBankWrBursts::9 6801 # Per bank write bursts +system.physmem.perBankWrBursts::10 6470 # Per bank write bursts +system.physmem.perBankWrBursts::11 6120 # Per bank write bursts +system.physmem.perBankWrBursts::12 7060 # Per bank write bursts system.physmem.perBankWrBursts::13 6677 # Per bank write bursts -system.physmem.perBankWrBursts::14 6959 # Per bank write bursts -system.physmem.perBankWrBursts::15 6830 # Per bank write bursts +system.physmem.perBankWrBursts::14 6963 # Per bank write bursts +system.physmem.perBankWrBursts::15 6844 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2550646795500 # Total gap between requests +system.physmem.totGap 2550602119500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 44 # Read request sizes (log2) +system.physmem.readPktSize::2 38 # Read request sizes (log2) system.physmem.readPktSize::3 15138816 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154623 # Read request sizes (log2) +system.physmem.readPktSize::6 154598 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754025 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59154 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1055042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 994364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 947765 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 947544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 945397 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 945218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2783572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2783267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3699218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 24042 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22770 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 21886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 21619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59148 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1066844 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1068011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 971384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1033822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2692544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2602827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3401172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19066 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -174,61 +162,61 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2390 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5855 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4875 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4842 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 852 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 265 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -237,93 +225,76 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 965273 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1013.486813 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 999.850047 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 92.541667 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 4202 0.44% 0.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3517 0.36% 0.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1855 0.19% 0.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1291 0.13% 1.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 949 0.10% 1.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 717 0.07% 1.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 589 0.06% 1.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 765 0.08% 1.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 951388 98.56% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 965273 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5001 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3051.486103 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 52637.524815 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 4974 99.46% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.48% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.16% 99.64% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 6 0.12% 99.76% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.78% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 2 0.04% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.84% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.14% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.187598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 908.669037 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 201.227455 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22588 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20116 1.99% 4.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8785 0.87% 5.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2331 0.23% 5.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2167 0.21% 5.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1761 0.17% 5.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9115 0.90% 6.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 858 0.08% 6.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943241 93.30% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2514.580135 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47785.198367 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6044 99.56% 99.56% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::65536-131071 1 0.02% 99.57% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 6 0.10% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 1 0.02% 99.82% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 2 0.03% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5001 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5001 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.353929 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.695200 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.701170 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 8 0.16% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.04% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 3 0.06% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.02% 0.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 8 0.16% 0.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.02% 0.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.06% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 5 0.10% 0.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 2 0.04% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 5 0.10% 0.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.04% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 1 0.02% 0.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 10 0.20% 1.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2816 56.31% 57.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 26 0.52% 57.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 135 2.70% 60.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 879 17.58% 78.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 49 0.98% 79.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 23 0.46% 79.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 15 0.30% 79.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 25 0.50% 80.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 14 0.28% 80.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 18 0.36% 81.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.14% 81.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.30% 81.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 16 0.32% 81.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 18 0.36% 82.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 15 0.30% 82.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 8 0.16% 82.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 16 0.32% 82.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 10 0.20% 83.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.02% 83.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1 0.02% 83.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 3 0.06% 83.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 243 4.86% 88.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 480 9.60% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::43 27 0.54% 98.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44 20 0.40% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::45 27 0.54% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46 21 0.42% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 16 0.32% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5001 # Writes before turning the bus around for reads -system.physmem.totQLat 577566851750 # Total ticks spent queuing -system.physmem.totMemAccLat 682115428000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76302460000 # Total ticks spent in databus transfers -system.physmem.totBankLat 28246116250 # Total ticks spent accessing banks -system.physmem.avgQLat 37847.20 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1850.93 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.578158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.392553 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.387042 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 4 0.07% 0.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.03% 0.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 7 0.12% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 4 0.07% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 2 0.03% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 3 0.05% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 4 0.07% 0.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 12 0.20% 0.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2739 45.12% 46.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 35 0.58% 46.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1542 25.40% 72.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1308 21.55% 93.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 93 1.53% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 45 0.74% 95.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 49 0.81% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 58 0.96% 97.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 25 0.41% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 17 0.28% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 20 0.33% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 16 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 13 0.21% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.23% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 14 0.23% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 16 0.26% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 10 0.16% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads +system.physmem.totQLat 393355196000 # Total ticks spent queuing +system.physmem.totMemAccLat 679593221000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76330140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25766.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44698.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44516.70 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.68 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -331,299 +302,308 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.73 # Average read queue length when enqueuing -system.physmem.avgWrQLen 15.38 # Average write queue length when enqueuing -system.physmem.readRowHits 14274135 # Number of row buffer hits during reads -system.physmem.writeRowHits 91331 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.51 # Row buffer hit rate for writes -system.physmem.avgGap 158359.74 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.60 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 54969038 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346130 # Transaction distribution -system.membus.trans_dist::ReadResp 16346133 # Transaction distribution -system.membus.trans_dist::WriteReq 763365 # Transaction distribution -system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59154 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4693 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4694 # Transaction distribution -system.membus.trans_dist::ReadExReq 131434 # Transaction distribution -system.membus.trans_dist::ReadExResp 131434 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution -system.membus.trans_dist::StoreCondReq 3 # Transaction distribution -system.membus.trans_dist::StoreCondResp 3 # Transaction distribution +system.physmem.avgRdQLen 6.51 # Average read queue length when enqueuing +system.physmem.avgWrQLen 15.34 # Average write queue length when enqueuing +system.physmem.readRowHits 14270645 # Number of row buffer hits during reads +system.physmem.writeRowHits 91138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 85.38 # Row buffer hit rate for writes +system.physmem.avgGap 158357.40 # Average gap between requests +system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2202343950500 # Time in different power states +system.physmem.memoryStateTime::REF 85170020000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 263082705750 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 54969203 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346092 # Transaction distribution +system.membus.trans_dist::ReadResp 16346092 # Transaction distribution +system.membus.trans_dist::WriteReq 763361 # Transaction distribution +system.membus.trans_dist::WriteResp 763361 # Transaction distribution +system.membus.trans_dist::Writeback 59148 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4680 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4680 # Transaction distribution +system.membus.trans_dist::ReadExReq 131444 # Transaction distribution +system.membus.trans_dist::ReadExResp 131444 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383060 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272780 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885816 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272670 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550412 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34550302 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390486 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16698004 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19096138 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16695968 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094102 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140206666 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140206666 # Total data (bytes) +system.membus.tot_pkt_size::total 140204630 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140204630 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487459000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486938500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3616000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17565357500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17564463000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4737629056 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4735162713 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37816335199 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37454635709 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64394 # number of replacements -system.l2c.tags.tagsinuse 51423.269942 # Cycle average of tags in use -system.l2c.tags.total_refs 1904392 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129782 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.673776 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2513283956500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36971.606132 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 22.825180 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4577.267389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3052.603978 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.951997 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3614.635006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3176.379887 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.564142 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000348 # Average percentage of cache occupancy +system.l2c.tags.replacements 64370 # number of replacements +system.l2c.tags.tagsinuse 51446.531370 # Cycle average of tags in use +system.l2c.tags.total_refs 1904863 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129760 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.679894 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2513258094500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36996.902854 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 21.266230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4638.850911 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3223.219228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.615555 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3561.358912 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2994.317308 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.564528 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000324 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.069844 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.055155 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.048468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784657 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 21 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65367 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.070783 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.049182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.054342 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045690 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.785012 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65368 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3070 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6838 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55080 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000320 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997421 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18929537 # Number of tag accesses -system.l2c.tags.data_accesses 18929537 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 32378 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6463 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 508619 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 187861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7240 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 462078 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199585 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435592 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608227 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64453.125000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 66750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59382.099596 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61974.555949 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60166.599067 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61748.237856 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61701.909837 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.566614 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.688361 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61669.274080 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61089.105156 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61412.836106 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84241.935484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 171750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59068.588204 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61615.745339 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 63645.833333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59405.033972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61214.590057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61268.145063 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -799,10 +767,6 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency @@ -814,43 +778,40 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58424320 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2676714 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2676716 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608227 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2954 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2966 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246181 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246181 # Transaction distribution -system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution -system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution -system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1967568 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5797861 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 37552 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149979 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7952960 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62924224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85579658 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 54820 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 255152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148813854 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148813854 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 206020 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4963822946 # Layer occupancy (ticks) +system.toL2Bus.throughput 58427348 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677396 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677395 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763361 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763361 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 607907 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2938 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2945 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246147 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246147 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1969203 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5796633 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 38454 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 149595 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7953885 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 62977408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85532246 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 56372 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 254604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 148820630 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148820630 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204356 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4962673723 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4432706696 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4436346984 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4484503287 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4483051170 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23902881 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24406904 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86618127 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86367392 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48419467 # Throughput (bytes/s) +system.iobus.throughput 48420315 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322169 # Transaction distribution system.iobus.trans_dist::ReadResp 16322169 # Transaction distribution system.iobus.trans_dist::WriteReq 8177 # Transaction distribution @@ -960,17 +921,17 @@ system.iobus.reqLayer25.occupancy 15138816000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374883000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 37825687801 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38146923291 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7508483 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5992866 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 375676 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4822577 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3918936 # Number of BTB hits +system.cpu0.branchPred.lookups 7527303 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6005482 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 376664 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4812068 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3910560 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.262279 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 722501 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39246 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.265685 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 724420 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38989 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +955,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25709068 # DTB read hits -system.cpu0.dtb.read_misses 39624 # DTB read misses -system.cpu0.dtb.write_hits 6152335 # DTB write hits -system.cpu0.dtb.write_misses 10221 # DTB write misses +system.cpu0.dtb.read_hits 25762472 # DTB read hits +system.cpu0.dtb.read_misses 39475 # DTB read misses +system.cpu0.dtb.write_hits 6143291 # DTB write hits +system.cpu0.dtb.write_misses 10324 # DTB write misses system.cpu0.dtb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5608 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1406 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 264 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5580 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1376 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 646 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25748692 # DTB read accesses -system.cpu0.dtb.write_accesses 6162556 # DTB write accesses +system.cpu0.dtb.perms_faults 639 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25801947 # DTB read accesses +system.cpu0.dtb.write_accesses 6153615 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31861403 # DTB hits -system.cpu0.dtb.misses 49845 # DTB misses -system.cpu0.dtb.accesses 31911248 # DTB accesses +system.cpu0.dtb.hits 31905763 # DTB hits +system.cpu0.dtb.misses 49799 # DTB misses +system.cpu0.dtb.accesses 31955562 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,687 +995,714 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5876098 # ITB inst hits -system.cpu0.itb.inst_misses 7014 # ITB inst misses +system.cpu0.itb.inst_hits 5893431 # ITB inst hits +system.cpu0.itb.inst_misses 7431 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 514 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 760 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 752 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2644 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2617 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1469 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1506 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5883112 # ITB inst accesses -system.cpu0.itb.hits 5876098 # DTB hits -system.cpu0.itb.misses 7014 # DTB misses -system.cpu0.itb.accesses 5883112 # DTB accesses -system.cpu0.numCycles 242192321 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5900862 # ITB inst accesses +system.cpu0.itb.hits 5893431 # DTB hits +system.cpu0.itb.misses 7431 # DTB misses +system.cpu0.itb.accesses 5900862 # DTB accesses +system.cpu0.numCycles 242264674 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15567613 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45445847 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7508483 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4641437 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10272972 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2435180 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 81106 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 50250706 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1544 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 48114 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1489776 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 378 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5874191 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 367063 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2900 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 79394723 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.721041 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.068559 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15531926 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45587183 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7527303 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4634980 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10285875 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2434733 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89107 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 50171859 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2068 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 54478 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1474048 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5891523 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 366856 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3025 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 79291736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.723314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.072188 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 69128739 87.07% 87.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 676261 0.85% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 870795 1.10% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1169302 1.47% 90.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1115285 1.40% 91.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 553948 0.70% 92.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1287197 1.62% 94.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 378519 0.48% 94.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4214677 5.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 69012854 87.04% 87.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 680232 0.86% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 874808 1.10% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1172230 1.48% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1090891 1.38% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557599 0.70% 92.56% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1295199 1.63% 94.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 379880 0.48% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4228043 5.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79394723 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031002 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.187644 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16658432 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 51288095 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9197431 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 656874 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1591763 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1006093 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91406 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 54494283 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 303520 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1591763 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17551658 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 20345183 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27653568 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 8896202 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3354292 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51932303 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 196 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 500448 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2179621 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 261 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 53595851 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 240832893 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 219678051 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5082 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39195467 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14400384 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 591696 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 540219 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6961736 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10014185 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6974197 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1050889 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1353332 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 48232956 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1025841 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 61971057 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 88766 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9957722 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24611703 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 275811 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 79394723 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.780544 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.499047 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 79291736 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031071 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.188171 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16635366 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 51194908 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9213198 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 653944 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1592125 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1010665 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90813 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 54600074 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 300654 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1592125 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17527482 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 20299787 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27625200 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8910460 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3334547 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 52031373 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 331 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 485563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2176301 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 182 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 53736698 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 241285167 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 220106334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 4864 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39390817 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14345881 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 590593 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 539084 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6947132 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10055649 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6962422 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1056834 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1358453 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 48348288 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1003135 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62086915 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 89013 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9905639 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24691410 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 254686 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 79291736 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.783019 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.501466 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 56910995 71.68% 71.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7345017 9.25% 80.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3503110 4.41% 85.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2918035 3.68% 89.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6157997 7.76% 96.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1482939 1.87% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 783446 0.99% 99.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 227116 0.29% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 66068 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 56790483 71.62% 71.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7331291 9.25% 80.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3517102 4.44% 85.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2900884 3.66% 88.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6182474 7.80% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1488398 1.88% 98.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 785922 0.99% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 230106 0.29% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 65076 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 79394723 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 79291736 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29670 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 1 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4193006 94.32% 94.99% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 222912 5.01% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 31039 0.70% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4198728 94.33% 95.03% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 221343 4.97% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15869 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29065604 46.90% 46.93% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46869 0.08% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.00% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1239 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26385475 42.58% 89.58% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6455974 10.42% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14970 0.02% 0.02% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29137192 46.93% 46.95% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47374 0.08% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1226 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.03% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26440432 42.59% 89.62% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6445693 10.38% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 61971057 # Type of FU issued -system.cpu0.iq.rate 0.255875 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4445589 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.071737 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207909567 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 59225484 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43186225 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11292 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6130 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5133 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66394829 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5948 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 311727 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62086915 # Type of FU issued +system.cpu0.iq.rate 0.256277 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4451111 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.071692 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208044448 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 59266351 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43285904 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 10871 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 5830 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 4924 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66517304 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5752 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 316537 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2130667 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3740 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15655 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 850179 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2144033 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4052 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15721 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 849604 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17067257 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 348827 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17082730 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 349385 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1591763 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15715155 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 239745 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 49373573 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105603 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10014185 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6974197 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 727713 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55741 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4727 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15655 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183161 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144870 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 328031 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 60906320 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26058550 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1064737 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1592125 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15682380 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239912 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 49471978 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105539 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10055649 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6962422 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 704937 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56286 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 4027 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15721 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184221 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 145235 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 329456 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61023718 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26110824 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1063197 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 114776 # number of nop insts executed -system.cpu0.iew.exec_refs 32455686 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5967734 # Number of branches executed -system.cpu0.iew.exec_stores 6397136 # Number of stores executed -system.cpu0.iew.exec_rate 0.251479 # Inst execution rate -system.cpu0.iew.wb_sent 60414213 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43191358 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23287316 # num instructions producing a value -system.cpu0.iew.wb_consumers 42834885 # num instructions consuming a value +system.cpu0.iew.exec_nop 120555 # number of nop insts executed +system.cpu0.iew.exec_refs 32498156 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5982225 # Number of branches executed +system.cpu0.iew.exec_stores 6387332 # Number of stores executed +system.cpu0.iew.exec_rate 0.251889 # Inst execution rate +system.cpu0.iew.wb_sent 60528797 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43290828 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23369621 # num instructions producing a value +system.cpu0.iew.wb_consumers 42956226 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.178335 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.543653 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.178692 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544033 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 9785836 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 750030 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 285660 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 77802960 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.502286 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.465598 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9786876 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 748449 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 287258 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 77699611 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.504830 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472024 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 63388396 81.47% 81.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7400911 9.51% 90.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1988257 2.56% 93.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1098992 1.41% 94.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 865715 1.11% 96.07% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 575312 0.74% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 733525 0.94% 97.75% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 350428 0.45% 98.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1401424 1.80% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 63277588 81.44% 81.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7407512 9.53% 90.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1967451 2.53% 93.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1105852 1.42% 94.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 852897 1.10% 96.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 576328 0.74% 96.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 737114 0.95% 97.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 349768 0.45% 98.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1425101 1.83% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 77802960 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29900744 # Number of instructions committed -system.cpu0.commit.committedOps 39079359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 77699611 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30084753 # Number of instructions committed +system.cpu0.commit.committedOps 39225066 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14007536 # Number of memory references committed -system.cpu0.commit.loads 7883518 # Number of loads committed -system.cpu0.commit.membars 209346 # Number of memory barriers committed -system.cpu0.commit.branches 5162239 # Number of branches committed -system.cpu0.commit.fp_insts 5086 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34792812 # Number of committed integer instructions. -system.cpu0.commit.function_calls 507721 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1401424 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14024434 # Number of memory references committed +system.cpu0.commit.loads 7911616 # Number of loads committed +system.cpu0.commit.membars 209739 # Number of memory barriers committed +system.cpu0.commit.branches 5192960 # Number of branches committed +system.cpu0.commit.fp_insts 4874 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34907078 # Number of committed integer instructions. +system.cpu0.commit.function_calls 509367 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 25154804 64.13% 64.13% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44602 0.11% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.24% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 1226 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.25% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7911616 20.17% 84.42% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 6112818 15.58% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::total 39225066 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1425101 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124291086 # The number of ROB reads -system.cpu0.rob.rob_writes 99365166 # The number of ROB writes -system.cpu0.timesIdled 908697 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 162797598 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2248209209 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 29823122 # Number of Instructions Simulated -system.cpu0.committedOps 39001737 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 29823122 # Number of Instructions Simulated -system.cpu0.cpi 8.120958 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.120958 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.123138 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.123138 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 276680521 # number of integer regfile reads -system.cpu0.int_regfile_writes 43875243 # number of integer regfile writes -system.cpu0.fp_regfile_reads 44965 # number of floating regfile reads -system.cpu0.fp_regfile_writes 42348 # number of floating regfile writes -system.cpu0.misc_regfile_reads 137565982 # number of misc regfile reads -system.cpu0.misc_regfile_writes 581037 # number of misc regfile writes -system.cpu0.icache.tags.replacements 983714 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.569506 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 10510100 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 984226 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.678543 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7060452000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.023627 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 194.545879 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.619187 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.379972 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999159 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 124324951 # The number of ROB reads +system.cpu0.rob.rob_writes 99658992 # The number of ROB writes +system.cpu0.timesIdled 907419 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 162972938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2247980405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30002566 # Number of Instructions Simulated +system.cpu0.committedOps 39142879 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30002566 # Number of Instructions Simulated +system.cpu0.cpi 8.074798 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.074798 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123842 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123842 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 277224657 # number of integer regfile reads +system.cpu0.int_regfile_writes 43993248 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44815 # number of floating regfile reads +system.cpu0.fp_regfile_writes 42286 # number of floating regfile writes +system.cpu0.misc_regfile_reads 137449038 # number of misc regfile reads +system.cpu0.misc_regfile_writes 580454 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984532 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.571226 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10502635 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 985044 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.662097 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7040991250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 317.697202 # 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mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085148 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11994.970857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12113.798603 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11865.395630 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11994.970857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 643844 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.993221 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21529454 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 644356 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.412359 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 43687250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 256.274589 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.718633 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.500536 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499450 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 643424 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.993257 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 21526419 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 643936 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.429439 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 43468250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 254.820066 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.173192 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497695 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502291 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 190 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 101648096 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 101648096 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 7014056 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6760706 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13774762 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3747600 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3513292 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7260892 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116614 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126440 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243054 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119391 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128245 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247636 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10761656 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10273998 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21035654 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10761656 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10273998 # number of overall hits -system.cpu0.dcache.overall_hits::total 21035654 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 333491 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 414863 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 748354 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1635288 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1327358 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2962646 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 7514 # 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number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 89347652079 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 70940705755 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 160288357834 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 89347652079 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 70940705755 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 160288357834 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7347547 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 7175569 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14523116 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5382888 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 4840650 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10223538 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124128 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 132505 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 256633 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 119397 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 128251 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247648 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12730435 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12016219 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24746654 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12730435 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12016219 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24746654 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.045388 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.057816 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051528 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.303794 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.274211 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289787 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060534 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.045772 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052912 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000050 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000047 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.154651 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.144989 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149960 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.154651 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.144989 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149960 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16037.735030 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.526677 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15301.974095 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51366.616636 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 48847.298563 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 50237.883403 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14288.062018 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13380.708326 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13882.796524 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 15083.500000 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 101635836 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101635836 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 7044250 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6727132 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13771382 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3751595 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3509581 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261176 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 116856 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 126271 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243127 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 119516 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 128128 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247644 # 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miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052705 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000017 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000039 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000028 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.153418 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.146328 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.149982 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.153418 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.146328 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.149982 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16007.580986 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14564.877994 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15211.386729 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52038.246168 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 47922.572947 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50174.521862 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14208.327160 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13440.945024 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13860.574333 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14041.750000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 43192.766864 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45382.265901 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 40718.545899 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 43192.766864 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 37128 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 22269 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3473 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 273 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027721 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026585 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025161 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023465 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.054371 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041108 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047523 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000050 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000047 # 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average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47002.959406 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 45387.965893 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46266.328011 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12590.421099 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11563.338351 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12131.703509 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13083.166667 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 607907 # number of writebacks +system.cpu0.dcache.writebacks::total 607907 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 148329 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7736714362 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16709674840 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8972960478 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7736714362 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16709674840 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91614967500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90722197000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182337164500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13706653581 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13072228739 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26778882320 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105321621081 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103794425739 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209116046820 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025366 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027805 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025015 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023619 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053874 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041306 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047391 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000017 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025651 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025218 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026112 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025651 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13866.040583 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13267.208633 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13557.819968 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47451.759954 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44533.839185 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46108.919160 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12477.106812 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11653.137137 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12106.615144 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12041.583333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27779.380328 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25002.202612 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26412.913077 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 27901.690583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24708.543276 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26326.430202 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency -system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7323132 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5902490 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346200 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4511574 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3765481 # Number of BTB hits +system.cpu1.branchPred.lookups 7300035 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5887077 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 345091 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4651296 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3771120 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 83.462690 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 676459 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34463 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.076758 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 673548 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34495 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1738,25 +1726,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25506602 # DTB read hits -system.cpu1.dtb.read_misses 36488 # DTB read misses -system.cpu1.dtb.write_hits 5558527 # DTB write hits -system.cpu1.dtb.write_misses 8439 # DTB write misses +system.cpu1.dtb.read_hits 25450161 # DTB read hits +system.cpu1.dtb.read_misses 36388 # DTB read misses +system.cpu1.dtb.write_hits 5568332 # DTB write hits +system.cpu1.dtb.write_misses 8538 # DTB write misses system.cpu1.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5463 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2276 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5495 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2244 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 247 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 679 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25543090 # DTB read accesses -system.cpu1.dtb.write_accesses 5566966 # DTB write accesses +system.cpu1.dtb.perms_faults 710 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25486549 # DTB read accesses +system.cpu1.dtb.write_accesses 5576870 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31065129 # DTB hits -system.cpu1.dtb.misses 44927 # DTB misses -system.cpu1.dtb.accesses 31110056 # DTB accesses +system.cpu1.dtb.hits 31018493 # DTB hits +system.cpu1.dtb.misses 44926 # DTB misses +system.cpu1.dtb.accesses 31063419 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1778,294 +1766,329 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5703436 # ITB inst hits -system.cpu1.itb.inst_misses 7020 # ITB inst misses +system.cpu1.itb.inst_hits 5679651 # ITB inst hits +system.cpu1.itb.inst_misses 6870 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 679 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 687 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2688 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2692 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1570 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5710456 # ITB inst accesses -system.cpu1.itb.hits 5703436 # DTB hits -system.cpu1.itb.misses 7020 # DTB misses -system.cpu1.itb.accesses 5710456 # DTB accesses -system.cpu1.numCycles 237056909 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5686521 # ITB inst accesses +system.cpu1.itb.hits 5679651 # DTB hits +system.cpu1.itb.misses 6870 # DTB misses +system.cpu1.itb.accesses 5686521 # DTB accesses +system.cpu1.numCycles 236844574 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14419718 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45234990 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7323132 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4441940 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 9947853 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2287798 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84999 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 49482147 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1272 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1896 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 44871 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1235484 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 189 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5701379 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 352457 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3064 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76794959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.726229 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.078871 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14466322 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45074741 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7300035 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4444668 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9928510 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2284755 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 83810 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 49428019 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1865 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 44064 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1232877 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 132 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5677454 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 353029 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3058 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76760101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.724873 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.076516 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66855647 87.06% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 632615 0.82% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 843009 1.10% 88.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1133482 1.48% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1002056 1.30% 91.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 554704 0.72% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1272745 1.66% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 372184 0.48% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4128517 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66839787 87.08% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 628644 0.82% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 837705 1.09% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1128430 1.47% 90.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1025116 1.34% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 549692 0.72% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1265677 1.65% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 371391 0.48% 94.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4113659 5.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76794959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030892 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.190819 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15530724 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50222847 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8895356 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 650267 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1493551 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 963840 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85500 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53154493 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286161 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1493551 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16374919 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19306160 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27715779 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8656578 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3245827 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 50687701 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 339 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 605911 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2002092 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 648 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53113804 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234485879 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 214384735 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5365 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39540919 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13572884 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 579809 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 536931 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6499660 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9772559 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6360216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 888468 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1099515 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47171321 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 962588 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61070577 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91971 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9248404 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 23463374 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 229936 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76794959 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.795242 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.505673 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76760101 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030822 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.190314 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15575790 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 50164874 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8875530 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 651724 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1490012 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 958602 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85804 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53028773 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286820 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1490012 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16419373 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19259514 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27698423 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8639214 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3251470 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 50560580 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 221 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 607469 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2007282 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 572 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 52946210 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 233908561 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 213841042 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5698 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39345682 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13600527 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 580708 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 537933 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6505084 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9729570 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6369599 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 877361 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1114434 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47034811 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 984793 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60942495 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 91566 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9279731 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 23349761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 250555 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76760101 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793935 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.504235 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54534134 71.01% 71.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 7328500 9.54% 80.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3483988 4.54% 85.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2874889 3.74% 88.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6131286 7.98% 96.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1377966 1.79% 98.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 776904 1.01% 99.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 225300 0.29% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61992 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54532875 71.04% 71.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7326090 9.54% 80.59% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3469207 4.52% 85.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2884980 3.76% 88.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6118042 7.97% 96.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1370862 1.79% 98.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 772587 1.01% 99.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 222613 0.29% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62845 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76794959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76760101 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29712 0.67% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4180230 94.88% 95.56% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 195658 4.44% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29035 0.66% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 5 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4177111 94.84% 95.50% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 198082 4.50% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12649 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28971083 47.44% 47.46% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46630 0.08% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 875 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26162080 42.84% 90.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5877234 9.62% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13548 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28887832 47.40% 47.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46127 0.08% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 887 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.50% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26105748 42.84% 90.34% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5888317 9.66% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61070577 # Type of FU issued -system.cpu1.iq.rate 0.257620 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4405603 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072140 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203466895 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57390461 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42382296 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11528 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6422 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5160 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65457468 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6063 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 311906 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60942495 # Type of FU issued +system.cpu1.iq.rate 0.257310 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4404233 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072269 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203173539 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57307144 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42269826 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12116 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6726 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5381 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65326800 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6380 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 306796 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1999074 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3048 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 15122 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 750838 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1984154 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3003 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 15089 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 749009 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17042744 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 332080 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17027364 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 331342 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1493551 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14864582 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 222698 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48241525 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96453 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9772559 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6360216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 687199 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 48610 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 15122 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 168053 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 134565 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 302618 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60042253 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25845364 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1028324 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1490012 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14823463 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 222107 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48121220 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 96425 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9729570 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6369599 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 709638 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 48371 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 4239 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 15089 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 167591 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133565 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301156 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59912848 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25789830 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1029647 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 107616 # number of nop insts executed -system.cpu1.iew.exec_refs 31671376 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5872062 # Number of branches executed -system.cpu1.iew.exec_stores 5826012 # Number of stores executed -system.cpu1.iew.exec_rate 0.253282 # Inst execution rate -system.cpu1.iew.wb_sent 59578158 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42387456 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23643387 # num instructions producing a value -system.cpu1.iew.wb_consumers 43005248 # num instructions consuming a value +system.cpu1.iew.exec_nop 101616 # number of nop insts executed +system.cpu1.iew.exec_refs 31626536 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5854246 # Number of branches executed +system.cpu1.iew.exec_stores 5836706 # Number of stores executed +system.cpu1.iew.exec_rate 0.252963 # Inst execution rate +system.cpu1.iew.wb_sent 59450905 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42275207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23556720 # num instructions producing a value +system.cpu1.iew.wb_consumers 42880647 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178807 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.549779 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178493 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.549356 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9166908 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 732652 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 262014 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 75301408 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513681 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.486972 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9147109 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 734238 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260548 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 75270089 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.511960 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.483838 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60995111 81.00% 81.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 7470337 9.92% 90.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1928698 2.56% 93.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1074141 1.43% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 820415 1.09% 96.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 494186 0.66% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 699344 0.93% 97.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 371316 0.49% 98.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1447860 1.92% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 60996835 81.04% 81.04% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7463530 9.92% 90.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1923766 2.56% 93.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1066165 1.42% 94.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 822611 1.09% 96.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 493470 0.66% 96.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 696092 0.92% 97.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 369554 0.49% 98.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1438066 1.91% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 75301408 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 30565527 # Number of instructions committed -system.cpu1.commit.committedOps 38680902 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 75270089 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 30381625 # Number of instructions committed +system.cpu1.commit.committedOps 38535309 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13382863 # Number of memory references committed -system.cpu1.commit.loads 7773485 # Number of loads committed -system.cpu1.commit.membars 194338 # Number of memory barriers committed -system.cpu1.commit.branches 5145142 # Number of branches committed -system.cpu1.commit.fp_insts 5126 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34406663 # Number of committed integer instructions. -system.cpu1.commit.function_calls 483721 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1447860 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13366006 # Number of memory references committed +system.cpu1.commit.loads 7745416 # Number of loads committed +system.cpu1.commit.membars 193947 # Number of memory barriers committed +system.cpu1.commit.branches 5114433 # Number of branches committed +system.cpu1.commit.fp_insts 5338 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 34292499 # Number of committed integer instructions. +system.cpu1.commit.function_calls 482077 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 25125071 65.20% 65.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43345 0.11% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 887 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.31% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 7745416 20.10% 85.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 5620590 14.59% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::total 38535309 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1438066 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120827478 # The number of ROB reads -system.cpu1.rob.rob_writes 97232532 # The number of ROB writes -system.cpu1.timesIdled 865086 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 160261950 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2316983227 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 30492768 # Number of Instructions Simulated -system.cpu1.committedOps 38608143 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 30492768 # Number of Instructions Simulated -system.cpu1.cpi 7.774201 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.774201 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.128631 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.128631 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 272500909 # number of integer regfile reads -system.cpu1.int_regfile_writes 43779735 # number of integer regfile writes -system.cpu1.fp_regfile_reads 45015 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42294 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133085319 # number of misc regfile reads -system.cpu1.misc_regfile_writes 592959 # number of misc regfile writes +system.cpu1.rob.rob_reads 120626402 # The number of ROB reads +system.cpu1.rob.rob_writes 96898257 # The number of ROB writes +system.cpu1.timesIdled 866184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 160084473 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2317121408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 30313431 # Number of Instructions Simulated +system.cpu1.committedOps 38467115 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 30313431 # Number of Instructions Simulated +system.cpu1.cpi 7.813189 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.813189 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.127989 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.127989 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 271901021 # number of integer regfile reads +system.cpu1.int_regfile_writes 43646883 # number of integer regfile writes +system.cpu1.fp_regfile_reads 45279 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42402 # number of floating regfile writes +system.cpu1.misc_regfile_reads 133121444 # number of misc regfile reads +system.cpu1.misc_regfile_writes 593543 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2082,17 +2105,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736889440801 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736889440801 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736889440801 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1734475259291 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1734475259291 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1734475259291 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83061 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83062 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 094868576..cce768d16 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,147 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.629695 # Number of seconds simulated -sim_ticks 2629694709500 # Number of ticks simulated -final_tick 2629694709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.631271 # Number of seconds simulated +sim_ticks 2631271319500 # Number of ticks simulated +final_tick 2631271319500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 422902 # Simulator instruction rate (inst/s) -host_op_rate 538135 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18468797106 # Simulator tick rate (ticks/s) -host_mem_usage 466428 # Number of bytes of host memory used -host_seconds 142.39 # Real time elapsed on the host -sim_insts 60215255 # Number of instructions simulated -sim_ops 76622777 # Number of ops (including micro ops) simulated +host_inst_rate 354699 # Simulator instruction rate (inst/s) +host_op_rate 451347 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15499898557 # Simulator tick rate (ticks/s) +host_mem_usage 465856 # Number of bytes of host memory used +host_seconds 169.76 # Real time elapsed on the host +sim_insts 60213853 # Number of instructions simulated +sim_ops 76620850 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 291720 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4684888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 299528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4518680 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 412356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4375828 # Number of bytes read from this memory -system.physmem.bytes_read::total 134021240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 291720 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 412356 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704076 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3689664 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1522876 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1493404 # Number of bytes written to this memory -system.physmem.bytes_written::total 6705944 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 404800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4542464 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 299528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704328 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690624 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1524152 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1491920 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706696 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10770 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10892 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 70640 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6459 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 68407 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57651 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380719 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 373351 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811721 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47251210 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70976 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690868 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57666 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 381038 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 372980 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811684 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47222898 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 110933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1781533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 113834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1717299 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 156808 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1664006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50964562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 110933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 156808 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267741 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1403077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 579108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 567900 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2550085 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1403077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47251210 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 153842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1726338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50934284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 113834 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 153842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267676 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402601 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 579245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 566996 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2548842 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47222898 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 110933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2360641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 113834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2296545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 156808 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2231906 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53514647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690908 # Number of read requests accepted -system.physmem.writeReqs 811721 # Number of write requests accepted -system.physmem.readBursts 15690908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811721 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004216192 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1920 # Total number of bytes read from write queue -system.physmem.bytesWritten 6737024 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134021240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6705944 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 30 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706455 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::cpu1.inst 153842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2293334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53483126 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690868 # Number of read requests accepted +system.physmem.writeReqs 811684 # Number of write requests accepted +system.physmem.readBursts 15690868 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811684 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004214848 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 704 # Total number of bytes read from write queue +system.physmem.bytesWritten 6724608 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134021920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6706696 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 11 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706598 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4517 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980391 # Per bank write bursts system.physmem.perBankRdBursts::1 980206 # Per bank write bursts -system.physmem.perBankRdBursts::2 980218 # Per bank write bursts -system.physmem.perBankRdBursts::3 980431 # Per bank write bursts +system.physmem.perBankRdBursts::2 980222 # Per bank write bursts +system.physmem.perBankRdBursts::3 980428 # Per bank write bursts system.physmem.perBankRdBursts::4 986950 # Per bank write bursts system.physmem.perBankRdBursts::5 980708 # Per bank write bursts -system.physmem.perBankRdBursts::6 980610 # Per bank write bursts -system.physmem.perBankRdBursts::7 980421 # Per bank write bursts +system.physmem.perBankRdBursts::6 980611 # Per bank write bursts +system.physmem.perBankRdBursts::7 980420 # Per bank write bursts system.physmem.perBankRdBursts::8 980615 # Per bank write bursts system.physmem.perBankRdBursts::9 980431 # Per bank write bursts system.physmem.perBankRdBursts::10 979815 # Per bank write bursts -system.physmem.perBankRdBursts::11 979558 # Per bank write bursts -system.physmem.perBankRdBursts::12 980154 # Per bank write bursts -system.physmem.perBankRdBursts::13 980093 # Per bank write bursts -system.physmem.perBankRdBursts::14 980167 # Per bank write bursts +system.physmem.perBankRdBursts::11 979544 # Per bank write bursts +system.physmem.perBankRdBursts::12 980153 # Per bank write bursts +system.physmem.perBankRdBursts::13 980076 # Per bank write bursts +system.physmem.perBankRdBursts::14 980177 # Per bank write bursts system.physmem.perBankRdBursts::15 980110 # Per bank write bursts -system.physmem.perBankWrBursts::0 6645 # Per bank write bursts -system.physmem.perBankWrBursts::1 6506 # Per bank write bursts -system.physmem.perBankWrBursts::2 6513 # Per bank write bursts -system.physmem.perBankWrBursts::3 6561 # Per bank write bursts -system.physmem.perBankWrBursts::4 6643 # Per bank write bursts -system.physmem.perBankWrBursts::5 6949 # Per bank write bursts -system.physmem.perBankWrBursts::6 6933 # Per bank write bursts -system.physmem.perBankWrBursts::7 6786 # Per bank write bursts -system.physmem.perBankWrBursts::8 6904 # Per bank write bursts -system.physmem.perBankWrBursts::9 6725 # Per bank write bursts -system.physmem.perBankWrBursts::10 6221 # Per bank write bursts -system.physmem.perBankWrBursts::11 6029 # Per bank write bursts -system.physmem.perBankWrBursts::12 6513 # Per bank write bursts -system.physmem.perBankWrBursts::13 6297 # Per bank write bursts +system.physmem.perBankWrBursts::0 6626 # Per bank write bursts +system.physmem.perBankWrBursts::1 6496 # Per bank write bursts +system.physmem.perBankWrBursts::2 6497 # Per bank write bursts +system.physmem.perBankWrBursts::3 6558 # Per bank write bursts +system.physmem.perBankWrBursts::4 6634 # Per bank write bursts +system.physmem.perBankWrBursts::5 6937 # Per bank write bursts +system.physmem.perBankWrBursts::6 6920 # Per bank write bursts +system.physmem.perBankWrBursts::7 6772 # Per bank write bursts +system.physmem.perBankWrBursts::8 6893 # Per bank write bursts +system.physmem.perBankWrBursts::9 6718 # Per bank write bursts +system.physmem.perBankWrBursts::10 6212 # Per bank write bursts +system.physmem.perBankWrBursts::11 6014 # Per bank write bursts +system.physmem.perBankWrBursts::12 6499 # Per bank write bursts +system.physmem.perBankWrBursts::13 6274 # Per bank write bursts system.physmem.perBankWrBursts::14 6516 # Per bank write bursts -system.physmem.perBankWrBursts::15 6525 # Per bank write bursts +system.physmem.perBankWrBursts::15 6506 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2629690290000 # Total gap between requests +system.physmem.totGap 2631266900000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 6718 # Read request sizes (log2) +system.physmem.readPktSize::2 6664 # Read request sizes (log2) system.physmem.readPktSize::3 15532032 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152158 # Read request sizes (log2) +system.physmem.readPktSize::6 152172 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 754070 # Write request sizes (log2) +system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57651 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1128915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 971082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 971066 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 973046 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 971647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 972454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2865167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2865325 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3808659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25323 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 23577 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 23920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 23318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 22983 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 22230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 22150 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57666 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139961 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1093203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1062031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2774379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2684271 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3510460 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 111897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 101929 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 96137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 92760 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -157,60 +169,60 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 342 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 339 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 318 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1166 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5848 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5837 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see @@ -221,373 +233,350 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 990183 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 1014.719065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1002.794597 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 86.877825 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3622 0.37% 0.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 3291 0.33% 0.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1715 0.17% 0.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1178 0.12% 0.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 920 0.09% 1.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 703 0.07% 1.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 532 0.05% 1.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 420 0.04% 1.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 977802 98.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 990183 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4537 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3458.425832 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 54557.622307 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 4511 99.43% 99.43% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 8 0.18% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 4 0.09% 99.69% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::393216-458751 2 0.04% 99.74% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 3 0.07% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.82% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.13% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040545 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.548041 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.383017 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.411888 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22983 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22832 2.19% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9281 0.89% 5.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2277 0.22% 5.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2320 0.22% 5.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1623 0.16% 5.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9470 0.91% 6.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 703 0.07% 6.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969056 93.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040545 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2612.962531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47489.703553 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5977 99.53% 99.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 11 0.18% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.77% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.80% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::589824-655359 3 0.05% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4537 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4537 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.201675 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.361663 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 9.873768 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 5 0.11% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 7 0.15% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 5 0.11% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 2 0.04% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 2 0.04% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 4 0.09% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 6 0.13% 0.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.07% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 3 0.07% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.07% 0.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.07% 0.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 2 0.04% 0.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 4 0.09% 1.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 7 0.15% 1.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 17 0.37% 1.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 1491 32.86% 34.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 339 7.47% 41.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 208 4.58% 46.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1050 23.14% 69.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 16 0.35% 70.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 12 0.26% 70.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.44% 70.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 24 0.53% 71.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 18 0.40% 71.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 14 0.31% 71.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 18 0.40% 72.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 18 0.40% 72.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 19 0.42% 73.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 13 0.29% 73.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 11 0.24% 73.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 12 0.26% 73.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.24% 74.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.07% 74.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 2 0.04% 74.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 1 0.02% 74.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::39 1015 22.37% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40 76 1.68% 98.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::41 13 0.29% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42 42 0.93% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::47 1 0.02% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::49 5 0.11% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50 5 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::51 5 0.11% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::53 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4537 # Writes before turning the bus around for reads -system.physmem.totQLat 592300556750 # Total ticks spent queuing -system.physmem.totMemAccLat 700300341750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78454390000 # Total ticks spent in databus transfers -system.physmem.totBankLat 29545395000 # Total ticks spent accessing banks -system.physmem.avgQLat 37748.08 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1882.97 # Average bank access latency per DRAM burst +system.physmem.rdPerTurnAround::total 6005 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.497419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.315574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.169730 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 7 0.12% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 6 0.10% 0.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 6 0.10% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 3 0.05% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 3 0.05% 0.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 4 0.07% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 4 0.07% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 8 0.13% 0.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.05% 0.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 4 0.07% 0.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 16 0.27% 1.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1890 31.47% 32.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 59 0.98% 33.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3765 62.70% 96.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 21 0.35% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 14 0.23% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 16 0.27% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.32% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.33% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 12 0.20% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.10% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 23 0.38% 98.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 21 0.35% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 18 0.30% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 14 0.23% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 10 0.17% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 11 0.18% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6005 # Writes before turning the bus around for reads +system.physmem.totQLat 402822623250 # Total ticks spent queuing +system.physmem.totMemAccLat 697026192000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78454285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25672.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44631.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 381.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44422.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 381.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.96 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.93 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.89 # Average write queue length when enqueuing -system.physmem.readRowHits 14676487 # Number of row buffer hits during reads -system.physmem.writeRowHits 89750 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.26 # Row buffer hit rate for writes -system.physmem.avgGap 159349.78 # Average gap between requests -system.physmem.pageHitRate 93.48 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 4.16 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54426652 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743677 # Transaction distribution -system.membus.trans_dist::ReadResp 16743677 # Transaction distribution -system.membus.trans_dist::WriteReq 763441 # Transaction distribution -system.membus.trans_dist::WriteResp 763441 # Transaction distribution -system.membus.trans_dist::Writeback 57651 # Transaction distribution +system.physmem.avgRdQLen 6.85 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.68 # Average write queue length when enqueuing +system.physmem.readRowHits 14667283 # Number of row buffer hits during reads +system.physmem.writeRowHits 88101 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 83.84 # Row buffer hit rate for writes +system.physmem.avgGap 159446.06 # Average gap between requests +system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2257272287500 # Time in different power states +system.physmem.memoryStateTime::REF 87863880000 # Time in different power states +system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem.memoryStateTime::ACT 286133845000 # Time in different power states +system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states +system.membus.throughput 54394584 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743630 # Transaction distribution +system.membus.trans_dist::ReadResp 16743630 # Transaction distribution +system.membus.trans_dist::WriteReq 763389 # Transaction distribution +system.membus.trans_dist::WriteResp 763389 # Transaction distribution +system.membus.trans_dist::Writeback 57666 # Transaction distribution system.membus.trans_dist::UpgradeReq 4517 # Transaction distribution system.membus.trans_dist::UpgradeResp 4517 # Transaction distribution -system.membus.trans_dist::ReadExReq 131342 # Transaction distribution -system.membus.trans_dist::ReadExResp 131342 # Transaction distribution +system.membus.trans_dist::ReadExReq 131349 # Transaction distribution +system.membus.trans_dist::ReadExResp 131349 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383092 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892577 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279541 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892408 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279372 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343605 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35343436 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390550 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16470928 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18869222 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16472360 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870654 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143125478 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143125478 # Total data (bytes) +system.membus.tot_pkt_size::total 143126910 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126910 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225762000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1225776000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3755500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3753500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171181500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171055500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987933108 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4987830629 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38819144750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38455776750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 62041 # number of replacements -system.l2c.tags.tagsinuse 51600.507824 # Cycle average of tags in use -system.l2c.tags.total_refs 1699332 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127423 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.336148 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574803290500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38204.625202 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000702 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2677.995545 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3048.557344 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4342.999627 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3326.329216 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.582956 # Average percentage of cache occupancy +system.l2c.tags.replacements 62060 # number of replacements +system.l2c.tags.tagsinuse 51620.522057 # Cycle average of tags in use +system.l2c.tags.total_refs 1699511 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127448 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.334937 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2576403565500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38224.293292 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2572.111888 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3079.413643 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4449.101058 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3295.601290 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583256 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.040863 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.046517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.039247 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.046988 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.066269 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.050756 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.787361 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65382 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6447 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56751 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997650 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277037 # Number of tag accesses -system.l2c.tags.data_accesses 17277037 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9996 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3617 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 411271 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 183421 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9883 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 433200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 187065 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1241955 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596489 # number of Writeback hits -system.l2c.Writeback_hits::total 596489 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.067888 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.050287 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787667 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65388 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2135 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6611 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56587 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997742 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17278044 # Number of tag accesses +system.l2c.tags.data_accesses 17278044 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 10108 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3664 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 418356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 187332 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9807 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3568 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 426125 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 183124 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242084 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596476 # number of Writeback hits +system.l2c.Writeback_hits::total 596476 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 55903 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58636 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114539 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9996 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 411271 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9883 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 433200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 245701 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356494 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9996 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3617 # number of overall hits -system.l2c.overall_hits::cpu0.inst 411271 # number of overall hits -system.l2c.overall_hits::cpu0.data 239324 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9883 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3502 # number of overall hits -system.l2c.overall_hits::cpu1.inst 433200 # number of overall hits -system.l2c.overall_hits::cpu1.data 245701 # number of overall hits -system.l2c.overall_hits::total 1356494 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57771 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56762 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114533 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 10108 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3664 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 418356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 245103 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 9807 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3568 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 426125 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 239886 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356617 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 10108 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3664 # number of overall hits +system.l2c.overall_hits::cpu0.inst 418356 # number of overall hits +system.l2c.overall_hits::cpu0.data 245103 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 9807 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3568 # number of overall hits +system.l2c.overall_hits::cpu1.inst 426125 # number of overall hits +system.l2c.overall_hits::cpu1.data 239886 # number of overall hits +system.l2c.overall_hits::total 1356617 # number of overall hits system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4144 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5204 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 4266 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5262 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6442 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5023 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20816 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1406 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1477 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2883 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 68791 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 64185 # 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -729,7 +715,6 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate @@ -739,39 +724,39 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52790847 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471761 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471761 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 763441 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 763441 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596489 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2909 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2909 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247515 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725013 # 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Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138654986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138654986 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 168824 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808734000 # Layer occupancy (ticks) +system.toL2Bus.throughput 52759012 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471877 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471877 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596476 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2915 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2915 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725028 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753762 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20291 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50582 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549663 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54751132 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83793442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 138653174 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138653174 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170100 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808682000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3865148750 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865303000 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420266392 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420412121 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12925000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13057000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30634250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30666250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48160270 # Throughput (bytes/s) +system.iobus.throughput 48131413 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16715394 # Transaction distribution system.iobus.trans_dist::ReadResp 16715394 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution @@ -881,7 +866,7 @@ system.iobus.reqLayer25.occupancy 15532032000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374908000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38823243250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39139813250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -906,25 +891,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7344844 # DTB read hits -system.cpu0.dtb.read_misses 6860 # DTB read misses -system.cpu0.dtb.write_hits 5551128 # DTB write hits -system.cpu0.dtb.write_misses 1832 # DTB write misses -system.cpu0.dtb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7447963 # DTB read hits +system.cpu0.dtb.read_misses 7119 # DTB read misses +system.cpu0.dtb.write_hits 5549645 # DTB write hits +system.cpu0.dtb.write_misses 1815 # DTB write misses +system.cpu0.dtb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6351 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6552 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 137 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 220 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7351704 # DTB read accesses -system.cpu0.dtb.write_accesses 5552960 # DTB write accesses +system.cpu0.dtb.perms_faults 230 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7455082 # DTB read accesses +system.cpu0.dtb.write_accesses 5551460 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12895972 # DTB hits -system.cpu0.dtb.misses 8692 # DTB misses -system.cpu0.dtb.accesses 12904664 # DTB accesses +system.cpu0.dtb.hits 12997608 # DTB hits +system.cpu0.dtb.misses 8934 # DTB misses +system.cpu0.dtb.accesses 13006542 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -946,125 +931,160 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30211154 # ITB inst hits -system.cpu0.itb.inst_misses 3603 # ITB inst misses +system.cpu0.itb.inst_hits 30500446 # ITB inst hits +system.cpu0.itb.inst_misses 3756 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2493 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2495 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 699 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2758 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 725 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 29 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2854 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30214757 # ITB inst accesses -system.cpu0.itb.hits 30211154 # DTB hits -system.cpu0.itb.misses 3603 # DTB misses -system.cpu0.itb.accesses 30214757 # DTB accesses -system.cpu0.numCycles 2627736532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30504202 # ITB inst accesses +system.cpu0.itb.hits 30500446 # DTB hits +system.cpu0.itb.misses 3756 # DTB misses +system.cpu0.itb.accesses 30504202 # DTB accesses +system.cpu0.numCycles 2629256644 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29624937 # Number of instructions committed -system.cpu0.committedOps 37728426 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 34074958 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4583 # Number of float alu accesses -system.cpu0.num_func_calls 1045164 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3935196 # number of instructions that are conditional controls -system.cpu0.num_int_insts 34074958 # number of integer instructions -system.cpu0.num_fp_insts 4583 # number of float instructions -system.cpu0.num_int_register_reads 197582111 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36713164 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3288 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_mem_refs 13470170 # number of memory refs -system.cpu0.num_load_insts 7667939 # Number of load instructions -system.cpu0.num_store_insts 5802231 # Number of store instructions -system.cpu0.num_idle_cycles 2282002616.045546 # Number of idle cycles -system.cpu0.num_busy_cycles 345733915.954454 # Number of busy cycles -system.cpu0.not_idle_fraction 0.131571 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.868429 # Percentage of idle cycles -system.cpu0.Branches 5074688 # Number of branches fetched +system.cpu0.committedInsts 29876886 # Number of instructions committed +system.cpu0.committedOps 37981807 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34283991 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4842 # Number of float alu accesses +system.cpu0.num_func_calls 1058651 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3976280 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34283991 # number of integer instructions +system.cpu0.num_fp_insts 4842 # number of float instructions +system.cpu0.num_int_register_reads 198984803 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36984019 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3491 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1354 # number of times the floating registers were written +system.cpu0.num_mem_refs 13572889 # number of memory refs +system.cpu0.num_load_insts 7771976 # Number of load instructions +system.cpu0.num_store_insts 5800913 # Number of store instructions +system.cpu0.num_idle_cycles 2280913483.245505 # Number of idle cycles +system.cpu0.num_busy_cycles 348343160.754495 # Number of busy cycles +system.cpu0.not_idle_fraction 0.132487 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.867513 # Percentage of idle cycles +system.cpu0.Branches 5129174 # Number of branches fetched +system.cpu0.op_class::No_OpClass 12846 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 24984996 64.70% 64.73% # Class of executed instruction +system.cpu0.op_class::IntMult 44336 0.11% 64.85% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 930 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.85% # Class of executed instruction +system.cpu0.op_class::MemRead 7771976 20.13% 84.98% # Class of executed instruction +system.cpu0.op_class::MemWrite 5800913 15.02% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 38615997 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83029 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856147 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.849495 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60652706 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856659 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.801458 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 20216402250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 158.742483 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 352.107012 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.310044 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.687709 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997753 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856182 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.863139 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60651276 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856694 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.796896 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 20196898250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.776297 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.086842 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.304251 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.693529 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997780 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62366026 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62366026 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29795008 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30857698 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60652706 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29795008 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30857698 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60652706 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29795008 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30857698 # number of overall hits -system.cpu0.icache.overall_hits::total 60652706 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 416146 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 440514 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 856660 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 416146 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 440514 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 856660 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 416146 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 440514 # number of overall misses -system.cpu0.icache.overall_misses::total 856660 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5672028500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6130116250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11802144750 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5672028500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6130116250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11802144750 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5672028500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6130116250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11802144750 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30211154 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 31298212 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 61509366 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30211154 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 31298212 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 61509366 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30211154 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 31298212 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 61509366 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013775 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014075 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013927 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013775 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014075 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013927 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013775 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014075 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013927 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13629.900323 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13915.826171 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.929879 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13629.900323 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13915.826171 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13776.929879 # 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Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97784979 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6545596 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6653610 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13199206 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4917377 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 5057557 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974934 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 119123 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117066 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236189 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 125242 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 122515 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247757 # 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number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 311895 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 307646 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619541 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2396807750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2338699250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4735507000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5342161454 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5370757779 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10712919233 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70030750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67311250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137342000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7738969204 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7709457029 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15448426233 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7738969204 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7709457029 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15448426233 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 90834275250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 91243928750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182078204000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13255943399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12983118997 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239062396 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104090218649 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 104227047747 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208317266396 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027699 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026717 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027204 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024872 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024120 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048873 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044468 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046695 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026433 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025657 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026488 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12898.315945 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12791.659072 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12844.417008 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43959.059248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42334.668852 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43152.714927 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.127695 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12303.165584 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11854.047866 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25587.270854 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24605.859777 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25094.866435 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12853.376896 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12804.757094 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12829.319238 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42593.495990 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42965.031071 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42778.952712 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11441.063552 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12355.222100 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11871.553289 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24812.738915 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25059.506800 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24935.276653 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1348,25 +1364,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7655819 # DTB read hits -system.cpu1.dtb.read_misses 7243 # DTB read misses -system.cpu1.dtb.write_hits 5681899 # DTB write hits -system.cpu1.dtb.write_misses 1828 # DTB write misses +system.cpu1.dtb.read_hits 7552227 # DTB read hits +system.cpu1.dtb.read_misses 6971 # DTB read misses +system.cpu1.dtb.write_hits 5683121 # DTB write hits +system.cpu1.dtb.write_misses 1859 # DTB write misses system.cpu1.dtb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6603 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 232 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7663062 # DTB read accesses -system.cpu1.dtb.write_accesses 5683727 # DTB write accesses +system.cpu1.dtb.perms_faults 222 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7559198 # DTB read accesses +system.cpu1.dtb.write_accesses 5684980 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13337718 # DTB hits -system.cpu1.dtb.misses 9071 # DTB misses -system.cpu1.dtb.accesses 13346789 # DTB accesses +system.cpu1.dtb.hits 13235348 # DTB hits +system.cpu1.dtb.misses 8830 # DTB misses +system.cpu1.dtb.accesses 13244178 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1388,50 +1404,85 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 31298229 # ITB inst hits -system.cpu1.itb.inst_misses 3696 # ITB inst misses +system.cpu1.itb.inst_hits 31007524 # ITB inst hits +system.cpu1.itb.inst_misses 3606 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 2493 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 740 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2898 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 714 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 34 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2820 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31301925 # ITB inst accesses -system.cpu1.itb.hits 31298229 # DTB hits -system.cpu1.itb.misses 3696 # DTB misses -system.cpu1.itb.accesses 31301925 # DTB accesses -system.cpu1.numCycles 2631652887 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31011130 # ITB inst accesses +system.cpu1.itb.hits 31007524 # DTB hits +system.cpu1.itb.misses 3606 # DTB misses +system.cpu1.itb.accesses 31011130 # DTB accesses +system.cpu1.numCycles 2633285995 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30590318 # Number of instructions committed -system.cpu1.committedOps 38894351 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35148183 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5686 # Number of float alu accesses -system.cpu1.num_func_calls 1095318 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4014750 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35148183 # number of integer instructions -system.cpu1.num_fp_insts 5686 # number of float instructions -system.cpu1.num_int_register_reads 203876321 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37823170 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4205 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1482 # number of times the floating registers were written -system.cpu1.num_mem_refs 13931138 # number of memory refs -system.cpu1.num_load_insts 7996929 # Number of load instructions -system.cpu1.num_store_insts 5934209 # Number of store instructions -system.cpu1.num_idle_cycles 2293790821.520695 # Number of idle cycles -system.cpu1.num_busy_cycles 337862065.479305 # Number of busy cycles -system.cpu1.not_idle_fraction 0.128384 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.871616 # Percentage of idle cycles -system.cpu1.Branches 5235663 # Number of branches fetched +system.cpu1.committedInsts 30336967 # Number of instructions committed +system.cpu1.committedOps 38639043 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34937438 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5427 # Number of float alu accesses +system.cpu1.num_func_calls 1081754 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3973481 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34937438 # number of integer instructions +system.cpu1.num_fp_insts 5427 # number of float instructions +system.cpu1.num_int_register_reads 202463130 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37550545 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4002 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1426 # number of times the floating registers were written +system.cpu1.num_mem_refs 13827657 # number of memory refs +system.cpu1.num_load_insts 7892397 # Number of load instructions +system.cpu1.num_store_insts 5935260 # Number of store instructions +system.cpu1.num_idle_cycles 2291893093.755996 # Number of idle cycles +system.cpu1.num_busy_cycles 341392901.244004 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129645 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870355 # Percentage of idle cycles +system.cpu1.Branches 5180924 # Number of branches fetched +system.cpu1.op_class::No_OpClass 15672 0.04% 0.04% # Class of executed instruction +system.cpu1.op_class::IntAlu 25411566 64.66% 64.70% # Class of executed instruction +system.cpu1.op_class::IntMult 43588 0.11% 64.81% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1181 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.81% # Class of executed instruction +system.cpu1.op_class::MemRead 7892397 20.08% 84.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 5935260 15.10% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 39299664 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1450,10 +1501,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1783080197250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1783080197250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1783080197250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1779915025250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779915025250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1779915025250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |