diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-04-22 13:20:33 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-04-22 13:20:33 -0400 |
| commit | d69f904a18593f75efcb0555b2bd092574181160 (patch) | |
| tree | 0afd4c3ec943f0166c70bf7b62215f404465da2f /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | 33ab8f735d0979ef68d7202d3adbf28f1ae2aceb (diff) | |
| download | gem5-d69f904a18593f75efcb0555b2bd092574181160.tar.xz | |
stats: Update stats for O3 switching fix.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
12 files changed, 5833 insertions, 5836 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 94883ba6e..4ca026c3a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -131,6 +133,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -194,6 +197,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu.checker.tracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 8654e0694..0b387654e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533112 # Number of seconds simulated -sim_ticks 2533112171000 # Number of ticks simulated -final_tick 2533112171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533116 # Number of seconds simulated +sim_ticks 2533115780500 # Number of ticks simulated +final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67901 # Simulator instruction rate (inst/s) -host_op_rate 87370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2852051940 # Simulator tick rate (ticks/s) -host_mem_usage 401172 # Number of bytes of host memory used -host_seconds 888.17 # Real time elapsed on the host +host_inst_rate 55678 # Simulator instruction rate (inst/s) +host_op_rate 71642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2338649550 # Simulator tick rate (ticks/s) +host_mem_usage 398880 # Number of bytes of host memory used +host_seconds 1083.15 # Real time elapsed on the host sim_insts 60307726 # Number of instructions simulated sim_ops 77599286 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093456 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory +system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096804 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47190040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1011 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190659 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47190040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096804 # Total number of read requests seen -system.physmem.writeReqs 813112 # Total number of write requests seen -system.physmem.cpureqs 218338 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195456 # Total number of bytes read from memory -system.physmem.bytesWritten 52039168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429648 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096806 # Total number of read requests seen +system.physmem.writeReqs 813108 # Total number of write requests seen +system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195584 # Total number of bytes read from memory +system.physmem.bytesWritten 52038912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943442 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943150 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943601 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50711 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32505 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533111047500 # Total gap between requests +system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533114676500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154560 # Categorize read packet sizes +system.physmem.readPktSize::6 154562 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59094 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59090 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see @@ -139,9 +139,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see @@ -151,10 +151,10 @@ system.physmem.wrQLenPdf::8 2829 # Wh system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see @@ -162,23 +162,23 @@ system.physmem.wrQLenPdf::19 35352 # Wh system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see -system.physmem.totQLat 393223335500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485617965500 # Sum of mem lat for all requests -system.physmem.totBusLat 75482460000 # Total cycles spent in databus access -system.physmem.totBankLat 16912170000 # Total cycles spent in bank access -system.physmem.avgQLat 26047.33 # Average queueing delay per request -system.physmem.avgBankLat 1120.27 # Average bank access latency per request +system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests +system.physmem.totBusLat 75482470000 # Total cycles spent in databus access +system.physmem.totBankLat 16917518750 # Total cycles spent in bank access +system.physmem.avgQLat 26047.39 # Average queueing delay per request +system.physmem.avgBankLat 1120.63 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32167.60 # Average memory access latency +system.physmem.avgMemAccLat 32168.02 # Average memory access latency system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s @@ -186,12 +186,12 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.09 # Average write queue length over time -system.physmem.readRowHits 15020204 # Number of row buffer hits during reads -system.physmem.writeRowHits 793057 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.11 # Average write queue length over time +system.physmem.readRowHits 15020181 # Number of row buffer hits during reads +system.physmem.writeRowHits 793022 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159215.87 # Average gap between requests +system.physmem.avgGap 159216.11 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,15 +210,15 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14674954 # Number of BP lookups -system.cpu.branchPred.condPredicted 11760315 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9798337 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7946170 # Number of BTB hits +system.cpu.branchPred.lookups 14672817 # Number of BP lookups +system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.097129 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399969 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72392 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 14987449 # DTB read hits @@ -266,27 +266,27 @@ system.cpu.checker.numWorkItemsStarted 0 # nu system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51400725 # DTB read hits -system.cpu.dtb.read_misses 64230 # DTB read misses -system.cpu.dtb.write_hits 11699827 # DTB write hits -system.cpu.dtb.write_misses 15817 # DTB write misses +system.cpu.dtb.read_hits 51400888 # DTB read hits +system.cpu.dtb.read_misses 64225 # DTB read misses +system.cpu.dtb.write_hits 11700104 # DTB write hits +system.cpu.dtb.write_misses 15848 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6546 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2361 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 419 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6555 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51464955 # DTB read accesses -system.cpu.dtb.write_accesses 11715644 # DTB write accesses +system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51465113 # DTB read accesses +system.cpu.dtb.write_accesses 11715952 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100552 # DTB hits -system.cpu.dtb.misses 80047 # DTB misses -system.cpu.dtb.accesses 63180599 # DTB accesses -system.cpu.itb.inst_hits 12329192 # ITB inst hits -system.cpu.itb.inst_misses 11376 # ITB inst misses +system.cpu.dtb.hits 63100992 # DTB hits +system.cpu.dtb.misses 80073 # DTB misses +system.cpu.dtb.accesses 63181065 # DTB accesses +system.cpu.itb.inst_hits 12331220 # ITB inst hits +system.cpu.itb.inst_misses 11422 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,148 +295,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4940 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4954 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2865 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12340568 # ITB inst accesses -system.cpu.itb.hits 12329192 # DTB hits -system.cpu.itb.misses 11376 # DTB misses -system.cpu.itb.accesses 12340568 # DTB accesses -system.cpu.numCycles 471811908 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12342642 # ITB inst accesses +system.cpu.itb.hits 12331220 # DTB hits +system.cpu.itb.misses 11422 # DTB misses +system.cpu.itb.accesses 12342642 # DTB accesses +system.cpu.numCycles 471822965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30566850 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96025902 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14674954 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9346139 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21161280 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5294268 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122956 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95541161 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2622 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86967 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195337 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 356 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12325832 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900070 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151313220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130167339 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302330 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712200 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496857 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2222542 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109034 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2758411 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745566 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8798941 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151313220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32523025 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95170118 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19191132 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962347 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466598 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956722 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171732 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112651707 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566963 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34464368 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36692438 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52511672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18154881 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023263 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106120156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20539 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985607 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4064974 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 783 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110525870 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485527409 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485436293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91116 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32135831 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830318 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736784 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12149928 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20332565 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516637 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977838 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2480356 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97929601 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124328965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167666 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21748794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57017345 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501539 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151313220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821666 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535351 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107094975 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13518793 8.93% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7075318 4.68% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5935233 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12598116 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2801723 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1697051 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465636 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126375 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151313220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62335 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8363613 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413579 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58629316 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93112 0.07% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued @@ -449,99 +449,99 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 17 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52921084 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319626 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124328965 # Type of FU issued -system.cpu.iq.rate 0.263514 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839530 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071098 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409034606 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121678500 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85964427 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23410 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12602 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10310 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132792371 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12458 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623186 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued +system.cpu.iq.rate 0.263501 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4678002 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6260 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29908 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784543 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107773 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892534 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27942266 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433430 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100134856 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201220 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20332565 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516637 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410804 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113293 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3501 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29908 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350102 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268608 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618710 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121542985 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52087637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2785980 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221321 # number of nop insts executed -system.cpu.iew.exec_refs 64299335 # number of memory reference insts executed -system.cpu.iew.exec_branches 11558025 # Number of branches executed -system.cpu.iew.exec_stores 12211698 # Number of stores executed -system.cpu.iew.exec_rate 0.257609 # Inst execution rate -system.cpu.iew.wb_sent 120384508 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85974737 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47254500 # num instructions producing a value -system.cpu.iew.wb_consumers 88210457 # num instructions consuming a value +system.cpu.iew.exec_nop 221132 # number of nop insts executed +system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed +system.cpu.iew.exec_branches 11557425 # Number of branches executed +system.cpu.iew.exec_stores 12211932 # Number of stores executed +system.cpu.iew.exec_rate 0.257596 # Inst execution rate +system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47248258 # num instructions producing a value +system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535702 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21478461 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534359 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147846622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525881 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516310 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120416670 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13325889 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3878179 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2122601 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1929203 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968068 0.65% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1602055 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701521 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2902436 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147846622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle system.cpu.commit.committedInsts 60458107 # Number of instructions committed system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -552,261 +552,261 @@ system.cpu.commit.branches 9961339 # Nu system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. system.cpu.commit.function_calls 991261 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2902436 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242323721 # The number of ROB reads -system.cpu.rob.rob_writes 202019018 # The number of ROB writes -system.cpu.timesIdled 1771597 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320498688 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594329392 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.rob.rob_reads 242323943 # The number of ROB reads +system.cpu.rob.rob_writes 202004834 # The number of ROB writes +system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60307726 # Number of Instructions Simulated system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated -system.cpu.cpi 7.823407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550308718 # number of integer regfile reads -system.cpu.int_regfile_writes 88462541 # number of integer regfile writes -system.cpu.fp_regfile_reads 8334 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 30122249 # number of misc regfile reads +system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550297303 # number of integer regfile reads +system.cpu.int_regfile_writes 88455601 # number of integer regfile writes +system.cpu.fp_regfile_reads 8347 # number of floating regfile reads +system.cpu.fp_regfile_writes 2910 # number of floating regfile writes +system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979554 # number of replacements -system.cpu.icache.tagsinuse 511.616693 # Cycle average of tags in use -system.cpu.icache.total_refs 11266265 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.495415 # Average number of references to valid blocks. +system.cpu.icache.replacements 979954 # number of replacements +system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use +system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616693 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11266265 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11266265 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11266265 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11266265 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11266265 # number of overall hits -system.cpu.icache.overall_hits::total 11266265 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059442 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059442 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059442 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059442 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059442 # number of overall misses -system.cpu.icache.overall_misses::total 1059442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13996692496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13996692496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13996692496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13996692496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13996692496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13996692496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12325707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12325707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12325707 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12325707 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12325707 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12325707 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13211.381554 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13211.381554 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13211.381554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13211.381554 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5064 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits +system.cpu.icache.overall_hits::total 11267650 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses +system.cpu.icache.overall_misses::total 1060047 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.050505 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79338 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79338 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79338 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79338 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79338 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79338 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11377433497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11377433497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11377433497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11377433497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11377433497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11377433497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79541 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79541 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79541 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79541 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79541 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79541 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980506 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980506 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980506 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980506 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11382269996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11382269996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11382269996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.394106 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.394106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079537 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64331 # number of replacements -system.cpu.l2cache.tagsinuse 51338.673427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885045 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129724 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.531197 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498168723000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36938.437105 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.056413 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64333 # number of replacements +system.cpu.l2cache.tagsinuse 51339.387704 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1885585 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129729 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.534799 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2523139741500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36938.518996 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.781617 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8154.476716 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6219.702844 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563636 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000398 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8154.357820 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6219.728923 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563637 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000409 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124427 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.094905 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783366 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52232 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10453 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387163 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416497 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607765 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607765 # number of Writeback hits +system.cpu.l2cache.occ_percent::cpu.inst 0.124426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.094906 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783377 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52369 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10535 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967038 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387148 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1417090 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607758 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607758 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 14 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 14 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112922 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112922 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 52232 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10453 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 541729027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5588812451 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6133075770 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002473267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007554097 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911803456 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911803456 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002521767 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015974 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986486 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986486 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914086223 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919167053 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026734 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38817.254560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39227.919476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10222363 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256341 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256341 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24717764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24717764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24717764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24717764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050863 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050863 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289887 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289887 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052871 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24717465 # 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average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30898.785260 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30275 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18688 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2630 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.511407 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.354839 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219123179899 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219123179899 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047640 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # 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average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,10 +1103,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229570022553 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229570022553 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7b8c607e4..0c5e2cb7e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -131,6 +133,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -589,6 +592,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index e24b483f1..960d43f01 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102958 # Number of seconds simulated -sim_ticks 1102958416500 # Number of ticks simulated -final_tick 1102958416500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102954 # Number of seconds simulated +sim_ticks 1102954033500 # Number of ticks simulated +final_tick 1102954033500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66795 # Simulator instruction rate (inst/s) -host_op_rate 85978 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1196309321 # Simulator tick rate (ticks/s) -host_mem_usage 404244 # Number of bytes of host memory used -host_seconds 921.97 # Real time elapsed on the host -sim_insts 61582525 # Number of instructions simulated -sim_ops 79269125 # Number of ops (including micro ops) simulated +host_inst_rate 66183 # Simulator instruction rate (inst/s) +host_op_rate 85190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1185337549 # Simulator tick rate (ticks/s) +host_mem_usage 402972 # Number of bytes of host memory used +host_seconds 930.50 # Real time elapsed on the host +sim_insts 61582952 # Number of instructions simulated +sim_ops 79269552 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 410752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4380596 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405056 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5224880 # Number of bytes read from this memory -system.physmem.bytes_read::total 59182180 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 410752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405056 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4259968 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 410112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4380532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 404608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5226032 # Number of bytes read from this memory +system.physmem.bytes_read::total 59181988 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 404608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 814720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4260416 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7287312 # Number of bytes written to this memory +system.physmem.bytes_written::total 7287760 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6418 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81665 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66562 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6322 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81683 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257809 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66569 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823398 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44207273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823405 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44207449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 372409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3971678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4737150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53657671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 372409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367245 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3862311 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3971636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 366840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4738214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53657710 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 366840 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 738671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862732 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729336 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6607060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3862311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44207273 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6607492 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44207449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 372409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3987091 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367245 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7466486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60264731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257812 # Total number of read requests seen -system.physmem.writeReqs 823398 # Total number of write requests seen -system.physmem.cpureqs 242000 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400499968 # Total number of bytes read from memory -system.physmem.bytesWritten 52697472 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59182180 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7287312 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 78 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12579 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391407 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390854 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391518 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390872 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390705 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390472 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391263 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51540 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50963 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 371831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3987049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 366840 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7467561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60265202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257809 # Total number of read requests seen +system.physmem.writeReqs 823405 # Total number of write requests seen +system.physmem.cpureqs 242034 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400499776 # Total number of bytes read from memory +system.physmem.bytesWritten 52697920 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59181988 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7287760 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 69 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12609 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391396 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391210 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390879 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391633 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391393 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390703 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390862 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391239 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390469 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391266 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51546 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50964 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51665 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51667 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52037 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51495 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51842 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51173 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51503 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51884 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51249 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51170 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51891 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32627 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102957282500 # Total gap between requests +system.physmem.numWrRetry 32620 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102952897500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162859 # Categorize read packet sizes +system.physmem.readPktSize::6 162856 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66562 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391898 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1085856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064332 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44429 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 15280 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7853 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66569 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441549 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086056 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098465 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44432 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44227 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 15214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,15 +156,15 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3001 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see @@ -177,38 +177,38 @@ system.physmem.wrQLenPdf::17 35800 # Wh system.physmem.wrQLenPdf::18 35800 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35800 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32713 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32643 # What write queue length does an incoming req see -system.physmem.totQLat 199244474250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239068869250 # Sum of mem lat for all requests -system.physmem.totBusLat 31288670000 # Total cycles spent in databus access -system.physmem.totBankLat 8535725000 # Total cycles spent in bank access -system.physmem.avgQLat 31839.72 # Average queueing delay per request -system.physmem.avgBankLat 1364.03 # Average bank access latency per request +system.physmem.wrQLenPdf::21 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32633 # What write queue length does an incoming req see +system.physmem.totQLat 199184958750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239005190000 # Sum of mem lat for all requests +system.physmem.totBusLat 31288700000 # Total cycles spent in databus access +system.physmem.totBankLat 8531531250 # Total cycles spent in bank access +system.physmem.avgQLat 31830.17 # Average queueing delay per request +system.physmem.avgBankLat 1363.36 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38203.74 # Average memory access latency -system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 38193.53 # Average memory access latency +system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.41 # Average write queue length over time -system.physmem.readRowHits 6213843 # Number of row buffer hits during reads -system.physmem.writeRowHits 799878 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.07 # Average write queue length over time +system.physmem.readRowHits 6213915 # Number of row buffer hits during reads +system.physmem.writeRowHits 799980 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes -system.physmem.avgGap 155758.31 # Average gap between requests +system.physmem.writeRowHitRate 97.16 # Row buffer hit rate for writes +system.physmem.avgGap 155757.60 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -227,237 +227,237 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72564 # number of replacements -system.l2c.tagsinuse 53751.759262 # Cycle average of tags in use -system.l2c.total_refs 1839556 # Total number of references to valid blocks. -system.l2c.sampled_refs 137761 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.353242 # Average number of references to valid blocks. +system.l2c.replacements 72561 # number of replacements +system.l2c.tagsinuse 53740.730134 # Cycle average of tags in use +system.l2c.total_refs 1839807 # Total number of references to valid blocks. +system.l2c.sampled_refs 137757 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.355452 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39378.859227 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.194190 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.010198 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4015.520084 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2826.859367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 10.896267 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3720.882915 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3794.537014 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600874 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000064 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061272 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043134 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056776 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.057900 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21638 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4069 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 385706 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30870 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5056 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589485 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198042 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1401521 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580941 # number of Writeback hits -system.l2c.Writeback_hits::total 580941 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1130 # number of UpgradeReq hits +system.l2c.occ_blocks::writebacks 39373.368087 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.826392 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.258184 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4017.777159 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2831.337785 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 9.908379 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3708.426786 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3795.827361 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600790 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061306 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043203 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000151 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056586 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.057920 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820018 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21639 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4056 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386080 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166672 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30823 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4930 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198131 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1401635 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581048 # number of Writeback hits +system.l2c.Writeback_hits::total 581048 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1122 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 742 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1872 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 147 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 340 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58929 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106971 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21638 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4069 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 385706 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214697 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30870 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5056 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589485 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256971 # number of demand (read+write) hits -system.l2c.demand_hits::total 1508492 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21638 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4069 # number of overall hits -system.l2c.overall_hits::cpu0.inst 385706 # number of overall hits -system.l2c.overall_hits::cpu0.data 214697 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30870 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5056 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589485 # number of overall hits -system.l2c.overall_hits::cpu1.data 256971 # number of overall hits -system.l2c.overall_hits::total 1508492 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.UpgradeReq_hits::total 1864 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48001 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58894 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106895 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21639 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4056 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386080 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214673 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30823 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4930 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 257025 # number of demand (read+write) hits +system.l2c.demand_hits::total 1508530 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21639 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4056 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386080 # number of overall hits +system.l2c.overall_hits::cpu0.data 214673 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30823 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4930 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589304 # number of overall hits +system.l2c.overall_hits::cpu1.data 257025 # number of overall hits +system.l2c.overall_hits::total 1508530 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6298 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6402 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6294 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6282 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25309 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5141 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3789 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8930 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 641 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 6288 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6413 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6293 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25310 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5149 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3783 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8932 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 648 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1064 # number of SCUpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 63471 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76579 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140050 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 13 # number of demand (read+write) misses +system.l2c.ReadExReq_misses::cpu1.data 76594 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140065 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # 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number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1838032 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180626880389 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194091233529 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036774 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030623 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180601825434 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194065955584 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000508 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000739 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016013 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036832 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000519 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010542 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030667 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.017685 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.819805 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836239 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.826699 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.768585 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.738899 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.756621 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569180 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565125 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566956 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098744 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000600 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016053 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.245405 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010551 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.243756 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098744 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.821081 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836022 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.827343 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772348 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.740214 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.759458 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569390 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565319 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567157 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000508 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000739 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016013 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000519 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010542 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.243778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098752 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000508 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000739 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016013 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000519 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010542 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.243778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098752 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45112.000157 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50778.834905 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46739.928982 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10056.507489 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10156.562681 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10098.960918 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10082.088924 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.694712 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10077.604541 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37457.263254 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41132.477559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39466.861514 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44454.161725 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 50145.589408 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46316.033088 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.000583 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10167.910124 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10103.974474 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10073.495370 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.055288 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10061.593985 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37401.096989 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41147.448442 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39449.774697 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54135.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38044.845918 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41828.202768 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40498.025444 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43065.487685 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38154.832462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 60927.470588 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47991.177696 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41861.113151 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40577.207474 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43405.395512 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38044.845918 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55313.437500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47257.772257 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41828.202768 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40498.025444 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -648,38 +648,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5991996 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4570590 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295222 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3736406 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2908427 # Number of BTB hits +system.cpu0.branchPred.lookups 5994746 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4572445 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294986 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3765254 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2911375 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.840229 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 670993 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28752 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.322141 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 671631 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28577 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8901229 # DTB read hits -system.cpu0.dtb.read_misses 28750 # DTB read misses -system.cpu0.dtb.write_hits 5135502 # DTB write hits -system.cpu0.dtb.write_misses 5613 # DTB write misses +system.cpu0.dtb.read_hits 8900432 # DTB read hits +system.cpu0.dtb.read_misses 28720 # DTB read misses +system.cpu0.dtb.write_hits 5136537 # DTB write hits +system.cpu0.dtb.write_misses 5640 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1817 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 968 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1815 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1027 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 548 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8929979 # DTB read accesses -system.cpu0.dtb.write_accesses 5141115 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8929152 # DTB read accesses +system.cpu0.dtb.write_accesses 5142177 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14036731 # DTB hits -system.cpu0.dtb.misses 34363 # DTB misses -system.cpu0.dtb.accesses 14071094 # DTB accesses -system.cpu0.itb.inst_hits 4213364 # ITB inst hits -system.cpu0.itb.inst_misses 5048 # ITB inst misses +system.cpu0.dtb.hits 14036969 # DTB hits +system.cpu0.dtb.misses 34360 # DTB misses +system.cpu0.dtb.accesses 14071329 # DTB accesses +system.cpu0.itb.inst_hits 4213831 # ITB inst hits +system.cpu0.itb.inst_misses 5055 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -688,148 +688,148 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1344 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1341 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1480 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4218412 # ITB inst accesses -system.cpu0.itb.hits 4213364 # DTB hits -system.cpu0.itb.misses 5048 # DTB misses -system.cpu0.itb.accesses 4218412 # DTB accesses -system.cpu0.numCycles 67828518 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4218886 # ITB inst accesses +system.cpu0.itb.hits 4213831 # DTB hits +system.cpu0.itb.misses 5055 # DTB misses +system.cpu0.itb.accesses 4218886 # DTB accesses +system.cpu0.numCycles 67827180 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11769514 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31989018 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5991996 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3579420 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7508503 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450801 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60684 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20631180 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 48154 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85409 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4211784 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 156653 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2012 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41149957 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004329 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.384713 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11769589 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31997398 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5994746 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3583006 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7510057 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450935 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 59891 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19410639 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4833 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47194 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1299057 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4212263 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157193 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2052 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41143300 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004817 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385260 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33648798 81.77% 81.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 562155 1.37% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818096 1.99% 85.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 677471 1.65% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773499 1.88% 88.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558438 1.36% 90.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 664363 1.61% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352105 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3095032 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33640645 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 563027 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816788 1.99% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 677485 1.65% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772099 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558236 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667723 1.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351865 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3095432 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41149957 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088340 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471616 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12268271 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20578267 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6812810 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512754 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977855 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934513 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64660 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39970940 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212731 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977855 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12837244 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5740254 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12723807 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6707246 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2163551 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38872652 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1850 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 437651 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1233683 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39221318 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175562913 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175528548 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34365 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30916412 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8304905 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410995 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 369967 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5350401 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7642102 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5682819 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1122438 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1201311 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36799804 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 894837 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37219527 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80251 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6274775 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13129416 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256270 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41149957 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904485 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.513383 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41143300 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088383 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471749 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12271204 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20567331 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6814121 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512354 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 978290 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934838 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64553 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39983053 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212073 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 978290 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12839379 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5742381 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12712172 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6708467 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2162611 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38883586 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1814 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 436137 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1233923 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 17 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39230664 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175613245 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175579140 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34105 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30916187 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8314476 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411042 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370243 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5355635 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7643947 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5684540 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124242 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1215247 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36809311 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895353 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37222613 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81088 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6285112 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13160919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256794 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41143300 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904707 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.513127 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26028016 63.25% 63.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5729313 13.92% 77.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3155280 7.67% 84.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2465546 5.99% 90.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2105206 5.12% 95.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 932712 2.27% 98.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 494007 1.20% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184426 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 55451 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26016757 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5731331 13.93% 77.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3155319 7.67% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471251 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2103314 5.11% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 932641 2.27% 98.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 493188 1.20% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184690 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54809 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41149957 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41143300 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26761 2.50% 2.50% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.54% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841654 78.63% 81.17% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 201534 18.83% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26572 2.49% 2.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 453 0.04% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841830 78.79% 81.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 199561 18.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22319985 59.97% 60.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46930 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22321556 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46948 0.13% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued @@ -857,361 +857,361 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.24% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.24% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9357970 25.14% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5441771 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9357811 25.14% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5443427 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37219527 # Type of FU issued -system.cpu0.iq.rate 0.548730 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070402 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028759 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116765436 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43977253 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34319519 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8378 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4660 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3869 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38233387 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4393 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306639 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37222613 # Type of FU issued +system.cpu0.iq.rate 0.548786 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068416 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028703 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116763775 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43997708 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34321266 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8390 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4632 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3861 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38234480 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4400 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306660 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1370211 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2367 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13030 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 536244 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372064 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2343 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13106 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537968 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192745 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5335 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192754 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5299 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977855 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4123044 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98683 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37812695 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84467 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7642102 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5682819 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571073 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39963 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2983 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13030 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149756 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117796 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267552 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36844879 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9216416 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 374648 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 978290 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4120588 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98455 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37822346 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84553 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7643947 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5684540 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571228 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39920 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2911 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13106 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150072 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117309 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267381 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36846322 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9215739 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376291 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118054 # number of nop insts executed -system.cpu0.iew.exec_refs 14611375 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4852197 # Number of branches executed -system.cpu0.iew.exec_stores 5394959 # Number of stores executed -system.cpu0.iew.exec_rate 0.543206 # Inst execution rate -system.cpu0.iew.wb_sent 36651456 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34323388 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18278983 # num instructions producing a value -system.cpu0.iew.wb_consumers 35164474 # num instructions consuming a value +system.cpu0.iew.exec_nop 117682 # number of nop insts executed +system.cpu0.iew.exec_refs 14611771 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4852307 # Number of branches executed +system.cpu0.iew.exec_stores 5396032 # Number of stores executed +system.cpu0.iew.exec_rate 0.543238 # Inst execution rate +system.cpu0.iew.wb_sent 36653422 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34325127 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18280728 # num instructions producing a value +system.cpu0.iew.wb_consumers 35164479 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506032 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519814 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506067 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519863 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6082175 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231668 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40172102 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778393 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739779 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6092264 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638559 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231469 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40165010 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778528 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.739872 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28502177 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5716215 14.23% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1915316 4.77% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 977454 2.43% 92.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784200 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 521856 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386686 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 221286 0.55% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1146912 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28490647 70.93% 70.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5723698 14.25% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913208 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 977623 2.43% 92.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784001 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 521196 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 385694 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 221095 0.55% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1147848 2.86% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40172102 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23670658 # Number of instructions committed -system.cpu0.commit.committedOps 31269703 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40165010 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23670535 # Number of instructions committed +system.cpu0.commit.committedOps 31269580 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11418466 # Number of memory references committed -system.cpu0.commit.loads 6271891 # Number of loads committed +system.cpu0.commit.refs 11418455 # Number of memory references committed +system.cpu0.commit.loads 6271883 # Number of loads committed system.cpu0.commit.membars 229601 # Number of memory barriers committed -system.cpu0.commit.branches 4243665 # Number of branches committed +system.cpu0.commit.branches 4243632 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27627466 # Number of committed integer instructions. +system.cpu0.commit.int_insts 27627385 # Number of committed integer instructions. system.cpu0.commit.function_calls 489162 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1146912 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 1147848 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75526096 # The number of ROB reads -system.cpu0.rob.rob_writes 75683450 # The number of ROB writes -system.cpu0.timesIdled 360623 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26678561 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138046604 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23589916 # Number of Instructions Simulated -system.cpu0.committedOps 31188961 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23589916 # Number of Instructions Simulated -system.cpu0.cpi 2.875318 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.875318 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347788 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347788 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171729807 # number of integer regfile reads -system.cpu0.int_regfile_writes 34069963 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3242 # number of floating regfile reads +system.cpu0.rob.rob_reads 75528065 # The number of ROB reads +system.cpu0.rob.rob_writes 75703855 # The number of ROB writes +system.cpu0.timesIdled 360661 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26683880 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138039181 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23589793 # Number of Instructions Simulated +system.cpu0.committedOps 31188838 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23589793 # Number of Instructions Simulated +system.cpu0.cpi 2.875277 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.875277 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347793 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347793 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171736211 # number of integer regfile reads +system.cpu0.int_regfile_writes 34071636 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3249 # number of floating regfile reads system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13000351 # number of misc regfile reads -system.cpu0.misc_regfile_writes 450996 # number of misc regfile writes -system.cpu0.icache.replacements 392023 # number of replacements -system.cpu0.icache.tagsinuse 511.011023 # Cycle average of tags in use -system.cpu0.icache.total_refs 3788789 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 392535 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.652105 # Average number of references to valid blocks. +system.cpu0.misc_regfile_reads 12999243 # number of misc regfile reads +system.cpu0.misc_regfile_writes 450984 # number of misc regfile writes +system.cpu0.icache.replacements 392403 # number of replacements +system.cpu0.icache.tagsinuse 511.011252 # Cycle average of tags in use +system.cpu0.icache.total_refs 3789022 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 392915 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.643363 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6567370000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.011023 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998068 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998068 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3788789 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3788789 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3788789 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3788789 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3788789 # number of overall hits -system.cpu0.icache.overall_hits::total 3788789 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 422860 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 422860 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 422860 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 422860 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 422860 # number of overall misses -system.cpu0.icache.overall_misses::total 422860 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794359497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5794359497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5794359497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5794359497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5794359497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5794359497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4211649 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4211649 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4211649 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4211649 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4211649 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4211649 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100402 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100402 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100402 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100402 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100402 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100402 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13702.784602 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13702.784602 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13702.784602 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13702.784602 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13702.784602 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2670 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 511.011252 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998069 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3789022 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3789022 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3789022 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3789022 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3789022 # number of overall hits +system.cpu0.icache.overall_hits::total 3789022 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423106 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423106 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423106 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423106 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423106 # number of overall misses +system.cpu0.icache.overall_misses::total 423106 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5802286496 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5802286496 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5802286496 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5802286496 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5802286496 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5802286496 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4212128 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4212128 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4212128 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4212128 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4212128 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4212128 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100449 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100449 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100449 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100449 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100449 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100449 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13713.552859 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13713.552859 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13713.552859 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13713.552859 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13713.552859 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4195 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 161 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 183 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.583851 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.923497 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30304 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30304 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30304 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30304 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30304 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30304 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392556 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392556 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392556 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392556 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392556 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392556 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4741290497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4741290497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4741290497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4741290497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4741290497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4741290497 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30174 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30174 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30174 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30174 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30174 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30174 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392932 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392932 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392932 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392932 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392932 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392932 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4748967496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4748967496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4748967496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4748967496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4748967496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4748967496 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7889500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7889500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7889500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7889500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093207 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093207 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093207 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093207 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.997781 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.997781 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.997781 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093286 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093286 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093286 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093286 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12085.977971 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12085.977971 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12085.977971 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275942 # number of replacements -system.cpu0.dcache.tagsinuse 461.279186 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9251897 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276454 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.466316 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275974 # number of replacements +system.cpu0.dcache.tagsinuse 462.017037 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9251393 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276486 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.460620 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43505000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 461.279186 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.900936 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.900936 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5774894 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5774894 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157331 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3157331 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139041 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139041 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137030 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137030 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8932225 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8932225 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8932225 # number of overall hits -system.cpu0.dcache.overall_hits::total 8932225 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392966 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392966 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582314 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582314 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8784 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8784 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7484 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7484 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1975280 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1975280 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1975280 # number of overall misses -system.cpu0.dcache.overall_misses::total 1975280 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5474748500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5474748500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60929978373 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60929978373 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88607500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88607500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46564000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46564000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66404726873 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66404726873 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66404726873 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66404726873 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6167860 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6167860 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.occ_blocks::cpu0.data 462.017037 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.902377 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.902377 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5774321 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5774321 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3157289 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3157289 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139126 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139126 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137035 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137035 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8931610 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8931610 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8931610 # number of overall hits +system.cpu0.dcache.overall_hits::total 8931610 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392659 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392659 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582356 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582356 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8783 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8783 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7478 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7478 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975015 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975015 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975015 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975015 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5465751000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5465751000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60871178363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60871178363 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88481000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88481000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46675000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46675000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66336929363 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66336929363 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66336929363 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66336929363 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6166980 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6166980 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739645 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 4739645 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147825 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147825 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144514 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144514 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10907505 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10907505 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10907505 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10907505 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063712 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063712 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333847 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333847 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059422 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059422 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051787 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051787 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181094 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181094 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181094 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181094 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13931.863062 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13931.863062 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38506.881929 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38506.881929 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10087.374772 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10087.374772 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.806521 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.806521 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33617.880439 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33617.880439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33617.880439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33617.880439 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8609 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2195 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 639 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 78 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.472613 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 28.141026 # average number of cycles each access was blocked +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147909 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147909 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144513 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144513 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10906625 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10906625 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10906625 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10906625 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063671 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063671 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333855 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333855 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059381 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059381 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051746 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051746 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181084 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181084 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181084 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181084 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13919.841389 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13919.841389 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38468.700067 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38468.700067 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10074.120460 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10074.120460 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6241.642150 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6241.642150 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33588.063566 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33588.063566 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33588.063566 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8548 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2163 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 649 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 77 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.171032 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 28.090909 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256402 # number of writebacks -system.cpu0.dcache.writebacks::total 256402 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204348 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204348 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452057 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1452057 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 461 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656405 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656405 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656405 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656405 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188618 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188618 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130257 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130257 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8323 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8323 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7482 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7482 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318875 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318875 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318875 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318875 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2375120000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2375120000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054292491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054292491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66886000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66886000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6429412491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6429412491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6429412491 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6429412491 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513828500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513828500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180296878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180296878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14694125378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14694125378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030581 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030581 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027482 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027482 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056303 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056303 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051774 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051774 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029234 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029234 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029234 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12592.223436 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12592.223436 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31125.332926 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31125.332926 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8036.284993 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8036.284993 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4223.469661 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4223.469661 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20162.798874 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20162.798874 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256417 # number of writebacks +system.cpu0.dcache.writebacks::total 256417 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203981 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203981 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452148 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1452148 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 473 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 473 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656129 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656129 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656129 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656129 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188678 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130208 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130208 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318886 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318886 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318886 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318886 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371660000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371660000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4050141991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4050141991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66675500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66675500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31721000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31721000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6421801991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6421801991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6421801991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6421801991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513534500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513534500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180320378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180320378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693854878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693854878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030595 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030595 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027472 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027472 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056183 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056183 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051739 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029238 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029238 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029238 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12569.880961 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12569.880961 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31105.170120 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31105.170120 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8023.525872 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8023.525872 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4242.476929 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4242.476929 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20138.237461 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20138.237461 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1219,38 +1219,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9066051 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7453207 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 407044 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6058627 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5236584 # Number of BTB hits +system.cpu1.branchPred.lookups 9076266 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7463483 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407973 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6084116 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5247879 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.431860 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 771955 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42437 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.255407 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773475 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42302 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42902362 # DTB read hits -system.cpu1.dtb.read_misses 36935 # DTB read misses -system.cpu1.dtb.write_hits 6824519 # DTB write hits -system.cpu1.dtb.write_misses 10718 # DTB write misses +system.cpu1.dtb.read_hits 42903620 # DTB read hits +system.cpu1.dtb.read_misses 37068 # DTB read misses +system.cpu1.dtb.write_hits 6823215 # DTB write hits +system.cpu1.dtb.write_misses 10679 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2714 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2009 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2777 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 645 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42939297 # DTB read accesses -system.cpu1.dtb.write_accesses 6835237 # DTB write accesses +system.cpu1.dtb.perms_faults 663 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42940688 # DTB read accesses +system.cpu1.dtb.write_accesses 6833894 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49726881 # DTB hits -system.cpu1.dtb.misses 47653 # DTB misses -system.cpu1.dtb.accesses 49774534 # DTB accesses -system.cpu1.itb.inst_hits 8392998 # ITB inst hits -system.cpu1.itb.inst_misses 5431 # ITB inst misses +system.cpu1.dtb.hits 49726835 # DTB hits +system.cpu1.dtb.misses 47747 # DTB misses +system.cpu1.dtb.accesses 49774582 # DTB accesses +system.cpu1.itb.inst_hits 8394995 # ITB inst hits +system.cpu1.itb.inst_misses 5378 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1259,114 +1259,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1500 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8398429 # ITB inst accesses -system.cpu1.itb.hits 8392998 # DTB hits -system.cpu1.itb.misses 5431 # DTB misses -system.cpu1.itb.accesses 8398429 # DTB accesses -system.cpu1.numCycles 408779942 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8400373 # ITB inst accesses +system.cpu1.itb.hits 8394995 # DTB hits +system.cpu1.itb.misses 5378 # DTB misses +system.cpu1.itb.accesses 8400373 # DTB accesses +system.cpu1.numCycles 408777731 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19814855 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66055643 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9066051 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6008539 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14146730 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3957386 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 64683 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77267641 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42583 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129813 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 133 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8391200 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740435 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2770 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114169430 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700459 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.044215 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19817241 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66077936 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9076266 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6021354 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14149044 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3958978 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63415 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 75978247 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4643 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42826 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1407438 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 103 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8393192 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 739597 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114161892 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700766 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.044841 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100030180 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 795116 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937715 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1888304 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1526967 1.34% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 578073 0.51% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2128721 1.86% 94.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 409818 0.36% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5874536 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100020305 87.61% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 795953 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939001 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1889167 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1518004 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 578108 0.51% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2132011 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410005 0.36% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5879338 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114169430 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022178 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161592 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21335636 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76916914 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12791603 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523584 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2601693 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1104215 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98013 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75225150 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326089 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2601693 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22720139 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31942959 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40740266 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11835652 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328721 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69758398 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18799 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 669077 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086745 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 378 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73725482 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321189458 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321130296 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59162 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49052273 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24673209 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444958 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387932 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7868643 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13207791 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8146456 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1036357 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1539549 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63487430 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157915 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89117422 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94398 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16230957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45692140 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277223 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114169430 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780572 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.518996 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114161892 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022203 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161648 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21336269 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76905312 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12792890 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524784 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2602637 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1103950 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97871 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75228090 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 324995 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2602637 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22719770 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31941572 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40729697 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11839035 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4329181 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69767929 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18791 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669754 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086107 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 334 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73761871 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321211401 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321151882 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59519 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49052831 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24709040 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445091 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388163 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7873081 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13208830 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8144792 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1029727 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1553546 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63522315 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158429 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89134167 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94409 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16267434 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45777798 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277724 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114161892 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780770 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519105 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83779617 73.38% 73.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8401659 7.36% 80.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4300327 3.77% 84.51% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3769049 3.30% 87.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10578609 9.27% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966316 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1028949 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 270980 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73924 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83758719 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8417078 7.37% 80.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4293584 3.76% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3776789 3.31% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10574202 9.26% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966117 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1029866 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 271331 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 74206 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114169430 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114161892 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 31906 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32060 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -1394,395 +1394,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7548325 95.86% 96.28% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 292902 3.72% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7549280 95.84% 96.26% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 294896 3.74% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37601994 42.19% 42.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59184 0.07% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.61% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43968762 49.34% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7172015 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37620086 42.21% 42.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59138 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43968936 49.33% 91.96% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170532 8.04% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89117422 # Type of FU issued -system.cpu1.iq.rate 0.218008 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7874129 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088357 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300405264 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80884614 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53615647 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15005 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6847 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96669700 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7919 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342898 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89134167 # Type of FU issued +system.cpu1.iq.rate 0.218050 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7877234 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088375 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300434418 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80956642 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53641825 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15018 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8136 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6869 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96689561 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7908 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342287 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3454228 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3835 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 16932 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1307521 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3455090 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3893 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17135 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1305851 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906117 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888056 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31905929 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888458 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2601693 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24180087 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 359608 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64749015 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 111417 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13207791 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8146456 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869148 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64619 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3744 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 16932 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200731 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155107 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355838 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86675355 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43272699 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2442067 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2602637 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24185109 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359685 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64785366 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111899 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13208830 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8144792 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869085 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64974 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3561 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17135 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 202123 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154728 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356851 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86703480 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43273897 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2430687 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103670 # number of nop insts executed -system.cpu1.iew.exec_refs 50383092 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6989591 # Number of branches executed -system.cpu1.iew.exec_stores 7110393 # Number of stores executed -system.cpu1.iew.exec_rate 0.212034 # Inst execution rate -system.cpu1.iew.wb_sent 85698110 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53622494 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29929482 # num instructions producing a value -system.cpu1.iew.wb_consumers 53410166 # num instructions consuming a value +system.cpu1.iew.exec_nop 104622 # number of nop insts executed +system.cpu1.iew.exec_refs 50383100 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6997981 # Number of branches executed +system.cpu1.iew.exec_stores 7109203 # Number of stores executed +system.cpu1.iew.exec_rate 0.212104 # Inst execution rate +system.cpu1.iew.wb_sent 85724428 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53648694 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29926721 # num instructions producing a value +system.cpu1.iew.wb_consumers 53389506 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131177 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560371 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131242 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560536 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16109317 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880692 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310619 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111567737 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431575 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399552 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16147511 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880705 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311675 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111559255 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431612 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399673 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94819418 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8239382 7.39% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114964 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1255344 1.13% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1246323 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567268 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1001355 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504765 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1818918 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94810700 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8240774 7.39% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114811 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254575 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1245157 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 568382 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 999815 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 505524 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1819517 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111567737 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38062248 # Number of instructions committed -system.cpu1.commit.committedOps 48149803 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111559255 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38062798 # Number of instructions committed +system.cpu1.commit.committedOps 48150353 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16592498 # Number of memory references committed -system.cpu1.commit.loads 9753563 # Number of loads committed +system.cpu1.commit.refs 16592681 # Number of memory references committed +system.cpu1.commit.loads 9753740 # Number of loads committed system.cpu1.commit.membars 190132 # Number of memory barriers committed -system.cpu1.commit.branches 5967184 # Number of branches committed +system.cpu1.commit.branches 5967363 # Number of branches committed system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42685255 # Number of committed integer instructions. +system.cpu1.commit.int_insts 42685619 # Number of committed integer instructions. system.cpu1.commit.function_calls 534609 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1818918 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 1819517 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172963873 # The number of ROB reads -system.cpu1.rob.rob_writes 131212452 # The number of ROB writes -system.cpu1.timesIdled 1408163 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294610512 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796500385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37992609 # Number of Instructions Simulated -system.cpu1.committedOps 48080164 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37992609 # Number of Instructions Simulated -system.cpu1.cpi 10.759460 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759460 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092941 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092941 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387855246 # number of integer regfile reads -system.cpu1.int_regfile_writes 56190036 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4937 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18474333 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405457 # number of misc regfile writes -system.cpu1.icache.replacements 595836 # number of replacements -system.cpu1.icache.tagsinuse 480.940966 # Cycle average of tags in use -system.cpu1.icache.total_refs 7749865 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 596348 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.995541 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74230255500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.940966 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.939338 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.939338 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7749865 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7749865 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7749865 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7749865 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7749865 # number of overall hits -system.cpu1.icache.overall_hits::total 7749865 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641285 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641285 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641285 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641285 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641285 # number of overall misses -system.cpu1.icache.overall_misses::total 641285 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8628357996 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8628357996 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8628357996 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8628357996 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8628357996 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8628357996 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8391150 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8391150 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8391150 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8391150 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8391150 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8391150 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076424 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076424 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076424 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076424 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076424 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076424 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13454.794664 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13454.794664 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13454.794664 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13454.794664 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13454.794664 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3208 # number of cycles access was blocked +system.cpu1.rob.rob_reads 172993511 # The number of ROB reads +system.cpu1.rob.rob_writes 131291211 # The number of ROB writes +system.cpu1.timesIdled 1408204 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294615839 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796493799 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37993159 # Number of Instructions Simulated +system.cpu1.committedOps 48080714 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37993159 # Number of Instructions Simulated +system.cpu1.cpi 10.759246 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759246 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092943 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092943 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387964882 # number of integer regfile reads +system.cpu1.int_regfile_writes 56217113 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4997 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2346 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18468785 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405479 # number of misc regfile writes +system.cpu1.icache.replacements 595625 # number of replacements +system.cpu1.icache.tagsinuse 480.695488 # Cycle average of tags in use +system.cpu1.icache.total_refs 7752260 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 596137 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.004158 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74233129000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.695488 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938858 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938858 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7752260 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7752260 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7752260 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7752260 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7752260 # number of overall hits +system.cpu1.icache.overall_hits::total 7752260 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 640881 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 640881 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 640881 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 640881 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 640881 # number of overall misses +system.cpu1.icache.overall_misses::total 640881 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13453.052899 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13453.052899 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2044 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 18.651163 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.883721 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44912 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7067932496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7067932496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7067932496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7067932496 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7067932496 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44715 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44715 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44715 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44715 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44715 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44715 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596166 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596166 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596166 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596166 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596166 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596166 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7061200496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7061200496 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7061200496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7061200496 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7061200496 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7061200496 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2836500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2836500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2836500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2836500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071072 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071072 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071072 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071072 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.529992 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.529992 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.529992 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071030 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071030 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071030 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.352908 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.352908 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.352908 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.352908 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # 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Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927110 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8307994 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8307994 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4138933 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138933 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97647 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97647 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94867 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94867 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12446927 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12446927 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12446927 # number of overall hits -system.cpu1.dcache.overall_hits::total 12446927 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 399316 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 399316 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1556536 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1556536 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13951 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13951 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10617 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10617 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1955852 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1955852 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1955852 # number of overall misses -system.cpu1.dcache.overall_misses::total 1955852 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6096380000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6096380000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61399313493 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61399313493 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129350500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53940000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53940000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67495693493 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67495693493 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67495693493 # 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number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 400056 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1556122 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556122 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13956 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13956 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10608 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10608 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1956178 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1956178 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1956178 # number of overall misses +system.cpu1.dcache.overall_misses::total 1956178 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6114203000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6114203000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61457337496 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61457337496 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 130378000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 130378000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53868000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53868000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67571540496 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67571540496 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67571540496 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67571540496 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8709123 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8709123 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 5695469 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 5695469 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111598 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111598 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105484 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105484 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14402779 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14402779 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14402779 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14402779 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045860 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045860 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273294 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273294 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125011 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125011 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100650 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100650 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135797 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135797 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135797 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135797 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15267.056667 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15267.056667 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39446.124916 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39446.124916 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9271.772633 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9271.772633 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.531224 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.531224 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34509.611920 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34509.611920 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34509.611920 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 27560 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 11546 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3309 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 159 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.328800 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 72.616352 # average number of cycles each access was blocked +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111477 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111477 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105481 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105481 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14404592 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14404592 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14404592 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14404592 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045935 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045935 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273221 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273221 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125192 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125192 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100568 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100568 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135802 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135802 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135802 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135802 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15283.367829 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15283.367829 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39493.906966 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39493.906966 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9342.075093 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9342.075093 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5078.054299 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5078.054299 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34542.633899 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34542.633899 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34542.633899 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34542.633899 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 26379 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 12882 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 156 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.921622 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 82.576923 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324541 # number of writebacks -system.cpu1.dcache.writebacks::total 324541 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171136 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171136 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394941 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1394941 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1433 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1433 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566077 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566077 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566077 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566077 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228180 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228180 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161595 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161595 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12518 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12518 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10611 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10611 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389775 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389775 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389775 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389775 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2858069500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2858069500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5115737712 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5115737712 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88636500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88636500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32718000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32718000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7973807212 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7973807212 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7973807212 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7973807212 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990097000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990097000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35704290190 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35704290190 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204694387190 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204694387190 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026206 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026206 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028373 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028373 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112170 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112170 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100593 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100593 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027062 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027062 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027062 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12525.503988 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12525.503988 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31657.772283 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31657.772283 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7080.723758 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7080.723758 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3083.404015 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3083.404015 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20457.461900 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20457.461900 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324632 # number of writebacks +system.cpu1.dcache.writebacks::total 324632 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171788 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171788 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1394549 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1394549 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1443 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1443 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566337 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566337 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566337 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566337 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161573 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161573 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12513 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12513 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10605 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10605 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389841 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389841 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389841 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389841 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2854852000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2854852000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5117226213 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5117226213 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89555500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89555500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32658000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32658000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7972078213 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7972078213 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7972078213 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7972078213 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989815500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989815500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35679552148 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35679552148 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204669367648 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204669367648 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026210 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026210 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112247 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112247 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100539 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100539 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027064 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027064 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027064 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12506.579985 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12506.579985 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31671.295408 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31671.295408 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7156.996723 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7156.996723 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3079.490806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3079.490806 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20449.563317 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20449.563317 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1804,18 +1804,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540179772418 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540179772418 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540179772418 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540179772418 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540125454155 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540125454155 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540125454155 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540125454155 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41712 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48865 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index dbb753c24..2b8b39c77 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -131,6 +133,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 97fb1321d..d0699dda9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.533112 # Number of seconds simulated -sim_ticks 2533112171000 # Number of ticks simulated -final_tick 2533112171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.533116 # Number of seconds simulated +sim_ticks 2533115780500 # Number of ticks simulated +final_tick 2533115780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62365 # Simulator instruction rate (inst/s) -host_op_rate 80247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2619544402 # Simulator tick rate (ticks/s) -host_mem_usage 400132 # Number of bytes of host memory used -host_seconds 967.00 # Real time elapsed on the host +host_inst_rate 64757 # Simulator instruction rate (inst/s) +host_op_rate 83325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2720016614 # Simulator tick rate (ticks/s) +host_mem_usage 398876 # Number of bytes of host memory used +host_seconds 931.29 # Real time elapsed on the host sim_insts 60307726 # Number of instructions simulated sim_ops 77599286 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093456 # Number of bytes read from this memory -system.physmem.bytes_read::total 129429648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory +system.physmem.bytes_read::total 129429776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796160 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796160 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3781760 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory +system.physmem.bytes_written::total 6797832 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096804 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12440 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096806 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59090 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47190040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1011 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813108 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314175 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51095111 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314175 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493031 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190659 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683690 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493031 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47190040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51095089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314301 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1492928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683585 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1492928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314175 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778801 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096804 # Total number of read requests seen -system.physmem.writeReqs 813112 # Total number of write requests seen -system.physmem.cpureqs 218338 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966195456 # Total number of bytes read from memory -system.physmem.bytesWritten 52039168 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129429648 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 314301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778674 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096806 # Total number of read requests seen +system.physmem.writeReqs 813108 # Total number of write requests seen +system.physmem.cpureqs 218339 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966195584 # Total number of bytes read from memory +system.physmem.bytesWritten 52038912 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129429776 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6797832 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 312 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943939 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943442 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943937 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 943392 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943979 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943150 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943973 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943153 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943272 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943215 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943605 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943692 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943794 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943286 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943217 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943610 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943691 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 942978 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943601 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50831 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943602 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50406 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51150 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50184 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50277 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51366 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50865 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51361 # Track writes on a per bank basis system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50795 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51181 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50711 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50625 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50798 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51185 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51244 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51225 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32505 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533111047500 # Total gap between requests +system.physmem.numWrRetry 32506 # Number of times wr buffer was full causing retry +system.physmem.totGap 2533114676500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154560 # Categorize read packet sizes +system.physmem.readPktSize::6 154562 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59094 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981079 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676469 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2688032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60687 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108699 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157561 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59090 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676222 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2687728 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108674 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157504 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16584 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 20063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 12693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 12694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 112 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see @@ -139,9 +139,9 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2576 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2659 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2706 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2730 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 2756 # What write queue length does an incoming req see @@ -151,10 +151,10 @@ system.physmem.wrQLenPdf::8 2829 # Wh system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see @@ -162,23 +162,23 @@ system.physmem.wrQLenPdf::19 35352 # Wh system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32694 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32647 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 32623 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 32597 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32571 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32548 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32524 # What write queue length does an incoming req see -system.physmem.totQLat 393223335500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485617965500 # Sum of mem lat for all requests -system.physmem.totBusLat 75482460000 # Total cycles spent in databus access -system.physmem.totBankLat 16912170000 # Total cycles spent in bank access -system.physmem.avgQLat 26047.33 # Average queueing delay per request -system.physmem.avgBankLat 1120.27 # Average bank access latency per request +system.physmem.totQLat 393224294250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485624283000 # Sum of mem lat for all requests +system.physmem.totBusLat 75482470000 # Total cycles spent in databus access +system.physmem.totBankLat 16917518750 # Total cycles spent in bank access +system.physmem.avgQLat 26047.39 # Average queueing delay per request +system.physmem.avgBankLat 1120.63 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32167.60 # Average memory access latency +system.physmem.avgMemAccLat 32168.02 # Average memory access latency system.physmem.avgRdBW 381.43 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.10 # Average consumed read bandwidth in MB/s @@ -186,12 +186,12 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time -system.physmem.avgWrQLen 11.09 # Average write queue length over time -system.physmem.readRowHits 15020204 # Number of row buffer hits during reads -system.physmem.writeRowHits 793057 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.11 # Average write queue length over time +system.physmem.readRowHits 15020181 # Number of row buffer hits during reads +system.physmem.writeRowHits 793022 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes -system.physmem.avgGap 159215.87 # Average gap between requests +system.physmem.avgGap 159216.11 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,38 +210,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14674954 # Number of BP lookups -system.cpu.branchPred.condPredicted 11760315 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703452 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9798337 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7946170 # Number of BTB hits +system.cpu.branchPred.lookups 14672817 # Number of BP lookups +system.cpu.branchPred.condPredicted 11756302 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704420 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9794195 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7944325 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.097129 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399969 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72392 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.112588 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1400354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72452 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51400725 # DTB read hits -system.cpu.dtb.read_misses 64230 # DTB read misses -system.cpu.dtb.write_hits 11699827 # DTB write hits -system.cpu.dtb.write_misses 15817 # DTB write misses +system.cpu.dtb.read_hits 51400888 # DTB read hits +system.cpu.dtb.read_misses 64225 # DTB read misses +system.cpu.dtb.write_hits 11700104 # DTB write hits +system.cpu.dtb.write_misses 15848 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3560 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2361 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 419 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2395 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 408 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1347 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51464955 # DTB read accesses -system.cpu.dtb.write_accesses 11715644 # DTB write accesses +system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51465113 # DTB read accesses +system.cpu.dtb.write_accesses 11715952 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63100552 # DTB hits -system.cpu.dtb.misses 80047 # DTB misses -system.cpu.dtb.accesses 63180599 # DTB accesses -system.cpu.itb.inst_hits 12329192 # ITB inst hits -system.cpu.itb.inst_misses 11376 # ITB inst misses +system.cpu.dtb.hits 63100992 # DTB hits +system.cpu.dtb.misses 80073 # DTB misses +system.cpu.dtb.accesses 63181065 # DTB accesses +system.cpu.itb.inst_hits 12331220 # ITB inst hits +system.cpu.itb.inst_misses 11422 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,148 +250,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2472 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2865 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2905 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12340568 # ITB inst accesses -system.cpu.itb.hits 12329192 # DTB hits -system.cpu.itb.misses 11376 # DTB misses -system.cpu.itb.accesses 12340568 # DTB accesses -system.cpu.numCycles 471811908 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12342642 # ITB inst accesses +system.cpu.itb.hits 12331220 # DTB hits +system.cpu.itb.misses 11422 # DTB misses +system.cpu.itb.accesses 12342642 # DTB accesses +system.cpu.numCycles 471822965 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30566850 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96025902 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14674954 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9346139 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21161280 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5294268 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122956 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95541161 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2622 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86967 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195337 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 356 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12325832 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900070 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5461 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151313220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785216 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150211 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30573370 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96017663 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14672817 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9344679 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21160566 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5295047 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 124247 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93127049 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86502 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2607471 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 357 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12327822 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900542 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5477 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151317698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785150 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150169 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130167339 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302330 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1712200 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496857 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2222542 1.47% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1109034 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2758411 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745566 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8798941 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130172761 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303441 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712324 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496425 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2221306 1.47% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109073 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2756927 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745885 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8799556 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151313220 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203526 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32523025 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95170118 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19191132 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962347 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3466598 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956722 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171732 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112651707 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566963 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3466598 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34464368 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36692438 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52511672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18154881 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6023263 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106120156 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20539 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 985607 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4064974 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 783 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110525870 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485527409 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485436293 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 91116 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 151317698 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203504 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32529947 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95168576 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19190992 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 961902 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3466281 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957763 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171745 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112647177 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568207 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3466281 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34471547 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36699353 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52502253 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18154395 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6023869 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106113727 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20537 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 985646 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066140 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 795 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110515015 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485506390 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485415520 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90870 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78390038 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32135831 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830318 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736784 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12149928 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20332565 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13516637 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977838 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2480356 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97929601 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124328965 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167666 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21748794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57017345 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501539 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151313220 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821666 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.535351 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32124976 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830416 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736951 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12148327 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20331207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13516553 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1968455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470685 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97921870 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983479 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124325634 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167955 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21739212 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56995294 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501084 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151317698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821620 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535306 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107094975 70.78% 70.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13518793 8.93% 79.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7075318 4.68% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5935233 3.92% 88.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12598116 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2801723 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1697051 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465636 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 126375 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107101494 70.78% 70.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13519014 8.93% 79.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7070833 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5935604 3.92% 88.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12601558 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2800079 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1698500 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 464413 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126203 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151313220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151317698 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62335 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8363613 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413579 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62151 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8366348 94.60% 95.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 415303 4.70% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58629316 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93112 0.07% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58625951 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93085 0.07% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued @@ -404,99 +404,99 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 17 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 4 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52921084 42.57% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12319626 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52921154 42.57% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319608 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124328965 # Type of FU issued -system.cpu.iq.rate 0.263514 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839530 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071098 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409034606 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121678500 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85964427 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23410 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12602 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10310 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132792371 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12458 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623186 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124325634 # Type of FU issued +system.cpu.iq.rate 0.263501 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8843805 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071134 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 409037091 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121660776 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85961644 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23336 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12538 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10309 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132793364 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12409 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623444 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4678002 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6260 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29908 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1784543 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4676644 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6237 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29883 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1784459 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107773 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 892534 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 892558 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3466598 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27942266 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 433430 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100134856 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201220 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20332565 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13516637 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410804 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113293 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3501 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29908 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350102 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268608 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618710 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121542985 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52087637 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2785980 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3466281 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27944782 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433344 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100126481 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 202692 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20331207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13516553 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410337 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113091 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3418 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29883 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269265 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619409 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121539796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52087723 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2785838 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221321 # number of nop insts executed -system.cpu.iew.exec_refs 64299335 # number of memory reference insts executed -system.cpu.iew.exec_branches 11558025 # Number of branches executed -system.cpu.iew.exec_stores 12211698 # Number of stores executed -system.cpu.iew.exec_rate 0.257609 # Inst execution rate -system.cpu.iew.wb_sent 120384508 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85974737 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47254500 # num instructions producing a value -system.cpu.iew.wb_consumers 88210457 # num instructions consuming a value +system.cpu.iew.exec_nop 221132 # number of nop insts executed +system.cpu.iew.exec_refs 64299655 # number of memory reference insts executed +system.cpu.iew.exec_branches 11557425 # Number of branches executed +system.cpu.iew.exec_stores 12211932 # Number of stores executed +system.cpu.iew.exec_rate 0.257596 # Inst execution rate +system.cpu.iew.wb_sent 120381824 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85971953 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47248258 # num instructions producing a value +system.cpu.iew.wb_consumers 88196266 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182222 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535702 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182212 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535717 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21478461 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21471534 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534359 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147846622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525881 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516310 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 535206 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147851417 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525864 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.516226 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120416670 81.45% 81.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13325889 9.01% 90.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3878179 2.62% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2122601 1.44% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1929203 1.30% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968068 0.65% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1602055 1.08% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 701521 0.47% 98.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2902436 1.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120424253 81.45% 81.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13319272 9.01% 90.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3880838 2.62% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2123082 1.44% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1929256 1.30% 95.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 967576 0.65% 96.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1605493 1.09% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701565 0.47% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2900082 1.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147846622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147851417 # Number of insts commited each cycle system.cpu.commit.committedInsts 60458107 # Number of instructions committed system.cpu.commit.committedOps 77749667 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -507,261 +507,261 @@ system.cpu.commit.branches 9961339 # Nu system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 68854898 # Number of committed integer instructions. system.cpu.commit.function_calls 991261 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2902436 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2900082 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242323721 # The number of ROB reads -system.cpu.rob.rob_writes 202019018 # The number of ROB writes -system.cpu.timesIdled 1771597 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320498688 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4594329392 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.rob.rob_reads 242323943 # The number of ROB reads +system.cpu.rob.rob_writes 202004834 # The number of ROB writes +system.cpu.timesIdled 1771447 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320505267 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4594325554 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60307726 # Number of Instructions Simulated system.cpu.committedOps 77599286 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 60307726 # Number of Instructions Simulated -system.cpu.cpi 7.823407 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823407 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127822 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.127822 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550308715 # number of integer regfile reads -system.cpu.int_regfile_writes 88462540 # number of integer regfile writes -system.cpu.fp_regfile_reads 8334 # number of floating regfile reads -system.cpu.fp_regfile_writes 2902 # number of floating regfile writes -system.cpu.misc_regfile_reads 30122249 # number of misc regfile reads +system.cpu.cpi 7.823591 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823591 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127819 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127819 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550297300 # number of integer regfile reads +system.cpu.int_regfile_writes 88455600 # number of integer regfile writes +system.cpu.fp_regfile_reads 8347 # number of floating regfile reads +system.cpu.fp_regfile_writes 2910 # number of floating regfile writes +system.cpu.misc_regfile_reads 30123534 # number of misc regfile reads system.cpu.misc_regfile_writes 831893 # number of misc regfile writes -system.cpu.icache.replacements 979554 # number of replacements -system.cpu.icache.tagsinuse 511.616693 # Cycle average of tags in use -system.cpu.icache.total_refs 11266265 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.495415 # Average number of references to valid blocks. +system.cpu.icache.replacements 979954 # number of replacements +system.cpu.icache.tagsinuse 511.616585 # Cycle average of tags in use +system.cpu.icache.total_refs 11267650 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980466 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.492137 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6410377000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.616693 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 511.616585 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999251 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999251 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11266265 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11266265 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11266265 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11266265 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11266265 # number of overall hits -system.cpu.icache.overall_hits::total 11266265 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059442 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059442 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059442 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059442 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059442 # number of overall misses -system.cpu.icache.overall_misses::total 1059442 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13996692496 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13996692496 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13996692496 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13996692496 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13996692496 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13996692496 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12325707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12325707 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12325707 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12325707 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12325707 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12325707 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085954 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085954 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085954 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085954 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085954 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085954 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13211.381554 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13211.381554 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13211.381554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13211.381554 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13211.381554 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5064 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11267650 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11267650 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11267650 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11267650 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11267650 # number of overall hits +system.cpu.icache.overall_hits::total 11267650 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060047 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060047 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060047 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060047 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060047 # number of overall misses +system.cpu.icache.overall_misses::total 1060047 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14006301995 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14006301995 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14006301995 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14006301995 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14006301995 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14006301995 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12327697 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12327697 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12327697 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12327697 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12327697 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12327697 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085989 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085989 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085989 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085989 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085989 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085989 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13212.906593 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13212.906593 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13212.906593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13212.906593 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13212.906593 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5383 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 802 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 290 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.050505 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.562069 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 802 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79338 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79338 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79338 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79338 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79338 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79338 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11377433497 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11377433497 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11377433497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11377433497 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11377433497 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11377433497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79541 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79541 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79541 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79541 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79541 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79541 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980506 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980506 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980506 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980506 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980506 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980506 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11382269996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11382269996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11382269996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11382269996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11382269996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11382269996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7555000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7555000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7555000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079517 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.079517 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079517 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.079517 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.394106 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.394106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.394106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.394106 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079537 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.079537 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.079537 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.079537 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.567409 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.567409 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.567409 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.567409 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64331 # number of replacements -system.cpu.l2cache.tagsinuse 51338.673427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1885045 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129724 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.531197 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2498168723000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36938.437105 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 26.056413 # Average occupied blocks per requestor +system.cpu.l2cache.replacements 64333 # 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Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 8154.357820 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6219.728923 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563637 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000409 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124427 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.094905 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783366 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52232 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10453 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 966649 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387163 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1416497 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607765 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607765 # number of Writeback hits +system.cpu.l2cache.occ_percent::cpu.inst 0.124426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.094906 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783377 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52369 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10535 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 967038 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387148 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1417090 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607758 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607758 # 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number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6133075770 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5080830 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002473267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007554097 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911803456 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26911803456 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002521767 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007602597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26911564456 # 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mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986486 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193914086223 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193919167053 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026734 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015970 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986500 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986500 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541208 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541208 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000765 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012580 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223364 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000765 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092632 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000782 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012581 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223367 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092632 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43959.059110 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46895.152675 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45343.511720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 43967.943105 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46382.308575 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45112.415348 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38172.208863 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59537.585366 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43959.059110 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38817.254560 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39227.919476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 43967.943105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38854.369098 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39263.244027 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643478 # number of replacements +system.cpu.dcache.replacements 643450 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21510687 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643990 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.402207 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21511687 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643962 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.405212 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42245000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13758124 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13758124 # 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number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104713593229 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104713593229 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 181601500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 181601500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 257000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 257000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114344199226 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114344199226 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114344199226 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114344199226 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14495401 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256458 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256458 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247617 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247617 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24717764 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24717764 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24717764 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24717764 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050863 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050863 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289887 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289887 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052871 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052871 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 24717465 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24717465 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24717465 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24717465 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050787 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050787 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289879 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289879 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052792 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052792 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149714 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149714 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149714 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13241.290587 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13241.290587 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35291.975855 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35291.975855 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13361.432893 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13361.432893 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149668 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149668 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149668 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149668 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13229.919338 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13229.919338 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35337.426328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35337.426328 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.213679 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.213679 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15117.647059 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15117.647059 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30898.785260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30898.785260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30898.785260 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 30275 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 18688 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2630 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 248 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.511407 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 75.354839 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30938.185392 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30938.185392 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30938.185392 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30435 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 19416 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2583 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 249 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.782811 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 77.975904 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607765 # number of writebacks -system.cpu.dcache.writebacks::total 607765 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351549 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351549 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714318 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714318 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1341 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065867 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065867 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065867 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065867 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385728 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385728 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249010 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249010 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12212 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12212 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607758 # number of writebacks +system.cpu.dcache.writebacks::total 607758 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350427 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350427 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714248 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714248 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064675 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064675 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064675 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064675 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385729 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385729 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4803158500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8205851415 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8205851415 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 142277500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 142277500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 223000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 223000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13004680415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13004680415 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13004680415 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13004680415 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395703000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395703000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727476899 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727476899 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219123179899 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219123179899 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026610 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024359 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047640 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047640 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13009009915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13009009915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13009009915 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13009009915 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395749000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395749000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36727240405 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36727240405 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219122989405 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219122989405 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026611 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026611 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024358 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047552 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047552 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025679 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025679 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025679 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12468.993695 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12468.993695 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32910.487189 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32910.487189 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11609.646250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11609.646250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12452.158121 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12452.158121 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32955.094216 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32955.094216 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11666.871669 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11666.871669 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13117.647059 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13117.647059 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20488.265103 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20488.265103 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20495.344343 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20495.344343 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,10 +1058,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229570022553 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229570022553 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229570022553 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229569916889 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229569916889 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229569916889 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 3a9f6f104..6dc26b748 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -92,6 +94,10 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_interval=100000000 +simpoint_profile=false +simpoint_profile_file=simpoint.bb.gz +simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false switched_out=false @@ -218,6 +224,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=true system=system tracer=system.cpu1.tracer @@ -333,6 +340,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 0638bf4e8..7f7ee8a99 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,167 +1,175 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401342 # Number of seconds simulated -sim_ticks 2401342096000 # Number of ticks simulated -final_tick 2401342096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401343 # Number of seconds simulated +sim_ticks 2401342505500 # Number of ticks simulated +final_tick 2401342505500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175097 # Simulator instruction rate (inst/s) -host_op_rate 224879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6969589731 # Simulator tick rate (ticks/s) -host_mem_usage 401152 # Number of bytes of host memory used -host_seconds 344.55 # Real time elapsed on the host -sim_insts 60328983 # Number of instructions simulated -sim_ops 77480984 # Number of ops (including micro ops) simulated +host_inst_rate 199955 # Simulator instruction rate (inst/s) +host_op_rate 256803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7959007704 # Simulator tick rate (ticks/s) +host_mem_usage 399904 # Number of bytes of host memory used +host_seconds 301.71 # Real time elapsed on the host +sim_insts 60329298 # Number of instructions simulated +sim_ops 77481139 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 503328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7112656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7093136 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 84416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 676928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 175488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1287544 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 503328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 84416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 175488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763232 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490172 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1326192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 84928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 676160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 175680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1309048 # Number of bytes read from this memory +system.physmem.bytes_read::total 124660776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 84928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 762720 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3745536 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490604 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1325756 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761352 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14067 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14048 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110864 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1319 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10577 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2742 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512399 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372543 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814542 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1327 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20467 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58524 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331439 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812478 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2961950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2953821 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 73079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 536177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51912667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 73079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317836 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560034 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620558 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552271 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815922 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814542 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 545132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51912951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209096 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35367 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73159 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1559768 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620738 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 552090 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815655 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1559768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3582508 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3574559 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 364954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 73079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1088448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54728589 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12617688 # Total number of read requests seen -system.physmem.writeReqs 398836 # Total number of write requests seen -system.physmem.cpureqs 54540 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807532032 # Total number of bytes read from memory -system.physmem.bytesWritten 25525504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102888120 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2640844 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 35367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 364636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1097221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54728606 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12618023 # Total number of read requests seen +system.physmem.writeReqs 398732 # Total number of write requests seen +system.physmem.cpureqs 54886 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807553472 # Total number of bytes read from memory +system.physmem.bytesWritten 25518848 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102909560 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2640668 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2353 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788745 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788844 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789174 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789012 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788870 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788937 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788603 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788021 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2360 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789126 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788779 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789028 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788935 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788618 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788026 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 788041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788285 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788254 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788096 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788287 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788712 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24959 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24829 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24777 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24647 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24874 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25287 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25154 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24830 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24779 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24767 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24961 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24885 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25219 # Track writes on a per bank basis +system.physmem.perBankRdReqs::11 788281 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788275 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788125 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788319 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788742 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24831 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24770 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25056 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24828 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24649 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 24783 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25151 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24834 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24883 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 25404 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24880 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25222 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14353 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400306886500 # Total gap between requests +system.physmem.numWrRetry 14347 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400307282000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 14 # Categorize read packet sizes system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34762 # Categorize read packet sizes +system.physmem.readPktSize::6 35097 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381411 # Categorize write packet sizes +system.physmem.writePktSize::2 381303 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17425 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 815618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 791939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998185 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260881 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261175 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249620 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6950 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6938 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17429 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 815886 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260870 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91397 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -177,356 +185,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14363 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14355 # What write queue length does an incoming req see -system.physmem.totQLat 277103451000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352917846000 # Sum of mem lat for all requests -system.physmem.totBusLat 63088440000 # Total cycles spent in databus access -system.physmem.totBankLat 12725955000 # Total cycles spent in bank access -system.physmem.avgQLat 21961.51 # Average queueing delay per request -system.physmem.avgBankLat 1008.58 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14349 # What write queue length does an incoming req see +system.physmem.totQLat 277119182500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 352940243750 # Sum of mem lat for all requests +system.physmem.totBusLat 63090115000 # Total cycles spent in databus access +system.physmem.totBankLat 12730946250 # Total cycles spent in bank access +system.physmem.avgQLat 21962.17 # Average queueing delay per request +system.physmem.avgBankLat 1008.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27970.09 # Average memory access latency -system.physmem.avgRdBW 336.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27971.12 # Average memory access latency +system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563138 # Number of row buffer hits during reads -system.physmem.writeRowHits 392488 # Number of row buffer hits during writes +system.physmem.readRowHits 12563435 # Number of row buffer hits during reads +system.physmem.writeRowHits 392399 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184404.60 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 63237 # number of replacements -system.l2c.tagsinuse 50354.010104 # Cycle average of tags in use -system.l2c.total_refs 1750448 # Total number of references to valid blocks. -system.l2c.sampled_refs 128633 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.608079 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374435270500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36848.768831 # Average occupied blocks per requestor +system.physmem.avgGap 184401.36 # Average gap between requests +system.l2c.replacements 63248 # number of replacements +system.l2c.tagsinuse 50357.471102 # Cycle average of tags in use +system.l2c.total_refs 1749120 # Total number of references to valid blocks. +system.l2c.sampled_refs 128641 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.596909 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374433885500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36827.136068 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5153.236731 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3773.370268 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5149.319270 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3787.835363 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 798.048897 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 747.701698 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 4.908414 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.itb.walker 0.004219 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1438.199404 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1588.778182 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562268 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu1.inst 800.097709 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 742.779862 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 5.892734 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1445.756642 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1597.659994 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.561938 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078632 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057577 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078572 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057798 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.012177 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.021945 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024243 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768341 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.012209 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011334 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000090 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.022060 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024378 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768394 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 8872 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3222 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 463260 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169090 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 463074 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169165 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 2536 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 132093 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65269 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18228 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4214 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 284683 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 139174 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291733 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597885 # number of Writeback hits -system.l2c.Writeback_hits::total 597885 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 132302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18053 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 283993 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 138836 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290665 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597754 # number of Writeback hits +system.l2c.Writeback_hits::total 597754 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 13 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 104667.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51137.767577 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41759.345527 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40163.838908 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -698,34 +656,34 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8063471 # 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Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8069688 # DTB read accesses -system.cpu0.dtb.write_accesses 6639352 # DTB write accesses +system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8070956 # DTB read accesses +system.cpu0.dtb.write_accesses 6629101 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14700784 # DTB hits -system.cpu0.dtb.misses 8256 # DTB misses -system.cpu0.dtb.accesses 14709040 # DTB accesses -system.cpu0.itb.inst_hits 32681637 # ITB inst hits -system.cpu0.itb.inst_misses 3491 # ITB inst misses +system.cpu0.dtb.hits 14691802 # DTB hits +system.cpu0.dtb.misses 8255 # DTB misses +system.cpu0.dtb.accesses 14700057 # DTB accesses +system.cpu0.itb.inst_hits 32689341 # ITB inst hits +system.cpu0.itb.inst_misses 3490 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 691 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 690 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2596 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -734,400 +692,400 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # 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number of times the integer registers were read +system.cpu0.num_int_register_writes 39627279 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3662 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15365306 # number of memory refs -system.cpu0.num_load_insts 8431456 # Number of load instructions -system.cpu0.num_store_insts 6933850 # Number of store instructions -system.cpu0.num_idle_cycles 13419590967.275719 # Number of idle cycles -system.cpu0.num_busy_cycles -13305580813.275719 # Number of busy cycles -system.cpu0.not_idle_fraction -116.705226 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.705226 # Percentage of idle cycles +system.cpu0.num_mem_refs 15356244 # number of memory refs +system.cpu0.num_load_insts 8432602 # Number of load instructions +system.cpu0.num_store_insts 6923642 # Number of store instructions +system.cpu0.num_idle_cycles 13418877123.276752 # Number of idle cycles +system.cpu0.num_busy_cycles -13304873074.276752 # Number of busy cycles +system.cpu0.not_idle_fraction -116.705268 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.705268 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892475 # number of replacements -system.cpu0.icache.tagsinuse 511.602627 # Cycle average of tags in use -system.cpu0.icache.total_refs 44228984 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892987 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.529259 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8120621000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.244790 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.725575 # 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average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11796.369343 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11695.632508 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11478.703988 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11796.369343 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11695.632508 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11478.703988 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11796.369343 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11695.632508 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23939 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23939 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23939 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23939 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23939 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23939 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 133904 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287171 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 421075 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 133904 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287171 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 421075 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 133904 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287171 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 421075 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1537176500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3381635486 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4918811986 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1537176500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3381635486 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4918811986 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1537176500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3381635486 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4918811986 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015979 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070653 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009329 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015979 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070653 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009329 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015979 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070653 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009329 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11479.690674 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11775.685867 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11681.557884 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11479.690674 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11775.685867 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11681.557884 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11479.690674 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11775.685867 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11681.557884 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 630091 # number of replacements +system.cpu0.dcache.replacements 629954 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23225610 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630603 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.830795 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23213851 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630466 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.820147 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.760102 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.700202 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.536812 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968281 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.018946 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012767 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.756165 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.709007 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.531944 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968274 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.018963 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012758 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6944978 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1884503 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4480327 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13309808 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5958718 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1341197 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2127096 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9427011 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131371 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33990 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73049 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238410 # number of LoadLockedReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6946152 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1881152 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4479308 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13306612 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5948925 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1341191 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2128617 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9418733 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131368 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34012 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72748 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238128 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137743 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35715 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73934 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12903696 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3225700 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6607423 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22736819 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12903696 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3225700 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6607423 # number of overall hits -system.cpu0.dcache.overall_hits::total 22736819 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169098 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 64736 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 284633 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 518467 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167836 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29507 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 592008 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 789351 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6372 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35737 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73913 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12895077 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3222343 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6607925 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22725345 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12895077 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3222343 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6607925 # number of overall hits +system.cpu0.dcache.overall_hits::total 22725345 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169178 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 64842 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 284494 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 518514 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167271 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29535 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 600821 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 797627 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6375 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1725 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3872 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11969 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 336934 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94243 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 876641 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1307818 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 336934 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94243 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 876641 # number of overall misses -system.cpu0.dcache.overall_misses::total 1307818 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 902119000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4115909000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5018028000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 726856500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18065670403 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 18792526903 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3870 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11970 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336449 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94377 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 885315 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1316141 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336449 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 94377 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 885315 # number of overall misses +system.cpu0.dcache.overall_misses::total 1316141 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 903782500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4105019000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5008801500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 727658500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18527388398 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19255046898 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22582000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52183000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74765000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 77000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 77000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1628975500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22181579403 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 23810554903 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1628975500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22181579403 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 23810554903 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7114076 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1949239 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4764960 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13828275 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6126554 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1370704 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2719104 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52040000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74622000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 52000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 52000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1631441000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22632407398 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24263848398 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1631441000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22632407398 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24263848398 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7115330 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1945994 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4763802 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13825126 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6116196 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1370726 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2729438 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216360 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137743 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35715 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76921 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250379 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35737 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76618 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250098 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137743 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35715 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73939 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35737 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73917 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13240630 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3319943 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7484064 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24044637 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13240630 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3319943 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7484064 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24044637 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023769 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033211 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059735 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037493 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027395 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021527 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217722 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077263 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046260 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048299 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050337 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047804 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000068 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000020 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025447 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028387 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117134 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054391 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025447 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028387 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.117134 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054391 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13935.352818 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14460.406910 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9678.587065 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24633.358186 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30515.922763 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23807.567106 # average WriteReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13231526 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3316720 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7493240 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24041486 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13231526 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3316720 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7493240 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24041486 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023777 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033321 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059720 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037505 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027349 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021547 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220126 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078074 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046282 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048269 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050510 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047861 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025428 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028455 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118148 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054745 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025428 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028455 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118148 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054745 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13938.226767 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14429.193586 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9659.915644 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24637.159303 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30836.785662 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24140.415129 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.014493 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13477.014463 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6246.553597 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15400 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15400 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17284.843437 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25302.922637 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18206.321448 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17284.843437 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25302.922637 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18206.321448 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8914 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 958 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1123 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 47 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.937667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.382979 # average number of cycles each access was blocked +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13447.028424 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6234.085213 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17286.425718 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25564.242555 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18435.599528 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17286.425718 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25564.242555 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18435.599528 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10180 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1987 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1115 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 42 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.130045 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 47.309524 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597885 # number of writebacks -system.cpu0.dcache.writebacks::total 597885 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146334 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146334 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539505 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 539505 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 408 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 408 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 685839 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 685839 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 685839 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 685839 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64736 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138299 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 203035 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29507 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52503 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82010 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 597754 # number of writebacks +system.cpu0.dcache.writebacks::total 597754 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146487 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146487 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547791 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 547791 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 426 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 426 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 694278 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 694278 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 694278 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 694278 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64842 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138007 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202849 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29535 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53030 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82565 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1725 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3464 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5189 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94243 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 190802 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 285045 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 94243 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 190802 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 285045 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 772647000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1796404500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2569051500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 667842500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1409486493 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2077328993 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3444 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5169 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94377 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 191037 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285414 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94377 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 191037 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285414 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 774098500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1795767000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2569865500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 668588500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1433658493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102246993 # number of WriteReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19132000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40548500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59680500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 67000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440489500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3205890993 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4646380493 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440489500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3205890993 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4646380493 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592646000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28973998000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56566644000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1275946000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147122763 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423068763 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28868592000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43121120763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71989712763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033211 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029024 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014683 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021527 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019309 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008027 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048299 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020725 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000068 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000020 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028387 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025494 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011855 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028387 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025494 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011855 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11935.352818 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12989.280472 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12653.244514 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22633.358186 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26845.827724 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25330.191355 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40258500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59390500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442687000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3229425493 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4672112493 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442687000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3229425493 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4672112493 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27590939000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28973644000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56564583000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276412500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14137928134 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15414340634 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28867351500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43111572134 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71978923634 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033321 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028970 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014672 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021547 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019429 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008082 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048269 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044950 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020668 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011872 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028455 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025495 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011872 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.226767 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13012.144312 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12668.859595 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22637.159303 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27034.857496 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25461.720983 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.014493 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11705.687067 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11501.349008 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15284.843437 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16802.187571 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16300.515683 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15284.843437 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16802.187571 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16300.515683 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11689.459930 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11489.746566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15286.425718 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16904.712140 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16369.598173 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1140,10 +1098,10 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2164639 # DTB read hits -system.cpu1.dtb.read_misses 2112 # DTB read misses -system.cpu1.dtb.write_hits 1457171 # DTB write hits -system.cpu1.dtb.write_misses 388 # DTB write misses +system.cpu1.dtb.read_hits 2161402 # DTB read hits +system.cpu1.dtb.read_misses 2114 # DTB read misses +system.cpu1.dtb.write_hits 1457218 # DTB write hits +system.cpu1.dtb.write_misses 386 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 237 # Number of times TLB was flushed by MVA & ASID @@ -1153,13 +1111,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2166751 # DTB read accesses -system.cpu1.dtb.write_accesses 1457559 # DTB write accesses +system.cpu1.dtb.read_accesses 2163516 # DTB read accesses +system.cpu1.dtb.write_accesses 1457604 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3621810 # DTB hits +system.cpu1.dtb.hits 3618620 # DTB hits system.cpu1.dtb.misses 2500 # DTB misses -system.cpu1.dtb.accesses 3624310 # DTB accesses -system.cpu1.itb.inst_hits 8394434 # ITB inst hits +system.cpu1.dtb.accesses 3621120 # DTB accesses +system.cpu1.itb.inst_hits 8380082 # ITB inst hits system.cpu1.itb.inst_misses 1132 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1176,352 +1134,352 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8395566 # ITB inst accesses -system.cpu1.itb.hits 8394434 # DTB hits +system.cpu1.itb.inst_accesses 8381214 # ITB inst accesses +system.cpu1.itb.hits 8380082 # DTB hits system.cpu1.itb.misses 1132 # DTB misses -system.cpu1.itb.accesses 8395566 # DTB accesses -system.cpu1.numCycles 574616929 # number of cpu cycles simulated +system.cpu1.itb.accesses 8381214 # DTB accesses +system.cpu1.numCycles 574618954 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8189721 # Number of instructions committed -system.cpu1.committedOps 10425154 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9334484 # Number of integer alu accesses +system.cpu1.committedInsts 8175033 # Number of instructions committed +system.cpu1.committedOps 10410069 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9322021 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 315358 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1143455 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9334484 # number of integer instructions +system.cpu1.num_func_calls 315375 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1140852 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9322021 # number of integer instructions system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 53815468 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10115295 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53738545 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10097471 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3794179 # number of memory refs -system.cpu1.num_load_insts 2259735 # Number of load instructions -system.cpu1.num_store_insts 1534444 # Number of store instructions -system.cpu1.num_idle_cycles 532869113.789336 # Number of idle cycles -system.cpu1.num_busy_cycles 41747815.210664 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072653 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927347 # Percentage of idle cycles +system.cpu1.num_mem_refs 3791152 # number of memory refs +system.cpu1.num_load_insts 2256757 # Number of load instructions +system.cpu1.num_store_insts 1534395 # Number of store instructions +system.cpu1.num_idle_cycles 532868716.793879 # Number of idle cycles +system.cpu1.num_busy_cycles 41750237.206121 # Number of busy cycles +system.cpu1.not_idle_fraction 0.072657 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.927343 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4726542 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3843019 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222839 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 2968663 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2529901 # Number of BTB hits +system.cpu2.branchPred.lookups 4722397 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3838487 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221435 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 2952816 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2527233 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 85.220215 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412372 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21902 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.587216 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 411089 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21408 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10882413 # DTB read hits -system.cpu2.dtb.read_misses 22825 # DTB read misses -system.cpu2.dtb.write_hits 3267303 # DTB write hits -system.cpu2.dtb.write_misses 5867 # DTB write misses +system.cpu2.dtb.read_hits 10881575 # DTB read hits +system.cpu2.dtb.read_misses 22640 # DTB read misses +system.cpu2.dtb.write_hits 3277177 # DTB write hits +system.cpu2.dtb.write_misses 5849 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2312 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 661 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 167 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2319 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 814 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 160 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 479 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10905238 # DTB read accesses -system.cpu2.dtb.write_accesses 3273170 # DTB write accesses +system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10904215 # DTB read accesses +system.cpu2.dtb.write_accesses 3283026 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14149716 # DTB hits -system.cpu2.dtb.misses 28692 # DTB misses -system.cpu2.dtb.accesses 14178408 # DTB accesses -system.cpu2.itb.inst_hits 4068625 # ITB inst hits -system.cpu2.itb.inst_misses 4512 # ITB inst misses +system.cpu2.dtb.hits 14158752 # DTB hits +system.cpu2.dtb.misses 28489 # DTB misses +system.cpu2.dtb.accesses 14187241 # DTB accesses +system.cpu2.itb.inst_hits 4065885 # ITB inst hits +system.cpu2.itb.inst_misses 4502 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 512 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1570 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1019 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1005 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4073137 # ITB inst accesses -system.cpu2.itb.hits 4068625 # DTB hits -system.cpu2.itb.misses 4512 # DTB misses -system.cpu2.itb.accesses 4073137 # DTB accesses -system.cpu2.numCycles 88262186 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4070387 # ITB inst accesses +system.cpu2.itb.hits 4065885 # DTB hits +system.cpu2.itb.misses 4502 # DTB misses +system.cpu2.itb.accesses 4070387 # DTB accesses +system.cpu2.numCycles 88259873 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9466966 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32442756 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4726542 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2942273 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6836207 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1818602 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 52204 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19340391 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 1503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 949 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33911 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57026 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 350 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4067278 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 310494 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1937 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37038296 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050561 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436650 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9453176 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32426467 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4722397 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2938322 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6835194 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1814499 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51467 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18689225 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 182 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 953 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32914 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 708494 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 306 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4064555 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 309850 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1926 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37018169 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050897 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436881 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30207118 81.56% 81.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383553 1.04% 82.59% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 510773 1.38% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 813677 2.20% 86.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 655447 1.77% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344842 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1012614 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 239002 0.65% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2871270 7.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30188064 81.55% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383346 1.04% 82.58% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 510640 1.38% 83.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 813031 2.20% 86.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 657801 1.78% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 343878 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1012409 2.73% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 238466 0.64% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2870534 7.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37038296 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053551 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367573 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10082561 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19277386 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6185445 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 295546 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1196299 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 612714 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53722 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36760071 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 181639 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1196299 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10657194 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6561283 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11169878 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5886650 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1565975 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34511546 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 423021 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 879548 # Number of times rename has blocked due to LSQ full +system.cpu2.fetch.rateDist::total 37018169 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053506 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367398 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10067654 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19275483 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6184949 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 295259 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1193811 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 613325 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53657 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36756215 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 182103 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1193811 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10642239 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6572797 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11156885 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5885889 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1565553 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34514239 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2456 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 419835 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 882809 # Number of times rename has blocked due to LSQ full system.cpu2.rename.FullRegisterEvents 92 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37019837 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157748297 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157720764 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27533 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25797181 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11222655 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231296 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207724 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3360285 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6539665 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3841357 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 538392 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 797336 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31744288 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511908 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34279119 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54882 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7417436 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19927896 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155705 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37038296 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925505 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580259 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 37003284 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157776579 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157748805 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27774 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25809996 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11193287 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 230807 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207161 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3357083 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6535673 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3850744 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 536963 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 792176 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31747463 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511528 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34289699 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55083 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7395646 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19879544 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155324 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37018169 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.926294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.580927 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24460082 66.04% 66.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3918248 10.58% 76.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2351220 6.35% 82.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1973788 5.33% 88.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2795799 7.55% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 886051 2.39% 98.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 483364 1.31% 99.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 134520 0.36% 99.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35224 0.10% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24442328 66.03% 66.03% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3909913 10.56% 76.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2354045 6.36% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974122 5.33% 88.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2799200 7.56% 95.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 884316 2.39% 98.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 484064 1.31% 99.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 134882 0.36% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35299 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37038296 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37018169 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18440 1.20% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.20% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407717 91.67% 92.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109411 7.13% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18550 1.21% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1408407 91.61% 92.81% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110486 7.19% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61375 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19374131 56.52% 56.70% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25889 0.08% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.77% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11382838 33.21% 89.98% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3434489 10.02% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61448 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19376629 56.51% 56.69% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 26012 0.08% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 381 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11380471 33.19% 89.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3444734 10.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34279119 # Type of FU issued -system.cpu2.iq.rate 0.388378 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1535568 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044796 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107208634 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39678959 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27407916 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6919 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3775 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3148 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35749638 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3674 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207865 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34289699 # Type of FU issued +system.cpu2.iq.rate 0.388508 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537443 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044837 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107211457 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39659859 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27420215 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6989 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3825 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3150 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35761973 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3721 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 208327 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1585739 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1960 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9442 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 583385 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1579914 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1893 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9373 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 582518 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5362930 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352406 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5363105 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352533 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1196299 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4872349 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91583 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32337356 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60924 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6539665 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3841357 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369639 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31243 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2490 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9442 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 106503 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88749 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195252 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33287010 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11093708 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 992109 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1193811 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4877812 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91796 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32340028 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60265 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6535673 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3850744 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 369403 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31610 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2472 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9373 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105135 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88586 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193721 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33297921 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11093060 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 991778 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 81160 # number of nop insts executed -system.cpu2.iew.exec_refs 14495137 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3696488 # Number of branches executed -system.cpu2.iew.exec_stores 3401429 # Number of stores executed -system.cpu2.iew.exec_rate 0.377138 # Inst execution rate -system.cpu2.iew.wb_sent 32866107 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27411064 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15680721 # num instructions producing a value -system.cpu2.iew.wb_consumers 28515439 # num instructions consuming a value +system.cpu2.iew.exec_nop 81037 # number of nop insts executed +system.cpu2.iew.exec_refs 14504508 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3695173 # Number of branches executed +system.cpu2.iew.exec_stores 3411448 # Number of stores executed +system.cpu2.iew.exec_rate 0.377271 # Inst execution rate +system.cpu2.iew.wb_sent 32878469 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27423365 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15687848 # num instructions producing a value +system.cpu2.iew.wb_consumers 28539684 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310564 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549903 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.310712 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549685 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7354772 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356203 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 169868 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35841861 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.689480 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.717059 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7335381 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356204 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168508 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35824220 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.690433 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.719118 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27192796 75.87% 75.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4189244 11.69% 87.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258322 3.51% 91.07% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 656013 1.83% 92.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 572033 1.60% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 315336 0.88% 95.37% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 400135 1.12% 96.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 291160 0.81% 97.30% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 966822 2.70% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27176930 75.86% 75.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4185525 11.68% 87.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1261410 3.52% 91.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 649563 1.81% 92.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 571804 1.60% 94.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 316250 0.88% 95.36% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 400543 1.12% 96.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 292091 0.82% 97.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 970104 2.71% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35841861 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20002488 # Number of instructions committed -system.cpu2.commit.committedOps 24712245 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35824220 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20010366 # Number of instructions committed +system.cpu2.commit.committedOps 24734227 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8211898 # Number of memory references committed -system.cpu2.commit.loads 4953926 # Number of loads committed -system.cpu2.commit.membars 94216 # Number of memory barriers committed -system.cpu2.commit.branches 3168186 # Number of branches committed +system.cpu2.commit.refs 8223985 # Number of memory references committed +system.cpu2.commit.loads 4955759 # Number of loads committed +system.cpu2.commit.membars 94186 # Number of memory barriers committed +system.cpu2.commit.branches 3169280 # Number of branches committed system.cpu2.commit.fp_insts 3103 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21932897 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294982 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 966822 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 21954082 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294910 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 970104 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66417184 # The number of ROB reads -system.cpu2.rob.rob_writes 65371468 # The number of ROB writes -system.cpu2.timesIdled 360346 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51223890 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567293863 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19948231 # Number of Instructions Simulated -system.cpu2.committedOps 24657988 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19948231 # Number of Instructions Simulated -system.cpu2.cpi 4.424562 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.424562 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.226011 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.226011 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153801675 # number of integer regfile reads -system.cpu2.int_regfile_writes 29257373 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22358 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9025255 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240725 # number of misc regfile writes +system.cpu2.rob.rob_reads 66398809 # The number of ROB reads +system.cpu2.rob.rob_writes 65374131 # The number of ROB writes +system.cpu2.timesIdled 360148 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51241704 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567295976 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19956402 # Number of Instructions Simulated +system.cpu2.committedOps 24680263 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19956402 # Number of Instructions Simulated +system.cpu2.cpi 4.422635 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.422635 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.226110 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.226110 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153855471 # number of integer regfile reads +system.cpu2.int_regfile_writes 29258344 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22383 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20838 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9035132 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240694 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1536,10 +1494,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981026264436 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981026264436 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981026264436 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981026264436 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981038235668 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981038235668 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981038235668 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981038235668 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index e2c3921ac..4b0166894 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -131,6 +133,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned @@ -589,6 +592,7 @@ renameToFetchDelay=1 renameToIEWDelay=2 renameToROBDelay=1 renameWidth=8 +simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread smtIQPolicy=Partitioned diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 83e83b33f..8bb759cd2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,147 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.543301 # Number of seconds simulated -sim_ticks 2543301032500 # Number of ticks simulated -final_tick 2543301032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.543311 # Number of seconds simulated +sim_ticks 2543310963000 # Number of ticks simulated +final_tick 2543310963000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74756 # Simulator instruction rate (inst/s) -host_op_rate 96190 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3152487696 # Simulator tick rate (ticks/s) -host_mem_usage 404224 # Number of bytes of host memory used -host_seconds 806.76 # Real time elapsed on the host -sim_insts 60309843 # Number of instructions simulated -sim_ops 77602131 # Number of ops (including micro ops) simulated +host_inst_rate 64896 # Simulator instruction rate (inst/s) +host_op_rate 83503 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2736674491 # Simulator tick rate (ticks/s) +host_mem_usage 401948 # Number of bytes of host memory used +host_seconds 929.34 # Real time elapsed on the host +sim_insts 60310426 # Number of instructions simulated +sim_ops 77602848 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 508544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4232464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 292032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4862300 # Number of bytes read from this memory -system.physmem.bytes_read::total 131009324 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 508544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 292032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3788480 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1346148 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1669964 # Number of bytes written to this memory -system.physmem.bytes_written::total 6804592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 505600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4226512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 293504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4868124 # Number of bytes read from this memory +system.physmem.bytes_read::total 131007148 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 505600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 293504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1344512 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1671600 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802416 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7946 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 66166 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4563 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 75980 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293525 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59195 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336537 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813223 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47619423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 805 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7900 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66073 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4586 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 76071 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293491 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59161 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336128 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417900 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813189 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47619237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 199954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1664162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1911807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51511529 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 199954 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314778 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489592 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 656613 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2675496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47619423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 198796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1661815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 115402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1914089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51510472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 198796 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 115402 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314198 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1488730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 528646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2674630 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1488730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47619237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 199954 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2193453 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2568420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54187025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293525 # Total number of read requests seen -system.physmem.writeReqs 813223 # Total number of write requests seen -system.physmem.cpureqs 218526 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978785600 # Total number of bytes read from memory -system.physmem.bytesWritten 52046272 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131009324 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6804592 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4665 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955677 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956490 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956276 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955444 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955565 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956160 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955611 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955315 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955980 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50418 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50434 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50916 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50863 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51375 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51196 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50726 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.inst 198796 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2190461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 115402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2571343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54185102 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293491 # Total number of read requests seen +system.physmem.writeReqs 813189 # Total number of write requests seen +system.physmem.cpureqs 218466 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978783424 # Total number of bytes read from memory +system.physmem.bytesWritten 52044096 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131007148 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6802416 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 14 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4673 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955732 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956264 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955447 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955562 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956165 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956089 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955603 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956033 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955432 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955985 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50834 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50412 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51163 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50191 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50901 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50804 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50730 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50631 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32474 # Number of times wr buffer was full causing retry -system.physmem.totGap 2543299855000 # Total gap between requests +system.physmem.numWrRetry 32475 # Number of times wr buffer was full causing retry +system.physmem.totGap 2543309787500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154666 # Categorize read packet sizes +system.physmem.readPktSize::6 154632 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59195 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3605146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 59953 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10676 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59161 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054822 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991773 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961430 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3605165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 59966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110015 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160547 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109964 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9914 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see @@ -156,290 +168,282 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2745 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2865 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35305 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32504 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32487 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see -system.physmem.totQLat 346872048750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 440039818750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467570000 # Total cycles spent in databus access -system.physmem.totBankLat 16700200000 # Total cycles spent in bank access -system.physmem.avgQLat 22680.99 # Average queueing delay per request -system.physmem.avgBankLat 1091.98 # Average bank access latency per request +system.physmem.totQLat 346644691750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439813624250 # Sum of mem lat for all requests +system.physmem.totBusLat 76467385000 # Total cycles spent in databus access +system.physmem.totBankLat 16701547500 # Total cycles spent in bank access +system.physmem.avgQLat 22666.18 # Average queueing delay per request +system.physmem.avgBankLat 1092.07 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28772.97 # Average memory access latency +system.physmem.avgMemAccLat 28758.25 # Average memory access latency system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218379 # Number of row buffer hits during reads -system.physmem.writeRowHits 794608 # Number of row buffer hits during writes +system.physmem.readRowHits 15218324 # Number of row buffer hits during reads +system.physmem.writeRowHits 794497 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.71 # Row buffer hit rate for writes -system.physmem.avgGap 157902.75 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64434 # number of replacements -system.l2c.tagsinuse 51415.067512 # Cycle average of tags in use -system.l2c.total_refs 1904100 # Total number of references to valid blocks. -system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.666441 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2506327384000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36945.837156 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 20.213783 # Average occupied blocks per requestor +system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes +system.physmem.avgGap 157904.04 # Average gap between requests +system.l2c.replacements 64400 # number of replacements +system.l2c.tagsinuse 51409.834545 # Cycle average of tags in use +system.l2c.total_refs 1903586 # Total number of references to valid blocks. +system.l2c.sampled_refs 129789 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.666775 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2531435998500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36958.443874 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 20.878124 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000349 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5214.159096 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3260.668190 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 16.334221 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2999.640373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2958.214345 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563749 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000308 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5181.005742 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3269.589268 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 7.697989 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3013.641151 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2958.578047 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563941 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000319 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.079562 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.049754 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.045771 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.045139 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784532 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 32674 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 7484 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 493926 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 214255 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30206 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6691 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 477455 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 172903 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435594 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 607840 # number of Writeback hits -system.l2c.Writeback_hits::total 607840 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 18 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.occ_percent::cpu0.inst 0.079056 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.049890 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.045985 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.045144 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784452 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32561 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 7200 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 489769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 212787 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30618 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 481086 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 174591 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1435318 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 608032 # number of Writeback hits +system.l2c.Writeback_hits::total 608032 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 20 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 57831 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55019 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112850 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 32674 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 7484 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 493926 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 272086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30206 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6691 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 477455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 227922 # number of demand (read+write) hits -system.l2c.demand_hits::total 1548444 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 32674 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 7484 # number of overall hits -system.l2c.overall_hits::cpu0.inst 493926 # number of overall hits -system.l2c.overall_hits::cpu0.data 272086 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30206 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6691 # number of overall hits -system.l2c.overall_hits::cpu1.inst 477455 # number of overall hits -system.l2c.overall_hits::cpu1.data 227922 # number of overall hits -system.l2c.overall_hits::total 1548444 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 32 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 57883 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 54957 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112840 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32561 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 7200 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 489769 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 270670 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30618 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6706 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 481086 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 229548 # number of demand (read+write) hits +system.l2c.demand_hits::total 1548158 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32561 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 7200 # number of overall hits +system.l2c.overall_hits::cpu0.inst 489769 # number of overall hits +system.l2c.overall_hits::cpu0.data 270670 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30618 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6706 # number of overall hits +system.l2c.overall_hits::cpu1.inst 481086 # number of overall hits +system.l2c.overall_hits::cpu1.data 229548 # number of overall hits +system.l2c.overall_hits::total 1548158 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 33 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6093 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 20 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015836 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988462 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989862 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.989119 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.513547 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567355 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541357 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000978 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000267 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015599 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.197809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000662 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.251909 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.091683 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000978 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000267 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015599 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.197809 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000662 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.251909 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.091683 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 94680563887 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 96027977321 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 190713593538 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.027637 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025723 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015819 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.987171 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990580 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988772 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.200000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.090909 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.512929 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567979 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541390 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.198407 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.250831 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091686 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001012 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015638 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.198407 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000326 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009442 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.250831 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091686 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45270.066766 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45381.291618 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46182.170647 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44780.273841 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46521.165293 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44712.359629 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39776.667972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37204.758462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38383.571238 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average overall mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39988.226573 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37119.935476 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38432.465895 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40272.034142 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37743.478047 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39328.980007 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62932.787879 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40272.034142 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 43001.703766 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40475.095470 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37743.478047 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39328.980007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44757.096380 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37683.798886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39359.547770 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -622,38 +634,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7635591 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6085397 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 382495 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4962348 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4056906 # Number of BTB hits +system.cpu0.branchPred.lookups 7600384 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6061207 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379102 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4941026 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4041960 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.753759 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 731596 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39324 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.804063 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 728879 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39033 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26057064 # DTB read hits -system.cpu0.dtb.read_misses 40223 # DTB read misses -system.cpu0.dtb.write_hits 5918699 # DTB write hits -system.cpu0.dtb.write_misses 9531 # DTB write misses +system.cpu0.dtb.read_hits 26040938 # DTB read hits +system.cpu0.dtb.read_misses 40555 # DTB read misses +system.cpu0.dtb.write_hits 5901951 # DTB write hits +system.cpu0.dtb.write_misses 9434 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1419 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5623 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1361 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 276 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26097287 # DTB read accesses -system.cpu0.dtb.write_accesses 5928230 # DTB write accesses +system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26081493 # DTB read accesses +system.cpu0.dtb.write_accesses 5911385 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31975763 # DTB hits -system.cpu0.dtb.misses 49754 # DTB misses -system.cpu0.dtb.accesses 32025517 # DTB accesses -system.cpu0.itb.inst_hits 6123062 # ITB inst hits -system.cpu0.itb.inst_misses 7629 # ITB inst misses +system.cpu0.dtb.hits 31942889 # DTB hits +system.cpu0.dtb.misses 49989 # DTB misses +system.cpu0.dtb.accesses 31992878 # DTB accesses +system.cpu0.itb.inst_hits 6096045 # ITB inst hits +system.cpu0.itb.inst_misses 7428 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -662,114 +674,114 @@ system.cpu0.itb.flush_tlb 257 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1589 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1569 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6130691 # ITB inst accesses -system.cpu0.itb.hits 6123062 # DTB hits -system.cpu0.itb.misses 7629 # DTB misses -system.cpu0.itb.accesses 6130691 # DTB accesses -system.cpu0.numCycles 239038664 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6103473 # ITB inst accesses +system.cpu0.itb.hits 6096045 # DTB hits +system.cpu0.itb.misses 7428 # DTB misses +system.cpu0.itb.accesses 6103473 # DTB accesses +system.cpu0.numCycles 239139269 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15574951 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47914738 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7635591 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4788502 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10629711 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2569699 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 94247 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49519281 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1748 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2018 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 51773 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101169 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6121027 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 398928 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3254 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77753565 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.762466 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119834 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15469651 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47735703 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7600384 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4770839 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10588915 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2554228 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 92050 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 48266741 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1619 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2012 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51922 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1409369 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 188 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6094028 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 397204 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3100 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77649364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.760813 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.117939 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67131545 86.34% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 691431 0.89% 87.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 886662 1.14% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1230744 1.58% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1150970 1.48% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576090 0.74% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1323248 1.70% 93.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 399344 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4363531 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67068023 86.37% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 685973 0.88% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 883508 1.14% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1225779 1.58% 89.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1145464 1.48% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 573659 0.74% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1320882 1.70% 93.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397746 0.51% 94.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4348330 5.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77753565 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031943 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.200448 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16625563 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49255605 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9626158 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 554470 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1689651 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1030343 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91400 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56424531 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 305535 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1689651 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17561755 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18982691 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27011773 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9171817 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3333839 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53601005 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13486 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 625862 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2162558 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 496 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55732914 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 244003598 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243955563 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48035 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40460066 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15272848 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429896 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381627 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6785358 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10376846 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6807542 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1061382 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1293746 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49728955 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043658 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63251434 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 97401 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10543512 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26574090 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 266492 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77753565 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813486 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77649364 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031782 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.199615 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16523555 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49304070 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9588345 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 552618 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1678659 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1021998 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90748 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56218321 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 303479 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1678659 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17458336 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19025484 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27018348 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9133613 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3332888 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53403158 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13481 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 625557 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2163090 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 470 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55533202 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243132036 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243084049 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47987 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40330710 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15202492 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 427890 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 379964 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6776397 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10330089 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6786263 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1056196 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1308824 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49548242 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1040790 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63116713 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95333 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10484602 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26435485 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 265976 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77649364 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.812843 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.518782 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54887435 70.59% 70.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7226514 9.29% 79.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3706413 4.77% 84.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3121683 4.01% 88.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6295236 8.10% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1399247 1.80% 98.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 816831 1.05% 99.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 232768 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 67438 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54835526 70.62% 70.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7206411 9.28% 79.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3684013 4.74% 84.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3126457 4.03% 88.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6296301 8.11% 96.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1390393 1.79% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 812577 1.05% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231214 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66472 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77753565 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77649364 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 32377 0.72% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 32527 0.73% 0.73% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available @@ -798,504 +810,504 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4226171 94.63% 95.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207252 4.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4227565 94.61% 95.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 208097 4.66% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195848 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29986404 47.41% 47.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47518 0.08% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1215 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26774233 42.33% 90.12% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6246205 9.88% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195790 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29888266 47.35% 47.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47148 0.07% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1209 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.74% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26756071 42.39% 90.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6228206 9.87% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63251434 # Type of FU issued -system.cpu0.iq.rate 0.264608 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4465804 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070604 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208856960 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61325058 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44235430 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12232 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6621 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5553 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67514929 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6461 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 324203 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63116713 # Type of FU issued +system.cpu0.iq.rate 0.263933 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4468193 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070793 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208483702 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61082486 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44086612 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12401 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6581 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5541 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67382548 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6568 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 320496 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2284618 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3570 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16131 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 894521 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2269255 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 15997 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 887357 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17140357 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367566 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17163539 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367436 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1689651 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14217323 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 235152 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50889581 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 104636 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10376846 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6807542 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742609 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56975 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3444 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16131 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 187025 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 148295 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 335320 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62072955 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26415193 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1178479 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1678659 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14252559 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 235358 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50705856 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 106082 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10330089 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6786263 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 740769 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 57048 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3493 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 15997 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 185463 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146727 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 332190 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61942896 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26397875 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1173817 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116968 # number of nop insts executed -system.cpu0.iew.exec_refs 32604278 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6035543 # Number of branches executed -system.cpu0.iew.exec_stores 6189085 # Number of stores executed -system.cpu0.iew.exec_rate 0.259677 # Inst execution rate -system.cpu0.iew.wb_sent 61541297 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44240983 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24348710 # num instructions producing a value -system.cpu0.iew.wb_consumers 44715244 # num instructions consuming a value +system.cpu0.iew.exec_nop 116824 # number of nop insts executed +system.cpu0.iew.exec_refs 32569629 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6012851 # Number of branches executed +system.cpu0.iew.exec_stores 6171754 # Number of stores executed +system.cpu0.iew.exec_rate 0.259024 # Inst execution rate +system.cpu0.iew.wb_sent 61414090 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44092153 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24268667 # num instructions producing a value +system.cpu0.iew.wb_consumers 44593954 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.185079 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544528 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184379 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544214 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10387971 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 777166 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 292435 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76063914 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525878 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.507211 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10328850 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 774814 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 289634 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75970705 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.524893 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.506232 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61806692 81.26% 81.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6917678 9.09% 90.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2055110 2.70% 93.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1140236 1.50% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1042779 1.37% 95.92% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 551797 0.73% 96.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 701755 0.92% 97.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 371851 0.49% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1476016 1.94% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61754720 81.29% 81.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6906334 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2042059 2.69% 93.07% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1137631 1.50% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1039888 1.37% 95.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547173 0.72% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 697067 0.92% 97.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 371357 0.49% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1474476 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76063914 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31320190 # Number of instructions committed -system.cpu0.commit.committedOps 40000322 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75970705 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31216883 # Number of instructions committed +system.cpu0.commit.committedOps 39876471 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14005249 # Number of memory references committed -system.cpu0.commit.loads 8092228 # Number of loads committed -system.cpu0.commit.membars 212474 # Number of memory barriers committed -system.cpu0.commit.branches 5211695 # Number of branches committed -system.cpu0.commit.fp_insts 5465 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35344589 # Number of committed integer instructions. -system.cpu0.commit.function_calls 514446 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1476016 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13959740 # Number of memory references committed +system.cpu0.commit.loads 8060834 # Number of loads committed +system.cpu0.commit.membars 211745 # Number of memory barriers committed +system.cpu0.commit.branches 5194005 # Number of branches committed +system.cpu0.commit.fp_insts 5497 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35234084 # Number of committed integer instructions. +system.cpu0.commit.function_calls 512673 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1474476 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123998072 # The number of ROB reads -system.cpu0.rob.rob_writes 102508386 # The number of ROB writes -system.cpu0.timesIdled 885261 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161285099 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289741427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31240748 # Number of Instructions Simulated -system.cpu0.committedOps 39920880 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31240748 # Number of Instructions Simulated -system.cpu0.cpi 7.651503 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.651503 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130693 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130693 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 281024230 # number of integer regfile reads -system.cpu0.int_regfile_writes 45498524 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22712 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19798 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15634103 # number of misc regfile reads -system.cpu0.misc_regfile_writes 430225 # number of misc regfile writes -system.cpu0.icache.replacements 984356 # number of replacements -system.cpu0.icache.tagsinuse 511.608403 # Cycle average of tags in use -system.cpu0.icache.total_refs 11036978 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984868 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.206556 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123727475 # The number of ROB reads +system.cpu0.rob.rob_writes 102131366 # The number of ROB writes +system.cpu0.timesIdled 883402 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161489905 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289692501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31137553 # Number of Instructions Simulated +system.cpu0.committedOps 39797141 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31137553 # Number of Instructions Simulated +system.cpu0.cpi 7.680092 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.680092 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130207 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130207 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280388173 # number of integer regfile reads +system.cpu0.int_regfile_writes 45343219 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22835 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19826 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15490012 # number of misc regfile reads +system.cpu0.misc_regfile_writes 428542 # number of misc regfile writes +system.cpu0.icache.replacements 983837 # number of replacements +system.cpu0.icache.tagsinuse 511.608434 # Cycle average of tags in use +system.cpu0.icache.total_refs 11044105 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984349 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.219705 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 359.190801 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 152.417601 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.701545 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.297691 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 356.557711 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 155.050723 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.696402 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.302833 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5577013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5459965 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11036978 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5577013 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5459965 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11036978 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5577013 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5459965 # number of overall hits -system.cpu0.icache.overall_hits::total 11036978 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 543890 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 521924 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065814 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 543890 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 521924 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065814 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 543890 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 521924 # number of overall misses -system.cpu0.icache.overall_misses::total 1065814 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7368318492 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6936357997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14304676489 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7368318492 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6936357997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14304676489 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7368318492 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6936357997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14304676489 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6120903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12102792 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6120903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5981889 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12102792 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6120903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5981889 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12102792 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088858 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087251 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088063 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088858 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087251 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088063 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088858 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087251 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088063 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.442483 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13289.977079 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13421.362910 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.442483 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13289.977079 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13421.362910 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.442483 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13289.977079 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13421.362910 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4739 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 847 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 348 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 5554519 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5489586 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11044105 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5554519 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5489586 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11044105 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13283.466163 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13416.705143 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5066 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 940 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 333 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.617816 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 847 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.213213 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 940 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # 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mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.082070 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080668 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081377 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11962.619923 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11709.250246 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11838.480772 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11962.619923 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11709.250246 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11838.480772 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11962.619923 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11709.250246 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11838.480772 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081289 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080831 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081289 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081743 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080831 # 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average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643416 # number of replacements +system.cpu0.dcache.replacements 643632 # number of replacements system.cpu0.dcache.tagsinuse 511.992721 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533980 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 643928 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.441596 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 21539031 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644144 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.438223 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 319.135976 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 192.856745 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.623312 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.376673 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 318.855973 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.136748 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.622766 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.377220 # 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number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.writebacks::writebacks 608032 # number of writebacks +system.cpu0.dcache.writebacks::total 608032 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 219382 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 144497 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 363879 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1284538 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1427444 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 2711982 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 715 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 707 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1422 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1503920 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1571941 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3075861 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1503920 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1571941 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3075861 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212780 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 173209 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 385989 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 120344 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 128537 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 248881 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6150 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 6063 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 333124 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 301746 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 634870 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 333124 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 301746 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 634870 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2896058500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2345588000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5241646500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4040706484 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4421917442 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8462623926 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72222000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 74035000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146257000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 67000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 133000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6936764984 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6767505442 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13704270426 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6936764984 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6767505442 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13704270426 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91949852000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90406740000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356592000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14910322570 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18705155021 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33615477591 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106732946936 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109215616220 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948563156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028290 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024665 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026554 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023234 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025493 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024348 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046835 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048056 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047426 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026236 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025012 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025643 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026236 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025012 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025643 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13597.997927 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13537.732605 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13571.191937 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33496.507264 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34418.762073 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33972.661544 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11711.161145 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12279.959886 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11990.082780 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106860174570 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109111895021 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215972069591 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028239 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024754 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026561 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023281 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025434 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024345 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046516 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048356 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047412 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000044 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025646 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026222 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025039 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025646 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13610.576652 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13541.952208 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13579.782066 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33576.301968 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34401.903281 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.691752 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11743.414634 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12210.951674 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11975.517891 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20758.411444 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22479.359666 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21572.140759 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20758.411444 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22479.359666 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21572.140759 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12090.909091 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20823.372030 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22427.821552 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21585.947400 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1310,38 +1322,38 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7008518 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5622209 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 340954 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4512372 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3795619 # Number of BTB hits +system.cpu1.branchPred.lookups 7054454 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5657096 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 345347 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4549622 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3820237 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.115826 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 671281 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35132 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 83.968229 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 674890 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35092 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25306381 # DTB read hits -system.cpu1.dtb.read_misses 36302 # DTB read misses -system.cpu1.dtb.write_hits 5796978 # DTB write hits -system.cpu1.dtb.write_misses 9188 # DTB write misses +system.cpu1.dtb.read_hits 25326740 # DTB read hits +system.cpu1.dtb.read_misses 36422 # DTB read misses +system.cpu1.dtb.write_hits 5812086 # DTB write hits +system.cpu1.dtb.write_misses 9253 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5467 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5525 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1356 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 233 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25342683 # DTB read accesses -system.cpu1.dtb.write_accesses 5806166 # DTB write accesses +system.cpu1.dtb.perms_faults 644 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25363162 # DTB read accesses +system.cpu1.dtb.write_accesses 5821339 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31103359 # DTB hits -system.cpu1.dtb.misses 45490 # DTB misses -system.cpu1.dtb.accesses 31148849 # DTB accesses -system.cpu1.itb.inst_hits 5983864 # ITB inst hits -system.cpu1.itb.inst_misses 6799 # ITB inst misses +system.cpu1.dtb.hits 31138826 # DTB hits +system.cpu1.dtb.misses 45675 # DTB misses +system.cpu1.dtb.accesses 31184501 # DTB accesses +system.cpu1.itb.inst_hits 6017589 # ITB inst hits +system.cpu1.itb.inst_misses 6780 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1350,284 +1362,284 @@ system.cpu1.itb.flush_tlb 254 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2574 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1493 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5990663 # ITB inst accesses -system.cpu1.itb.hits 5983864 # DTB hits -system.cpu1.itb.misses 6799 # DTB misses -system.cpu1.itb.accesses 5990663 # DTB accesses -system.cpu1.numCycles 234290379 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6024369 # ITB inst accesses +system.cpu1.itb.hits 6017589 # DTB hits +system.cpu1.itb.misses 6780 # DTB misses +system.cpu1.itb.accesses 6024369 # DTB accesses +system.cpu1.numCycles 234207757 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15116451 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46466902 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7008518 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4466900 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10252429 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2600331 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81459 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47550524 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2006 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 43802 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94777 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 144 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5981892 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442637 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2912 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74921475 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.771035 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.135527 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15218240 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46698589 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7054454 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4495127 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10302624 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2620130 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82175 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 46347162 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1067 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2022 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43841 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1251673 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 166 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 6015552 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 445431 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2871 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 75042047 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773320 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138232 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64676712 86.33% 86.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 618864 0.83% 87.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 829977 1.11% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1202840 1.61% 89.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1044061 1.39% 91.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 533999 0.71% 91.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1368584 1.83% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 349498 0.47% 94.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4296940 5.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64747187 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 625900 0.83% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 833929 1.11% 88.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1208466 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1046555 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 538335 0.72% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1373859 1.83% 93.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351234 0.47% 94.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4316582 5.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74921475 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029914 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.198330 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16127430 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47340991 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9302277 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 452157 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1696491 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 939788 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 85014 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54712393 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 283938 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1696491 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17063579 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18568678 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25752424 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8740556 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3097679 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51550474 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7120 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 486939 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2114664 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 95 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53606265 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 236686025 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 236643642 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42383 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37932809 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15673455 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 402617 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 356688 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6237356 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9815438 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6669487 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 880329 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1133832 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47508806 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 941900 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60718178 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80732 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10491137 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27821920 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236570 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74921475 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.810424 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521077 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 75042047 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030120 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199390 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16229024 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47299345 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9347740 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 453958 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1709750 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 948283 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85990 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54953007 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286020 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1709750 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17168291 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18529773 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25747808 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8785346 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3098929 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51771461 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7122 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 486511 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2115721 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53850166 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237651325 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237608915 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42410 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38062786 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15787379 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 405266 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 358955 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6248671 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9866186 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6689314 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 887473 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1140418 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47717114 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 944883 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60871845 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 81909 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10575332 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 28005773 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 237169 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 75042047 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811170 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521401 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53226617 71.04% 71.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6639225 8.86% 79.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3521147 4.70% 84.60% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2865539 3.82% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6243808 8.33% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1415606 1.89% 98.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 739373 0.99% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210738 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59422 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53284770 71.01% 71.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6662382 8.88% 79.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3536622 4.71% 84.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2873956 3.83% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6247532 8.33% 96.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1425164 1.90% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 742478 0.99% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 209609 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59534 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74921475 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 75042047 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 26168 0.60% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4150795 94.85% 95.45% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199100 4.55% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26737 0.61% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4146600 94.82% 95.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 199958 4.57% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 167818 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28373691 46.73% 47.01% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46091 0.08% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040141 42.89% 89.97% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6089511 10.03% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167876 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28487291 46.80% 47.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46424 0.08% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 902 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26063934 42.82% 89.97% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6105398 10.03% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60718178 # Type of FU issued -system.cpu1.iq.rate 0.259158 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4376064 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072072 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200849206 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58949996 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41661656 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10739 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5891 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4795 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 64920728 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5696 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 301587 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60871845 # Type of FU issued +system.cpu1.iq.rate 0.259905 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4373296 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071844 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201275709 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59245662 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41829457 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10720 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5895 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4750 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65071600 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5665 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 304013 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2252430 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3185 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14519 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 849951 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2271620 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3204 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14692 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 855526 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16963490 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 458141 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16940305 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 458975 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1696491 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13989696 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 234454 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48555942 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 97471 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9815438 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6669487 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669348 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 52364 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3770 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14519 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 165263 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 131892 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 297155 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59347630 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635579 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1370548 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1709750 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13959970 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 234377 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48767354 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 97921 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9866186 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6689314 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 671038 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52079 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3815 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14692 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 167743 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133124 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 300867 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59498020 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25657253 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1373825 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105236 # number of nop insts executed -system.cpu1.iew.exec_refs 31674399 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5507310 # Number of branches executed -system.cpu1.iew.exec_stores 6038820 # Number of stores executed -system.cpu1.iew.exec_rate 0.253308 # Inst execution rate -system.cpu1.iew.wb_sent 58770434 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41666451 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22724136 # num instructions producing a value -system.cpu1.iew.wb_consumers 41696356 # num instructions consuming a value +system.cpu1.iew.exec_nop 105357 # number of nop insts executed +system.cpu1.iew.exec_refs 31711723 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5535621 # Number of branches executed +system.cpu1.iew.exec_stores 6054470 # Number of stores executed +system.cpu1.iew.exec_rate 0.254039 # Inst execution rate +system.cpu1.iew.wb_sent 58916799 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41834207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22806182 # num instructions producing a value +system.cpu1.iew.wb_consumers 41818913 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177841 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.544991 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178620 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545356 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10406617 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 705330 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 257195 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73224984 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.515564 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.495876 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10492813 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 707714 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 260708 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73332297 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516509 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.496867 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59733735 81.58% 81.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6648402 9.08% 90.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1900730 2.60% 93.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1014899 1.39% 94.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 955667 1.31% 95.94% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 519546 0.71% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 702094 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 374619 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1375292 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59797837 81.54% 81.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6663272 9.09% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1912982 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1016048 1.39% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 959954 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 526368 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 702800 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 373366 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1379670 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73224984 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29140034 # Number of instructions committed -system.cpu1.commit.committedOps 37752190 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73332297 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29243924 # Number of instructions committed +system.cpu1.commit.committedOps 37876758 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13382544 # Number of memory references committed -system.cpu1.commit.loads 7563008 # Number of loads committed -system.cpu1.commit.membars 191164 # Number of memory barriers committed -system.cpu1.commit.branches 4749934 # Number of branches committed -system.cpu1.commit.fp_insts 4747 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33512913 # Number of committed integer instructions. -system.cpu1.commit.function_calls 476869 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1375292 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13428354 # Number of memory references committed +system.cpu1.commit.loads 7594566 # Number of loads committed +system.cpu1.commit.membars 191899 # Number of memory barriers committed +system.cpu1.commit.branches 4767702 # Number of branches committed +system.cpu1.commit.fp_insts 4715 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33624060 # Number of committed integer instructions. +system.cpu1.commit.function_calls 478655 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1379670 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119137293 # The number of ROB reads -system.cpu1.rob.rob_writes 98065994 # The number of ROB writes -system.cpu1.timesIdled 872405 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159368904 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285729995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29069095 # Number of Instructions Simulated -system.cpu1.committedOps 37681251 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29069095 # Number of Instructions Simulated -system.cpu1.cpi 8.059775 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.059775 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124073 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124073 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 268846383 # number of integer regfile reads -system.cpu1.int_regfile_writes 42770958 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22164 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19740 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14685681 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402240 # number of misc regfile writes +system.cpu1.rob.rob_reads 119446868 # The number of ROB reads +system.cpu1.rob.rob_writes 98500710 # The number of ROB writes +system.cpu1.timesIdled 873517 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159165710 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285782593 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29172873 # Number of Instructions Simulated +system.cpu1.committedOps 37805707 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29172873 # Number of Instructions Simulated +system.cpu1.cpi 8.028272 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.028272 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124560 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124560 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269572472 # number of integer regfile reads +system.cpu1.int_regfile_writes 42951903 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22113 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14815337 # number of misc regfile reads +system.cpu1.misc_regfile_writes 403940 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1642,17 +1654,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192848371945 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192848371945 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192848371945 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192848371945 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192618547941 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192618547941 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192618547941 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83051 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83057 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 8baae834f..0095c8976 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,14 +19,16 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 +panic_on_oops=true +panic_on_panic=true readfile=tests/halt.sh symbolfile= work_begin_ckpt_count=0 @@ -65,7 +67,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -91,6 +93,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=false system=system tracer=system.cpu0.tracer @@ -214,6 +217,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +simpoint_start_insts= switched_out=true system=system tracer=system.cpu1.tracer diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 26ec1de8f..a80cc588c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,16 +1,28 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.610012 # Number of seconds simulated -sim_ticks 2610011893000 # Number of ticks simulated -final_tick 2610011893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2610011895000 # Number of ticks simulated +final_tick 2610011895000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167893 # Simulator instruction rate (inst/s) -host_op_rate 213643 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7278548305 # Simulator tick rate (ticks/s) -host_mem_usage 438276 # Number of bytes of host memory used -host_seconds 358.59 # Real time elapsed on the host +host_inst_rate 531747 # Simulator instruction rate (inst/s) +host_op_rate 676644 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 23052454652 # Simulator tick rate (ticks/s) +host_mem_usage 397728 # Number of bytes of host memory used +host_seconds 113.22 # Real time elapsed on the host sim_insts 60204721 # Number of instructions simulated sim_ops 76610045 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -105,7 +117,7 @@ system.physmem.perBankWrReqs::14 50585 # Tr system.physmem.perBankWrReqs::15 51197 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2610007485000 # Total gap between requests +system.physmem.totGap 2610007487000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6679 # Categorize read packet sizes @@ -122,11 +134,11 @@ system.physmem.writePktSize::5 0 # Ca system.physmem.writePktSize::6 57385 # Categorize write packet sizes system.physmem.rdQLenPdf::0 1116599 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 960481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 974946 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3652365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3652366 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2754414 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2758655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2734327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2758656 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2734326 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 61705 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 60367 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 111551 # What read queue length does an incoming req see @@ -184,14 +196,14 @@ system.physmem.wrQLenPdf::28 1 # Wh system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 338127152500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 432998718750 # Sum of mem lat for all requests +system.physmem.totQLat 338127200750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 432998808250 # Sum of mem lat for all requests system.physmem.totBusLat 77470020000 # Total cycles spent in databus access -system.physmem.totBankLat 17401546250 # Total cycles spent in bank access +system.physmem.totBankLat 17401587500 # Total cycles spent in bank access system.physmem.avgQLat 21823.10 # Average queueing delay per request -system.physmem.avgBankLat 1123.11 # Average bank access latency per request +system.physmem.avgBankLat 1123.12 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27946.21 # Average memory access latency +system.physmem.avgMemAccLat 27946.22 # Average memory access latency system.physmem.avgRdBW 379.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.90 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s @@ -205,31 +217,19 @@ system.physmem.writeRowHits 794097 # Nu system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.86 # Row buffer hit rate for writes system.physmem.avgGap 160069.31 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 61815 # number of replacements -system.l2c.tagsinuse 50922.556622 # Cycle average of tags in use +system.l2c.tagsinuse 50922.556971 # Cycle average of tags in use system.l2c.total_refs 1697645 # Total number of references to valid blocks. system.l2c.sampled_refs 127200 # Sample count of references to valid blocks. system.l2c.avg_refs 13.346266 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2558113997500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37911.407506 # Average occupied blocks per requestor +system.l2c.warmup_cycle 2558113998500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 37911.407860 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000184 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000643 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3494.638708 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3026.772490 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3494.638706 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3026.772488 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 3500.625095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2989.111997 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2989.111995 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.578482 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -240,12 +240,12 @@ system.l2c.occ_percent::cpu1.data 0.045610 # Av system.l2c.occ_percent::total 0.777017 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 10043 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3654 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 407564 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 186717 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 407563 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 186718 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 9399 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 3346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 436383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 183761 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 436384 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 183760 # number of ReadReq hits system.l2c.ReadReq_hits::total 1240867 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 596298 # number of Writeback hits system.l2c.Writeback_hits::total 596298 # number of Writeback hits @@ -257,21 +257,21 @@ system.l2c.ReadExReq_hits::cpu1.data 58743 # nu system.l2c.ReadExReq_hits::total 114544 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 10043 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 3654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 407564 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 242518 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 407563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 242519 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 9399 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 3346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 436383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 242504 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 436384 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 242503 # number of demand (read+write) hits system.l2c.demand_hits::total 1355411 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 10043 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 3654 # number of overall hits -system.l2c.overall_hits::cpu0.inst 407564 # number of overall hits -system.l2c.overall_hits::cpu0.data 242518 # number of overall hits +system.l2c.overall_hits::cpu0.inst 407563 # number of overall hits +system.l2c.overall_hits::cpu0.data 242519 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 9399 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 3346 # number of overall hits -system.l2c.overall_hits::cpu1.inst 436383 # number of overall hits -system.l2c.overall_hits::cpu1.data 242504 # number of overall hits +system.l2c.overall_hits::cpu1.inst 436384 # number of overall hits +system.l2c.overall_hits::cpu1.data 242503 # number of overall hits system.l2c.overall_hits::total 1355411 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses @@ -303,38 +303,38 @@ system.l2c.overall_misses::total 153560 # nu system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 69000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.inst 276276000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 281472500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 285306500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 251488000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1094694500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 281450000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 285328500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 251478000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1094684000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu0.data 249000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu1.data 205000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 454000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3062671000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3034678000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6097349000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3062643000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3034803500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6097446500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 69000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.inst 276276000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3344143500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 285306500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 3286166000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 7192043500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3344093000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 285328500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 3286281500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7192130500 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 69000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.inst 276276000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3344143500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 285306500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 3286166000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 7192043500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3344093000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 285328500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 3286281500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7192130500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 10044 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 3656 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 412728 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 192005 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 412727 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 192006 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 9399 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 3346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 441819 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 188322 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 441820 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 188321 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 1261319 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 596298 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 596298 # number of Writeback accesses(hits+misses) @@ -346,21 +346,21 @@ system.l2c.ReadExReq_accesses::cpu1.data 125087 # nu system.l2c.ReadExReq_accesses::total 247652 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 10044 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 3656 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 412728 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 314570 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 412727 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 314571 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 9399 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 3346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 441819 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 313409 # 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average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40958.833075 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33836.715664 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39941.167403 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33764.860094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 34259.219816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40958.639427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33836.052948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 39945.214496 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33766.513716 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 34259.809163 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -573,7 +573,7 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7403432 # DTB read hits +system.cpu0.dtb.read_hits 7403435 # DTB read hits system.cpu0.dtb.read_misses 6873 # DTB read misses system.cpu0.dtb.write_hits 5501198 # DTB write hits system.cpu0.dtb.write_misses 1842 # DTB write misses @@ -586,12 +586,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 225 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7410305 # DTB read accesses +system.cpu0.dtb.read_accesses 7410308 # DTB read accesses system.cpu0.dtb.write_accesses 5503040 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12904630 # DTB hits +system.cpu0.dtb.hits 12904633 # DTB hits system.cpu0.dtb.misses 8715 # DTB misses -system.cpu0.dtb.accesses 12913345 # DTB accesses +system.cpu0.dtb.accesses 12913348 # DTB accesses system.cpu0.itb.inst_hits 30303054 # ITB inst hits system.cpu0.itb.inst_misses 3598 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits @@ -613,26 +613,26 @@ system.cpu0.itb.inst_accesses 30306652 # IT system.cpu0.itb.hits 30303054 # DTB hits system.cpu0.itb.misses 3598 # DTB misses system.cpu0.itb.accesses 30306652 # DTB accesses -system.cpu0.numCycles 2668343003 # number of cpu cycles simulated +system.cpu0.numCycles 2668342955 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29632665 # Number of instructions committed -system.cpu0.committedOps 37682858 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33888275 # Number of integer alu accesses +system.cpu0.committedInsts 29632666 # Number of instructions committed +system.cpu0.committedOps 37682860 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33888276 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5192 # Number of float alu accesses system.cpu0.num_func_calls 1024744 # number of times a function call or return occured system.cpu0.num_conditional_control_insts 3926833 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33888275 # number of integer instructions +system.cpu0.num_int_insts 33888276 # number of integer instructions system.cpu0.num_fp_insts 5192 # number of float instructions -system.cpu0.num_int_register_reads 194247306 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36521980 # number of times the integer registers were written +system.cpu0.num_int_register_reads 194247325 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36521977 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3842 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1352 # number of times the floating registers were written -system.cpu0.num_mem_refs 13487420 # number of memory refs -system.cpu0.num_load_insts 7732200 # Number of load instructions +system.cpu0.num_mem_refs 13487423 # number of memory refs +system.cpu0.num_load_insts 7732203 # Number of load instructions system.cpu0.num_store_insts 5755220 # Number of store instructions -system.cpu0.num_idle_cycles -6063478274.849866 # Number of idle cycles -system.cpu0.num_busy_cycles 8731821277.849865 # Number of busy cycles +system.cpu0.num_idle_cycles -6063478143.749568 # Number of idle cycles +system.cpu0.num_busy_cycles 8731821098.749567 # Number of busy cycles system.cpu0.not_idle_fraction 3.272376 # Percentage of non-idle cycles system.cpu0.idle_fraction -2.272376 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed @@ -643,38 +643,38 @@ system.cpu0.icache.total_refs 60642600 # To system.cpu0.icache.sampled_refs 856185 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 70.828851 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 18907162000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 150.590705 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 360.381607 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 150.590700 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 360.381612 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.294122 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::cpu1.inst 0.703870 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.997993 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29889508 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30753092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu0.inst 29889509 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30753091 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60642600 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29889508 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30753092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu0.inst 29889509 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30753091 # number of demand (read+write) hits system.cpu0.icache.demand_hits::total 60642600 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29889508 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 30753092 # number of overall hits +system.cpu0.icache.overall_hits::cpu0.inst 29889509 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30753091 # number of overall hits system.cpu0.icache.overall_hits::total 60642600 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 413546 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 442639 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu0.inst 413545 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 442640 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 856185 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 413546 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 442639 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu0.inst 413545 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 442640 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 856185 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 413546 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 442639 # number of overall misses +system.cpu0.icache.overall_misses::cpu0.inst 413545 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 442640 # number of overall misses system.cpu0.icache.overall_misses::total 856185 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5610148500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5995583000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11605731500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5610148500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 5995583000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11605731500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5610148500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 5995583000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11605731500 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5610135500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 5995618000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11605753500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5610135500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 5995618000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11605753500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5610135500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 5995618000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11605753500 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 30303054 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::cpu1.inst 31195731 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 61498785 # number of ReadReq accesses(hits+misses) @@ -693,15 +693,15 @@ system.cpu0.icache.demand_miss_rate::total 0.013922 # system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013647 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014189 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013922 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13565.960014 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13545.085273 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13555.167984 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13565.960014 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13545.085273 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13555.167984 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13565.960014 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13545.085273 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13555.167984 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13565.961383 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13545.133743 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13555.193679 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13565.961383 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13545.133743 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13555.193679 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13565.961383 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13545.133743 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13555.193679 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,24 +710,24 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413546 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442639 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 413545 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 442640 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 856185 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 413546 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 442639 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 413545 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 442640 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 856185 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 413546 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 442639 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 413545 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 442640 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 856185 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4783056500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5110305000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9893361500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4783056500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5110305000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9893361500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4783056500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5110305000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9893361500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4783045500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5110338000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9893383500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4783045500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5110338000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9893383500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4783045500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5110338000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9893383500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 298856500 # number of overall MSHR uncacheable cycles @@ -741,15 +741,15 @@ system.cpu0.icache.demand_mshr_miss_rate::total 0.013922 system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013647 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014189 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013922 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11555.167984 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11555.167984 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11565.960014 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.085273 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11555.167984 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11565.961383 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.133743 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11555.193679 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11565.961383 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.133743 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11555.193679 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11565.961383 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.133743 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11555.193679 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -761,13 +761,13 @@ system.cpu0.dcache.total_refs 23658362 # To system.cpu0.dcache.sampled_refs 627978 # Sample count of references to valid blocks. system.cpu0.dcache.avg_refs 37.673871 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 140.437193 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 371.475629 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu0.data 140.437195 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 371.475626 # Average occupied blocks per requestor system.cpu0.dcache.occ_percent::cpu0.data 0.274291 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::cpu1.data 0.725538 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999830 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6510444 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6686709 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 6510445 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6686708 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13197153 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 4886816 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::cpu1.data 5087431 # number of WriteReq hits @@ -778,14 +778,14 @@ system.cpu0.dcache.LoadLockedReq_hits::total 236322 system.cpu0.dcache.StoreCondReq_hits::cpu0.data 112519 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::cpu1.data 135213 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 247732 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11397260 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11774140 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 11397261 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 11774139 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 23171400 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11397260 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11774140 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 11397261 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 11774139 # number of overall hits system.cpu0.dcache.overall_hits::total 23171400 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 186238 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 182678 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 186239 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 182677 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 368916 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 123980 # 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number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4024689000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4035697500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8060386500 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 80055500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 75055500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 155111000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 6680861500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 6627466500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 13308328000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 6680861500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 6627466500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 13308328000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6696682 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6869387 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 6680826500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 6627569500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13308396000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 6680826500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 6627569500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13308396000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6696684 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6869385 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 13566069 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 5010796 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu1.data 5214011 # number of WriteReq accesses(hits+misses) @@ -826,13 +826,13 @@ system.cpu0.dcache.LoadLockedReq_accesses::total 247733 system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 112519 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 135213 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247732 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11707478 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12083398 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 11707480 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 12083396 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 23790876 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11707478 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12083398 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11707480 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 12083396 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 23790876 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027810 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027811 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.026593 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.027194 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.024743 # miss rate for WriteReq accesses @@ -841,27 +841,27 @@ system.cpu0.dcache.WriteReq_miss_rate::total 0.024505 system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051254 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.041741 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046062 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026497 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026498 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025594 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026038 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026497 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026498 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025594 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026038 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14262.108163 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14188.325907 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14225.573030 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32462.614938 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31881.588719 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 32169.087245 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14261.983258 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14188.277670 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14225.486290 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 32462.405227 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31882.584137 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 32169.486351 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13881.654240 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13298.281361 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13593.111910 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21536.021443 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.218458 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21483.201932 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.021443 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.218458 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21483.201932 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21483.311702 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21535.839197 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21430.620811 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21483.311702 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -872,8 +872,8 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 596298 # number of writebacks system.cpu0.dcache.writebacks::total 596298 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186238 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182678 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 186239 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 182677 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 368916 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 123980 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 126580 # number of WriteReq MSHR misses @@ -881,41 +881,41 @@ system.cpu0.dcache.WriteReq_mshr_misses::total 250560 system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5767 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5644 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11411 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 310218 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 309258 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 310219 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 309257 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 619476 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 310218 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 309258 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 310219 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 309257 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 619476 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283670500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226539000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510209500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3776755000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 3782411500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7559166500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2283659500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2226518000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4510177500 # 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number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 18700033500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654781500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100140166000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794947500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027810 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 100654899000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 100139976500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 200794875500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027811 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027194 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024743 # mshr miss rate for WriteReq accesses @@ -924,27 +924,27 @@ system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051254 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.041741 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046062 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.026038 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026497 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026498 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025594 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.026038 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12262.108163 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.325907 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.573030 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.614938 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29881.588719 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.087245 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12261.983258 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12188.277670 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12225.486290 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30462.405227 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29882.584137 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30169.486351 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11881.654240 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11298.281361 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.111910 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19536.021443 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.218458 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.201932 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19535.839197 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19430.620811 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19483.311702 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -961,7 +961,7 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7594464 # DTB read hits +system.cpu1.dtb.read_hits 7594461 # DTB read hits system.cpu1.dtb.read_misses 6935 # DTB read misses system.cpu1.dtb.write_hits 5731015 # DTB write hits system.cpu1.dtb.write_misses 1760 # DTB write misses @@ -974,12 +974,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7601399 # DTB read accesses +system.cpu1.dtb.read_accesses 7601396 # DTB read accesses system.cpu1.dtb.write_accesses 5732775 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13325479 # DTB hits +system.cpu1.dtb.hits 13325476 # DTB hits system.cpu1.dtb.misses 8695 # DTB misses -system.cpu1.dtb.accesses 13334174 # DTB accesses +system.cpu1.dtb.accesses 13334171 # DTB accesses system.cpu1.itb.inst_hits 31195731 # ITB inst hits system.cpu1.itb.inst_misses 3619 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits @@ -1001,26 +1001,26 @@ system.cpu1.itb.inst_accesses 31199350 # IT system.cpu1.itb.hits 31195731 # DTB hits system.cpu1.itb.misses 3619 # DTB misses system.cpu1.itb.accesses 31199350 # DTB accesses -system.cpu1.numCycles 2551680783 # number of cpu cycles simulated +system.cpu1.numCycles 2551680835 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30572056 # Number of instructions committed -system.cpu1.committedOps 38927187 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 34988620 # Number of integer alu accesses +system.cpu1.committedInsts 30572055 # Number of instructions committed +system.cpu1.committedOps 38927185 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34988619 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5077 # Number of float alu accesses system.cpu1.num_func_calls 1115365 # number of times a function call or return occured system.cpu1.num_conditional_control_insts 4021820 # number of instructions that are conditional controls -system.cpu1.num_int_insts 34988620 # number of integer instructions +system.cpu1.num_int_insts 34988619 # number of integer instructions system.cpu1.num_fp_insts 5077 # number of float instructions -system.cpu1.num_int_register_reads 200559310 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37663253 # number of times the integer registers were written +system.cpu1.num_int_register_reads 200559291 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37663256 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3651 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1428 # number of times the floating registers were written -system.cpu1.num_mem_refs 13910244 # number of memory refs -system.cpu1.num_load_insts 7929876 # Number of load instructions +system.cpu1.num_mem_refs 13910241 # number of memory refs +system.cpu1.num_load_insts 7929873 # Number of load instructions system.cpu1.num_store_insts 5980368 # Number of store instructions -system.cpu1.num_idle_cycles 10585260111.377636 # Number of idle cycles -system.cpu1.num_busy_cycles -8033579328.377636 # Number of busy cycles +system.cpu1.num_idle_cycles 10585260303.338047 # Number of idle cycles +system.cpu1.num_busy_cycles -8033579468.338046 # Number of busy cycles system.cpu1.not_idle_fraction -3.148348 # Percentage of non-idle cycles system.cpu1.idle_fraction 4.148348 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -1039,10 +1039,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947260006 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947260006 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1195947260006 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1195947261004 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1195947261004 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1195947261004 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |