diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-02-10 09:51:37 -0600 |
| commit | 26ca8b87470912d5e593a21fc968dd2ddf0e20b2 (patch) | |
| tree | bf97df45e65f08107321f58d83688b08bbd3f675 /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | 6a7a6263e16cd3a16b4d7738f7df06f6e7a97ed6 (diff) | |
| download | gem5-26ca8b87470912d5e593a21fc968dd2ddf0e20b2.tar.xz | |
Regressions: Update stats due to O3 CPU changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
7 files changed, 1573 insertions, 1610 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 6f9417ef5..631ad091d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,14 +9,13 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -62,7 +62,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -126,6 +126,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -157,6 +158,7 @@ tracer=system.cpu0.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side @@ -580,6 +582,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -611,6 +614,7 @@ tracer=system.cpu1.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu1.dcache.cpu_side icache_port=system.cpu1.icache.cpu_side @@ -1069,7 +1073,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1111,7 +1114,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -1121,7 +1123,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -1191,7 +1192,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -1203,7 +1203,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -1213,7 +1212,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1242,7 +1240,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -1252,7 +1249,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -1262,7 +1258,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -1275,7 +1270,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -1289,7 +1283,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -1300,7 +1293,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -1319,7 +1311,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -1329,7 +1320,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -1338,7 +1328,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -1350,7 +1339,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -1360,7 +1348,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -1370,7 +1357,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -1380,7 +1366,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -1390,7 +1375,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -1404,7 +1388,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -1418,7 +1401,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -1441,7 +1423,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -1451,7 +1432,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -1461,7 +1441,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -1471,7 +1450,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 04178bb32..523f8a126 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -13,6 +13,7 @@ warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 28da0bb31..6780ea1b9 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 09:54:17 -gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Feb 3 2012 14:00:40 +gem5 started Feb 3 2012 14:01:00 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582494395500 because m5_exit instruction encountered +Exiting @ tick 2582494330500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 11b3b4098..d8f37781a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.582494 # Number of seconds simulated -sim_ticks 2582494395500 # Number of ticks simulated -final_tick 2582494395500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2582494330500 # Number of ticks simulated +final_tick 2582494330500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77486 # Simulator instruction rate (inst/s) -host_tick_rate 2505663009 # Simulator tick rate (ticks/s) -host_mem_usage 386072 # Number of bytes of host memory used -host_seconds 1030.66 # Real time elapsed on the host -sim_insts 79862069 # Number of instructions simulated +host_inst_rate 58235 # Simulator instruction rate (inst/s) +host_tick_rate 1883208568 # Simulator tick rate (ticks/s) +host_mem_usage 413296 # Number of bytes of host memory used +host_seconds 1371.33 # Real time elapsed on the host +sim_insts 79859495 # Number of instructions simulated system.nvmem.bytes_read 384 # Number of bytes read from this memory system.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -18,143 +18,143 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 131490980 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1177856 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10251344 # Number of bytes written to this memory -system.physmem.num_reads 15129077 # Number of read requests responded to by this memory -system.physmem.num_writes 870131 # Number of write requests responded to by this memory +system.physmem.bytes_read 131499364 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1184000 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10236688 # Number of bytes written to this memory +system.physmem.num_reads 15129208 # Number of read requests responded to by this memory +system.physmem.num_writes 869902 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 50916269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 456092 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3969551 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 54885821 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 132200 # number of replacements -system.l2c.tagsinuse 27582.989225 # Cycle average of tags in use -system.l2c.total_refs 1817822 # Total number of references to valid blocks. -system.l2c.sampled_refs 162144 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.211158 # Average number of references to valid blocks. +system.physmem.bw_read 50919517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 458471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3963876 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 54883393 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 132156 # number of replacements +system.l2c.tagsinuse 27576.843805 # Cycle average of tags in use +system.l2c.total_refs 1820044 # Total number of references to valid blocks. +system.l2c.sampled_refs 162190 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.221678 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 5000.897751 # Average occupied blocks per context -system.l2c.occ_blocks::1 7176.831699 # Average occupied blocks per context -system.l2c.occ_blocks::2 15405.259775 # Average occupied blocks per context -system.l2c.occ_percent::0 0.076308 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.109510 # Average percentage of cache occupancy -system.l2c.occ_percent::2 0.235066 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 738573 # number of ReadReq hits -system.l2c.ReadReq_hits::1 628212 # number of ReadReq hits -system.l2c.ReadReq_hits::2 178875 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1545660 # number of ReadReq hits -system.l2c.Writeback_hits::0 598786 # number of Writeback hits -system.l2c.Writeback_hits::total 598786 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 1039 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 1048 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2087 # number of UpgradeReq hits +system.l2c.occ_blocks::0 4997.961622 # Average occupied blocks per context +system.l2c.occ_blocks::1 7175.690427 # Average occupied blocks per context +system.l2c.occ_blocks::2 15403.191755 # Average occupied blocks per context +system.l2c.occ_percent::0 0.076263 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.109492 # Average percentage of cache occupancy +system.l2c.occ_percent::2 0.235034 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 739066 # number of ReadReq hits +system.l2c.ReadReq_hits::1 627724 # number of ReadReq hits +system.l2c.ReadReq_hits::2 184257 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1551047 # number of ReadReq hits +system.l2c.Writeback_hits::0 599046 # number of Writeback hits +system.l2c.Writeback_hits::total 599046 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 992 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 1000 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1992 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::0 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 451 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 626 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 58347 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 39083 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97430 # number of ReadExReq hits -system.l2c.demand_hits::0 796920 # number of demand (read+write) hits -system.l2c.demand_hits::1 667295 # number of demand (read+write) hits -system.l2c.demand_hits::2 178875 # number of demand (read+write) hits -system.l2c.demand_hits::total 1643090 # number of demand (read+write) hits -system.l2c.overall_hits::0 796920 # number of overall hits -system.l2c.overall_hits::1 667295 # number of overall hits -system.l2c.overall_hits::2 178875 # number of overall hits -system.l2c.overall_hits::total 1643090 # number of overall hits -system.l2c.ReadReq_misses::0 19694 # number of ReadReq misses -system.l2c.ReadReq_misses::1 20569 # number of ReadReq misses -system.l2c.ReadReq_misses::2 168 # number of ReadReq misses -system.l2c.ReadReq_misses::total 40431 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7390 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 3840 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11230 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 864 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 454 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1318 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 97999 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 50217 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 148216 # number of ReadExReq misses -system.l2c.demand_misses::0 117693 # number of demand (read+write) misses -system.l2c.demand_misses::1 70786 # number of demand (read+write) misses -system.l2c.demand_misses::2 168 # number of demand (read+write) misses -system.l2c.demand_misses::total 188647 # number of demand (read+write) misses -system.l2c.overall_misses::0 117693 # number of overall misses -system.l2c.overall_misses::1 70786 # number of overall misses -system.l2c.overall_misses::2 168 # number of overall misses -system.l2c.overall_misses::total 188647 # number of overall misses -system.l2c.ReadReq_miss_latency 2112279500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 61500500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency 8037000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7780237999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9892517499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9892517499 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 758267 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 648781 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 179043 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1586091 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 598786 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 598786 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 8429 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 4888 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13317 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 1039 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 905 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1944 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 156346 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 89300 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245646 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 914613 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 738081 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 179043 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1831737 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 914613 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 738081 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 179043 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1831737 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.025972 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.031704 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.000938 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.058615 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.876735 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.785597 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.831569 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.501657 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.626808 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.562340 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.128681 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.095905 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.000938 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.225524 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.128681 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.095905 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.000938 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.225524 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 107254.976135 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 102692.376878 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 12573092.261905 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 12783039.614917 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 8322.124493 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 16015.755208 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_hits::1 443 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 618 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 58603 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 38925 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 97528 # number of ReadExReq hits +system.l2c.demand_hits::0 797669 # number of demand (read+write) hits +system.l2c.demand_hits::1 666649 # number of demand (read+write) hits +system.l2c.demand_hits::2 184257 # number of demand (read+write) hits +system.l2c.demand_hits::total 1648575 # number of demand (read+write) hits +system.l2c.overall_hits::0 797669 # number of overall hits +system.l2c.overall_hits::1 666649 # number of overall hits +system.l2c.overall_hits::2 184257 # number of overall hits +system.l2c.overall_hits::total 1648575 # number of overall hits +system.l2c.ReadReq_misses::0 19787 # number of ReadReq misses +system.l2c.ReadReq_misses::1 20563 # number of ReadReq misses +system.l2c.ReadReq_misses::2 170 # number of ReadReq misses +system.l2c.ReadReq_misses::total 40520 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 7351 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 3816 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11167 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 849 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 448 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1297 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 97885 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 50394 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 148279 # number of ReadExReq misses +system.l2c.demand_misses::0 117672 # number of demand (read+write) misses +system.l2c.demand_misses::1 70957 # number of demand (read+write) misses +system.l2c.demand_misses::2 170 # number of demand (read+write) misses +system.l2c.demand_misses::total 188799 # number of demand (read+write) misses +system.l2c.overall_misses::0 117672 # number of overall misses +system.l2c.overall_misses::1 70957 # number of overall misses +system.l2c.overall_misses::2 170 # number of overall misses +system.l2c.overall_misses::total 188799 # number of overall misses +system.l2c.ReadReq_miss_latency 2117109000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 60330000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency 7673500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7779101999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9896210999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9896210999 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 758853 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 648287 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 184427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1591567 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 599046 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 599046 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 8343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 4816 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13159 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 1024 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 891 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1915 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::0 156488 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 89319 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245807 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::0 915341 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 737606 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 184427 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1837374 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 915341 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 737606 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 184427 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1837374 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026075 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.031719 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.000922 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.058716 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.881098 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.792359 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.829102 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.502806 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.625511 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.564202 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.128555 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.096199 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.000922 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.225676 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.128555 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.096199 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.000922 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.225676 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 106994.946177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 102957.204688 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 12453582.352941 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12663534.503806 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 8207.046660 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 15809.748428 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::0 9302.083333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 17702.643172 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::0 9038.280330 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 17128.348214 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 79390.993775 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 154932.353566 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 79471.849609 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 154365.638747 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 84053.575820 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 139752.458099 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 58884032.732143 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 59107838.766062 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 84053.575820 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 139752.458099 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 58884032.732143 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 59107838.766062 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 84099.964299 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 139467.719873 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 58213005.876471 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 58436573.560642 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 84099.964299 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 139467.719873 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 58213005.876471 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 58436573.560642 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -163,56 +163,56 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 112847 # number of writebacks -system.l2c.ReadReq_mshr_hits 98 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits 98 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 98 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 40333 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 11230 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 1318 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 148216 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 188549 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 188549 # number of overall MSHR misses +system.l2c.writebacks 112618 # number of writebacks +system.l2c.ReadReq_mshr_hits 97 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits 97 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits 97 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses 40423 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 11167 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 1297 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 148279 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 188702 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 188702 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1616144000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 449664000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 52753500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5939088499 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7555232499 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7555232499 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131965191500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32542078084 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164507269584 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.053191 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.062167 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 0.225270 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.340628 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 1.332305 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.297463 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1619864500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 446963000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 51939000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5941339999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7561204499 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7561204499 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131964916000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32535008680 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164499924680 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.053269 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.062354 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 0.219182 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.334804 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 1.338487 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.318729 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.268527 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.456354 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.266602 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.455668 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.948000 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 1.659754 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.947542 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 1.660106 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.206152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0.255458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 1.053093 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.514703 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.206152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0.255458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 1.053093 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.514703 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40070.017108 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40041.317898 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40025.417299 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40070.495082 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40070.392837 # average overall mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.206155 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 0.255830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 1.023180 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.485165 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.206155 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 0.255830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 1.023180 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.485165 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40072.842194 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40025.342527 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40045.489591 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40068.654354 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40069.551457 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40069.551457 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 42404013 # DTB read hits -system.cpu0.dtb.read_misses 55271 # DTB read misses -system.cpu0.dtb.write_hits 6896316 # DTB write hits -system.cpu0.dtb.write_misses 11117 # DTB write misses +system.cpu0.dtb.read_hits 42410626 # DTB read hits +system.cpu0.dtb.read_misses 55840 # DTB read misses +system.cpu0.dtb.write_hits 6900244 # DTB write hits +system.cpu0.dtb.write_misses 11203 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 2702 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 10190 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 580 # Number of TLB faults due to prefetch +system.cpu0.dtb.align_faults 9414 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 598 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1489 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 42459284 # DTB read accesses -system.cpu0.dtb.write_accesses 6907433 # DTB write accesses +system.cpu0.dtb.perms_faults 1544 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 42466466 # DTB read accesses +system.cpu0.dtb.write_accesses 6911447 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 49300329 # DTB hits -system.cpu0.dtb.misses 66388 # DTB misses -system.cpu0.dtb.accesses 49366717 # DTB accesses -system.cpu0.itb.inst_hits 6430047 # ITB inst hits -system.cpu0.itb.inst_misses 17344 # ITB inst misses +system.cpu0.dtb.hits 49310870 # DTB hits +system.cpu0.dtb.misses 67043 # DTB misses +system.cpu0.dtb.accesses 49377913 # DTB accesses +system.cpu0.itb.inst_hits 6428492 # ITB inst hits +system.cpu0.itb.inst_misses 17283 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -256,121 +256,121 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1577 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1596 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 5810 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 5840 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6447391 # ITB inst accesses -system.cpu0.itb.hits 6430047 # DTB hits -system.cpu0.itb.misses 17344 # DTB misses -system.cpu0.itb.accesses 6447391 # DTB accesses -system.cpu0.numCycles 352464224 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6445775 # ITB inst accesses +system.cpu0.itb.hits 6428492 # DTB hits +system.cpu0.itb.misses 17283 # DTB misses +system.cpu0.itb.accesses 6445775 # DTB accesses +system.cpu0.numCycles 352483912 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 8639262 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 6396113 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 634960 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 7354016 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 5046946 # Number of BTB hits +system.cpu0.BPredUnit.lookups 8645116 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 6399988 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 634817 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 7331445 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 5034787 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 806008 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 135144 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16864575 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 45911459 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8639262 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5852954 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 11507352 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2656909 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 105092 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 79183942 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 2005 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 114543 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 115021 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 279 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6424056 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 290090 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 8736 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 109741052 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.540842 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.794710 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 805074 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 135243 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 16860833 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 45928818 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 8645116 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5839861 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 11494054 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2657796 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 106861 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 79215676 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 7529 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 114865 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 114660 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 256 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6422476 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 290012 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 8748 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 109764102 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.540930 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.795930 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98251365 89.53% 89.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 1141553 1.04% 90.57% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1483062 1.35% 91.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1305311 1.19% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1111109 1.01% 94.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 877492 0.80% 94.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 783730 0.71% 95.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 504789 0.46% 96.10% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4282641 3.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98288129 89.54% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 1143186 1.04% 90.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1488169 1.36% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1267497 1.15% 93.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1112191 1.01% 94.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 871683 0.79% 94.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 797932 0.73% 95.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 504639 0.46% 96.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4290676 3.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 109741052 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.024511 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.130258 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18015904 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 78867966 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 10351735 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 744902 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1760545 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1349765 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 89024 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56859019 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 296865 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1760545 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 19077781 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 33324855 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 41068350 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 10047301 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 4462220 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54490886 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1483 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 580883 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 3149232 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 205 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 54779837 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 247536349 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 247487579 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48770 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 41441157 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13338679 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 828868 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 763855 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8500592 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 11770384 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 7686805 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1443183 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1570137 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50961905 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1297752 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 80276174 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 137636 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9888896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22816025 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 253324 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 109741052 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.731505 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.440076 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 109764102 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.024526 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.130300 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18029022 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78891581 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 10335231 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 746808 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1761460 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1349167 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 89318 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56878279 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 297096 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1761460 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 19090042 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 33342572 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 41068842 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 10032499 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 4468687 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54513639 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1476 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 586863 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 3152149 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 190 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 54798998 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 247626093 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 247578647 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47446 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 41436679 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13362318 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 827066 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 763098 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8512546 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 11778849 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 7693096 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1451709 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1599658 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50981510 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1297142 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 80275629 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 138322 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9920481 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22908706 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 252718 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 109764102 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.731347 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.440423 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 80125799 73.01% 73.01% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10111373 9.21% 82.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 4133530 3.77% 85.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3177611 2.90% 88.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 9954078 9.07% 97.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1265279 1.15% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 670333 0.61% 99.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 224189 0.20% 99.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 78860 0.07% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 80151995 73.02% 73.02% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10117120 9.22% 82.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 4139720 3.77% 86.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3156304 2.88% 88.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 9950540 9.07% 97.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1264670 1.15% 99.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 681180 0.62% 99.72% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 223017 0.20% 99.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 79556 0.07% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 109741052 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 109764102 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 37808 0.47% 0.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 38058 0.47% 0.47% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 626 0.01% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.48% # attempts to use FU when none available @@ -399,374 +399,378 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.48% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.48% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.48% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 7704393 95.96% 96.44% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 285533 3.56% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 7704046 95.93% 96.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 287948 3.59% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 88461 0.11% 0.11% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29731481 37.04% 37.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 62351 0.08% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1694 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 43135014 53.73% 90.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 7257159 9.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 88478 0.11% 0.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29722864 37.03% 37.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 62274 0.08% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 3 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.21% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1682 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 43138789 53.74% 90.95% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 7261531 9.05% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 80276174 # Type of FU issued -system.cpu0.iq.rate 0.227757 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 8028360 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.100009 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 278513864 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62161443 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 46668615 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11568 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6980 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5172 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 88210042 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6031 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 399886 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 80275629 # Type of FU issued +system.cpu0.iq.rate 0.227743 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8030678 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.100039 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 278539843 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62212125 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 46665965 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11176 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6795 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5030 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 88212004 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 5825 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 398434 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2526229 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5188 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20554 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 993550 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2535542 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 5119 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20483 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1000305 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 32220160 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 13300 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 32220121 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 13276 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1760545 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 25952608 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 355602 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 52433539 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 243567 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 11770384 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 7686805 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 865740 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 62160 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 5553 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20554 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 507509 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 136100 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 643609 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 79551295 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 42843907 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 724879 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1761460 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 25970226 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 355776 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 52452605 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 244534 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 11778849 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 7693096 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 864933 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 506934 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 642786 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 173882 # number of nop insts executed -system.cpu0.iew.exec_refs 50011427 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6433542 # Number of branches executed -system.cpu0.iew.exec_stores 7167520 # Number of stores executed -system.cpu0.iew.exec_rate 0.225700 # Inst execution rate -system.cpu0.iew.wb_sent 79133797 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 46673787 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24793926 # num instructions producing a value -system.cpu0.iew.wb_consumers 46078393 # num instructions consuming a value +system.cpu0.iew.exec_nop 173953 # number of nop insts executed +system.cpu0.iew.exec_refs 50020846 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6431362 # Number of branches executed +system.cpu0.iew.exec_stores 7171156 # Number of stores executed +system.cpu0.iew.exec_rate 0.225691 # Inst execution rate +system.cpu0.iew.wb_sent 79131384 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 46670995 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24791862 # num instructions producing a value +system.cpu0.iew.wb_consumers 46093474 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.132421 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.538081 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 41927345 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 10365163 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1044428 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 567784 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 108024119 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.388129 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.248779 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 41923639 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 108046246 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.388016 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.248887 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 90994296 84.24% 84.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 9318293 8.63% 92.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2453548 2.27% 95.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1344047 1.24% 96.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1036100 0.96% 97.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 648919 0.60% 97.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 654404 0.61% 98.54% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 241700 0.22% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1332812 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 91022248 84.24% 84.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 9317978 8.62% 92.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2446901 2.26% 95.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1345942 1.25% 96.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1037116 0.96% 97.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 636722 0.59% 97.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 665653 0.62% 98.54% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 241447 0.22% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1332239 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 108024119 # Number of insts commited each cycle -system.cpu0.commit.count 41927345 # Number of instructions committed +system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle +system.cpu0.commit.count 41923639 # Number of instructions committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 15937410 # Number of memory references committed -system.cpu0.commit.loads 9244155 # Number of loads committed -system.cpu0.commit.membars 288635 # Number of memory barriers committed -system.cpu0.commit.branches 5542672 # Number of branches committed -system.cpu0.commit.fp_insts 4916 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 37173454 # Number of committed integer instructions. -system.cpu0.commit.function_calls 620264 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1332812 # number cycles where commit BW limit reached +system.cpu0.commit.refs 15936098 # Number of memory references committed +system.cpu0.commit.loads 9243307 # Number of loads committed +system.cpu0.commit.membars 288653 # Number of memory barriers committed +system.cpu0.commit.branches 5542289 # Number of branches committed +system.cpu0.commit.fp_insts 4852 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 37169940 # Number of committed integer instructions. +system.cpu0.commit.function_calls 620184 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1332239 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 157900366 # The number of ROB reads -system.cpu0.rob.rob_writes 106355397 # The number of ROB writes -system.cpu0.timesIdled 1453890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 242723172 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 4812468828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41801518 # Number of Instructions Simulated -system.cpu0.committedInsts_total 41801518 # Number of Instructions Simulated -system.cpu0.cpi 8.431852 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 8.431852 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.118598 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.118598 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 354175079 # number of integer regfile reads -system.cpu0.int_regfile_writes 46137251 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4205 # number of floating regfile reads -system.cpu0.fp_regfile_writes 1348 # number of floating regfile writes -system.cpu0.misc_regfile_reads 65629786 # number of misc regfile reads -system.cpu0.misc_regfile_writes 635954 # number of misc regfile writes -system.cpu0.icache.replacements 539173 # number of replacements -system.cpu0.icache.tagsinuse 511.623608 # Cycle average of tags in use -system.cpu0.icache.total_refs 5839899 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 539685 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 10.820940 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 16020223000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::0 511.623608 # Average occupied blocks per context -system.cpu0.icache.occ_percent::0 0.999265 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::0 5839899 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5839899 # number of ReadReq hits -system.cpu0.icache.demand_hits::0 5839899 # number of demand (read+write) hits +system.cpu0.rob.rob_reads 157931724 # The number of ROB reads +system.cpu0.rob.rob_writes 106372981 # The number of ROB writes +system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 41797812 # Number of Instructions Simulated +system.cpu0.committedInsts_total 41797812 # Number of Instructions Simulated +system.cpu0.cpi 8.433071 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.433071 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.118581 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.118581 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads +system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads +system.cpu0.fp_regfile_writes 1336 # number of floating regfile writes +system.cpu0.misc_regfile_reads 65704114 # number of misc regfile reads +system.cpu0.misc_regfile_writes 635920 # number of misc regfile writes +system.cpu0.icache.replacements 538787 # number of replacements +system.cpu0.icache.tagsinuse 511.612990 # Cycle average of tags in use +system.cpu0.icache.total_refs 5838964 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::0 511.612990 # Average occupied blocks per context +system.cpu0.icache.occ_percent::0 0.999244 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::0 5838964 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5838964 # number of ReadReq hits +system.cpu0.icache.demand_hits::0 5838964 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5839899 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::0 5839899 # number of overall hits +system.cpu0.icache.demand_hits::total 5838964 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::0 5838964 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 5839899 # number of overall hits -system.cpu0.icache.ReadReq_misses::0 584029 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 584029 # number of ReadReq misses -system.cpu0.icache.demand_misses::0 584029 # number of demand (read+write) misses +system.cpu0.icache.overall_hits::total 5838964 # number of overall hits +system.cpu0.icache.ReadReq_misses::0 583385 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 583385 # number of ReadReq misses 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no_value # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::0 0.090915 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::0 0.090837 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::0 14968.531511 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::0 14968.531511 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::0 14981.780450 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::0 14968.531511 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::0 14981.780450 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1586493 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 210 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 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miss cycles +system.cpu0.dcache.ReadReq_accesses::0 8430247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8430247 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::0 6210780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::0 231253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::0 207554 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 207554 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::0 14641027 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 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miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::0 13938.284221 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::0 37819.001675 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12137.203696 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11383.590734 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::0 33067.208456 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::0 33067.208456 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 6759989 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1802000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 868 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 123 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7788.005760 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 14650.406504 # average number of cycles each access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7939.679157 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks 326934 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits 223096 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits 1684995 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits 326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits 1908091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits 1908091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses 239784 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses 178385 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses 9630 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses 7769 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses 418169 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses 418169 # number of overall MSHR misses +system.cpu0.dcache.writebacks 327766 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits 223882 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits 1685987 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits 318 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits 1909869 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits 1909869 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses 239530 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses 178306 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses 9724 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses 7685 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses 417836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses 417836 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 2937322500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency 6377417488 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 86877000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 65112500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency 9314739988 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency 9314739988 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138959379000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038732984 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency 139998111984 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028470 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency 2943060000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency 6370530485 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 87975000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 64109000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency 9313590485 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency 9313590485 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138958680000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1038766498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028413 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.028709 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.041648 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.042049 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037437 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.037027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::0 0.028576 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::0 0.028539 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::0 0.028576 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::0 0.028539 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12249.868632 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35750.861833 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9021.495327 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8381.065774 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 22275.061011 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35728.076930 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 9047.202797 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 8342.094990 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -775,27 +779,27 @@ system.cpu0.dcache.soft_prefetch_mshr_full 0 # system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10573739 # DTB read hits -system.cpu1.dtb.read_misses 42015 # DTB read misses -system.cpu1.dtb.write_hits 5529871 # DTB write hits -system.cpu1.dtb.write_misses 15191 # DTB write misses +system.cpu1.dtb.read_hits 10576968 # DTB read hits +system.cpu1.dtb.read_misses 41875 # DTB read misses +system.cpu1.dtb.write_hits 5530754 # DTB write hits +system.cpu1.dtb.write_misses 15302 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1927 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3403 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 280 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1929 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3229 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 271 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 684 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10615754 # DTB read accesses -system.cpu1.dtb.write_accesses 5545062 # DTB write accesses +system.cpu1.dtb.perms_faults 692 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10618843 # DTB read accesses +system.cpu1.dtb.write_accesses 5546056 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16103610 # DTB hits -system.cpu1.dtb.misses 57206 # DTB misses -system.cpu1.dtb.accesses 16160816 # DTB accesses -system.cpu1.itb.inst_hits 8206065 # ITB inst hits -system.cpu1.itb.inst_misses 3031 # ITB inst misses +system.cpu1.dtb.hits 16107722 # DTB hits +system.cpu1.dtb.misses 57177 # DTB misses +system.cpu1.dtb.accesses 16164899 # DTB accesses +system.cpu1.itb.inst_hits 8214514 # ITB inst hits +system.cpu1.itb.inst_misses 3039 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -804,517 +808,517 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1367 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1364 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2156 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2090 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8209096 # ITB inst accesses -system.cpu1.itb.hits 8206065 # DTB hits -system.cpu1.itb.misses 3031 # DTB misses -system.cpu1.itb.accesses 8209096 # DTB accesses -system.cpu1.numCycles 69056369 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8217553 # ITB inst accesses +system.cpu1.itb.hits 8214514 # DTB hits +system.cpu1.itb.misses 3039 # DTB misses +system.cpu1.itb.accesses 8217553 # DTB accesses +system.cpu1.numCycles 69079827 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 8325282 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 6737041 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 502555 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7261407 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5699060 # Number of BTB hits +system.cpu1.BPredUnit.lookups 8333886 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 6743827 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 503378 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 7264644 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5697386 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 682916 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 107380 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 17608500 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 62544782 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8325282 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6381976 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13909998 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4633998 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 45331 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 15806576 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 3075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 32937 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 125179 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8203545 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 759342 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1683 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 50660963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.494360 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.745003 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 681249 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 107003 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 17615974 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 62597753 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8333886 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6378635 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13915716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4638538 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 47230 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 15838358 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 6458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 32444 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 124703 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 257 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8212062 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 760593 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1708 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 50714542 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.493810 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.745034 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 36758800 72.56% 72.56% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 702781 1.39% 73.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1220162 2.41% 76.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2515175 4.96% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1141377 2.25% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 650709 1.28% 84.86% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1886656 3.72% 88.58% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 404310 0.80% 89.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5380993 10.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 36806671 72.58% 72.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 703817 1.39% 73.96% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1220981 2.41% 76.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2510265 4.95% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1144946 2.26% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 645263 1.27% 84.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1889491 3.73% 88.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 406577 0.80% 89.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5386531 10.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 50660963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.120558 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.905706 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 18651451 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16071797 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12503703 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 383683 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3050329 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1080503 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 80301 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69737045 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 259727 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3050329 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 19796555 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3624603 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 10867059 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11733074 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1589343 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 63809564 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2981 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 320281 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 864112 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 38202 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 68239803 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 296124940 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 296072200 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 52740 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39106608 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29133195 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 434621 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 382462 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4203927 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11080202 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7013216 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 634211 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 885799 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 56015216 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 652114 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 50333331 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 120412 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18201885 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 52559759 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 132486 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 50660963 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.993533 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.617126 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 50714542 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.120641 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.906165 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18659331 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16106637 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12510231 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 383783 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3054560 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1080138 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 80287 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69798471 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 258266 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3054560 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 19806381 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 3656042 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 10855578 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11745212 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 1596769 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 63854983 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3125 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 323865 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 877546 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 38196 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 68287616 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 296328670 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 296276198 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 52472 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39108035 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 29179581 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 433573 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 381926 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4171821 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 11087265 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7018828 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 641698 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 916656 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 56054776 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 651703 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 50356280 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 119136 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18241893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52675305 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 132202 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 50714542 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.992936 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.616562 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 32144545 63.45% 63.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5530112 10.92% 74.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3775848 7.45% 81.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3605586 7.12% 88.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2986827 5.90% 94.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1557942 3.08% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 784538 1.55% 99.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 214001 0.42% 99.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 61564 0.12% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 32179059 63.45% 63.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5535325 10.91% 74.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3792419 7.48% 81.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3611748 7.12% 88.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2992147 5.90% 94.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1532229 3.02% 97.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 792020 1.56% 99.45% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 217740 0.43% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61855 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 50660963 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 50714542 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 15475 1.52% 1.52% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1190 0.12% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.63% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 748820 73.38% 75.02% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 254917 24.98% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 15740 1.54% 1.54% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1188 0.12% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 747449 73.17% 74.83% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 257163 25.17% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 18622 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 32741822 65.05% 65.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 50334 0.10% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 2 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11609954 23.07% 88.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 5911828 11.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32754833 65.05% 65.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 50290 0.10% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 764 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.18% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 11616605 23.07% 88.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 5915163 11.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 50333331 # Type of FU issued -system.cpu1.iq.rate 0.728873 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1020402 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.020273 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 152512648 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 74873900 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 44249478 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12744 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7082 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5800 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 51328452 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6659 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 264599 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 50356280 # Type of FU issued +system.cpu1.iq.rate 0.728958 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1021540 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.020286 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 152611934 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 74953147 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 44267008 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 12764 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7028 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5816 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 51352530 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6668 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 264404 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3968304 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7379 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 12210 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1474293 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3974504 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 7309 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 12272 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1480206 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 1850149 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1139663 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 1850099 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1138705 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3050329 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 2505738 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 70750 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56718238 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 255272 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11080202 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7013216 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 408861 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 28043 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3317 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 12210 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 383709 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 125709 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 509418 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 47546383 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10844490 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2786948 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3054560 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 2510034 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 71099 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 56757065 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 253770 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 11087265 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7018828 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 408322 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 28335 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3451 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 12272 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 384395 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 124639 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 509034 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 47564456 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10848097 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2791824 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 50908 # number of nop insts executed -system.cpu1.iew.exec_refs 16665607 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5805305 # Number of branches executed -system.cpu1.iew.exec_stores 5821117 # Number of stores executed -system.cpu1.iew.exec_rate 0.688516 # Inst execution rate -system.cpu1.iew.wb_sent 46287732 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 44255278 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 24264943 # num instructions producing a value -system.cpu1.iew.wb_consumers 44435618 # num instructions consuming a value +system.cpu1.iew.exec_nop 50586 # number of nop insts executed +system.cpu1.iew.exec_refs 16669887 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5808702 # Number of branches executed +system.cpu1.iew.exec_stores 5821790 # Number of stores executed +system.cpu1.iew.exec_rate 0.688543 # Inst execution rate +system.cpu1.iew.wb_sent 46305936 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 44272824 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 24255669 # num instructions producing a value +system.cpu1.iew.wb_consumers 44425528 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.640857 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.546070 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38085105 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18540440 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 519628 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 449695 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 47651856 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.799237 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.835547 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38086237 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 47701192 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.798434 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.833708 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 34686600 72.79% 72.79% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6094128 12.79% 85.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1835097 3.85% 89.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 960943 2.02% 91.45% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 825753 1.73% 93.18% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 740854 1.55% 94.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 593786 1.25% 95.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 449604 0.94% 96.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1465091 3.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 34720154 72.79% 72.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6104752 12.80% 85.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1842443 3.86% 89.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 962149 2.02% 91.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 825618 1.73% 93.19% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 737310 1.55% 94.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 600667 1.26% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 447664 0.94% 96.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1460435 3.06% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 47651856 # Number of insts commited each cycle -system.cpu1.commit.count 38085105 # Number of instructions committed +system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle +system.cpu1.commit.count 38086237 # Number of instructions committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 12650821 # Number of memory references committed -system.cpu1.commit.loads 7111898 # Number of loads committed -system.cpu1.commit.membars 148710 # Number of memory barriers committed -system.cpu1.commit.branches 4804442 # Number of branches committed +system.cpu1.commit.refs 12651383 # Number of memory references committed +system.cpu1.commit.loads 7112761 # Number of loads committed +system.cpu1.commit.membars 148646 # Number of memory barriers committed +system.cpu1.commit.branches 4805168 # Number of branches committed system.cpu1.commit.fp_insts 5744 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 34027730 # Number of committed integer instructions. -system.cpu1.commit.function_calls 433273 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1465091 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 34028190 # Number of committed integer instructions. +system.cpu1.commit.function_calls 433251 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1460435 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 102053926 # The number of ROB reads -system.cpu1.rob.rob_writes 116420763 # The number of ROB writes -system.cpu1.timesIdled 449905 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 18395406 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5095165422 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38060551 # Number of Instructions Simulated -system.cpu1.committedInsts_total 38060551 # Number of Instructions Simulated -system.cpu1.cpi 1.814382 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.814382 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551152 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551152 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 222777169 # number of integer regfile reads -system.cpu1.int_regfile_writes 47147395 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4225 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1812 # number of floating regfile writes -system.cpu1.misc_regfile_reads 77230796 # number of misc regfile reads -system.cpu1.misc_regfile_writes 323252 # number of misc regfile writes -system.cpu1.icache.replacements 485904 # number of replacements -system.cpu1.icache.tagsinuse 498.788757 # Cycle average of tags in use -system.cpu1.icache.total_refs 7675789 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 486416 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 15.780297 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74237229000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::0 498.788757 # Average occupied blocks per context +system.cpu1.rob.rob_reads 102142645 # The number of ROB reads +system.cpu1.rob.rob_writes 116493771 # The number of ROB writes +system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38061683 # Number of Instructions Simulated +system.cpu1.committedInsts_total 38061683 # Number of Instructions Simulated +system.cpu1.cpi 1.814944 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.814944 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.550981 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.550981 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads +system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads +system.cpu1.fp_regfile_writes 1800 # number of floating regfile writes +system.cpu1.misc_regfile_reads 77318861 # number of misc regfile reads +system.cpu1.misc_regfile_writes 323177 # number of misc regfile writes +system.cpu1.icache.replacements 485586 # number of replacements +system.cpu1.icache.tagsinuse 498.788681 # Cycle average of tags in use +system.cpu1.icache.total_refs 7684975 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::0 498.788681 # Average occupied blocks per context system.cpu1.icache.occ_percent::0 0.974197 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::0 7675789 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7675789 # number of ReadReq hits -system.cpu1.icache.demand_hits::0 7675789 # number of demand (read+write) hits +system.cpu1.icache.ReadReq_hits::0 7684975 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7684975 # number of ReadReq hits +system.cpu1.icache.demand_hits::0 7684975 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7675789 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::0 7675789 # number of overall hits +system.cpu1.icache.demand_hits::total 7684975 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::0 7684975 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 7675789 # number of overall hits -system.cpu1.icache.ReadReq_misses::0 527703 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527703 # number of ReadReq misses -system.cpu1.icache.demand_misses::0 527703 # number of demand (read+write) misses +system.cpu1.icache.overall_hits::total 7684975 # number of overall hits +system.cpu1.icache.ReadReq_misses::0 527035 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 527035 # number of ReadReq misses +system.cpu1.icache.demand_misses::0 527035 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527703 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::0 527703 # number of overall misses +system.cpu1.icache.demand_misses::total 527035 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::0 527035 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 527703 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency 7760328997 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency 7760328997 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency 7760328997 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::0 8203492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8203492 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::0 8203492 # number of demand (read+write) accesses +system.cpu1.icache.overall_misses::total 527035 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency 7752735997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency 7752735997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency 7752735997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::0 8212010 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8212010 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::0 8212010 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8203492 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::0 8203492 # number of overall (read+write) accesses +system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::0 8212010 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8203492 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::0 0.064327 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::0 0.064327 # miss rate for demand accesses +system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::0 0.064179 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::0 0.064179 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::0 0.064327 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::0 0.064179 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::0 14705.864846 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::0 14710.097047 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::0 14705.864846 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::0 14710.097047 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::0 14705.864846 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::0 14710.097047 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1243497 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 7446.089820 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7776.452941 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks 18536 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits 41257 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits 41257 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits 41257 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses 486446 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses 486446 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses 486446 # number of overall MSHR misses +system.cpu1.icache.writebacks 18538 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits 40914 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits 40914 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits 40914 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses 486121 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses 486121 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses 486121 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency 5802515997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency 5802515997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency 5802515997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency 5799471497 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency 5799471497 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency 5799471497 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059297 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059196 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::0 0.059297 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::0 0.059196 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::0 0.059297 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::0 0.059196 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11928.386701 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11928.386701 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11930.098673 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 272184 # number of replacements -system.cpu1.dcache.tagsinuse 444.922817 # Cycle average of tags in use -system.cpu1.dcache.total_refs 10410516 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 272526 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 38.200084 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 66749899000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::0 444.922817 # Average occupied blocks per context -system.cpu1.dcache.occ_percent::0 0.868990 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::0 7080702 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 7080702 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::0 3139041 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3139041 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::0 75297 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75297 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::0 72589 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72589 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::0 10219743 # number of demand (read+write) hits +system.cpu1.dcache.replacements 272200 # number of replacements +system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use +system.cpu1.dcache.total_refs 10416163 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::0 447.953212 # Average occupied blocks per context +system.cpu1.dcache.occ_percent::0 0.874909 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::0 7085363 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::0 3139669 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::0 75360 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 75360 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::0 72622 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72622 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::0 10225032 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10219743 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::0 10219743 # number of overall hits +system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::0 10225032 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 10219743 # number of overall hits -system.cpu1.dcache.ReadReq_misses::0 323641 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 323641 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::0 1274421 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1274421 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::0 12692 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 12692 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::0 11088 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 11088 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::0 1598062 # number of demand (read+write) misses +system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits +system.cpu1.dcache.ReadReq_misses::0 323287 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 323287 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::0 1273508 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::0 12669 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::0 11046 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::0 1596795 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1598062 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::0 1598062 # number of overall misses +system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::0 1596795 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 1598062 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency 5056918000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency 46262292366 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency 147873000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency 87994000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency 51319210366 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency 51319210366 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::0 7404343 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 7404343 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::0 4413462 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4413462 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::0 87989 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87989 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::0 83677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 83677 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::0 11817805 # number of demand (read+write) accesses +system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency 5044696500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency 46343696337 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency 148164500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency 87512500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency 51388392837 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency 51388392837 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::0 7408650 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::0 4413177 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::0 88029 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::0 83668 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::0 11821827 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11817805 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::0 11817805 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::0 11821827 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11817805 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::0 0.043710 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::0 0.288758 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.144245 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132510 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::0 0.135225 # miss rate for demand accesses +system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::0 0.043636 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::0 0.288569 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.143918 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.132022 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::0 0.135072 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::0 0.135225 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::0 0.135072 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15625.084584 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15604.390217 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::0 36300.635635 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::0 36390.581243 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11650.882446 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7935.966811 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7922.551150 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::0 32113.403839 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::0 32113.403839 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 13353050 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5461500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3087 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4325.574992 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 34134.375000 # average number of cycles each access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4235.796880 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks 223414 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits 134188 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits 1158095 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits 989 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits 1292283 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits 1292283 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses 189453 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses 116326 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses 11703 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses 11087 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses 305779 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses 305779 # number of overall MSHR misses +system.cpu1.dcache.writebacks 223077 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits 133946 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits 1157260 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits 1008 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits 1291206 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits 1291206 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses 189341 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses 116248 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses 11661 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses 11046 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses 305589 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses 305589 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 2493574500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency 3446976050 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 98971000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54655500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency 5940550550 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency 5940550550 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455171000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41503599517 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency 49958770517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025587 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_latency 2489937000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency 3452864547 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 99179500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 54297000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency 5942801547 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency 5942801547 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 8455613500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 41497603581 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency 49953217081 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025557 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026357 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.026341 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.133005 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.132468 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132498 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.132022 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::0 0.025874 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::0 0.025850 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::0 0.025874 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::0 0.025850 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13161.968932 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29632.034541 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8456.891395 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4929.692433 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 19427.594930 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8505.231112 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4915.535035 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -1375,8 +1379,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1308164258694 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1308164258694 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1308174844926 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -1391,8 +1395,8 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 55740 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 41953 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 41930 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index c84a9ea85..f906b4862 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=true time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,14 +9,13 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver -boot_cpu_frequency=500 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_loader_mem=system.nvmem boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -62,7 +62,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -126,6 +126,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -157,6 +158,7 @@ tracer=system.cpu.tracer trapLatency=13 wbDepth=1 wbWidth=8 +workload= dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side @@ -615,7 +617,6 @@ fake_mem=false pio_addr=0 pio_latency=1000 pio_size=8 -platform=system.realview ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -657,7 +658,6 @@ system=system type=A9SCU pio_addr=520093696 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[5] @@ -667,7 +667,6 @@ amba_id=0 ignore_access=false pio_addr=268451840 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[24] @@ -737,7 +736,6 @@ max_backoff_delay=10000000 min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 -platform=system.realview system=system vnc=system.vncserver dma=system.iobus.port[6] @@ -749,7 +747,6 @@ amba_id=0 ignore_access=false pio_addr=268632064 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[12] @@ -759,7 +756,6 @@ fake_mem=true pio_addr=1073741824 pio_latency=1000 pio_size=536870912 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -788,7 +784,6 @@ amba_id=0 ignore_access=false pio_addr=268513280 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[19] @@ -798,7 +793,6 @@ amba_id=0 ignore_access=false pio_addr=268517376 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[20] @@ -808,7 +802,6 @@ amba_id=0 ignore_access=false pio_addr=268521472 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[21] @@ -821,7 +814,6 @@ int_num=52 is_mouse=false pio_addr=268460032 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[7] @@ -835,7 +827,6 @@ int_num=53 is_mouse=true pio_addr=268464128 pio_latency=1000 -platform=system.realview system=system vnc=system.vncserver pio=system.iobus.port[8] @@ -846,7 +837,6 @@ fake_mem=false pio_addr=520101888 pio_latency=1000 pio_size=4095 -platform=system.realview ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -865,7 +855,6 @@ int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 pio_latency=1000 -platform=system.realview system=system pio=system.membus.port[6] @@ -875,7 +864,6 @@ amba_id=0 ignore_access=false pio_addr=268455936 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[25] @@ -884,7 +872,6 @@ type=RealViewCtrl idreg=0 pio_addr=268435456 pio_latency=1000 -platform=system.realview proc_id0=201326592 proc_id1=201327138 system=system @@ -896,7 +883,6 @@ amba_id=266289 ignore_access=false pio_addr=268529664 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[26] @@ -906,7 +892,6 @@ amba_id=0 ignore_access=false pio_addr=268492800 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[23] @@ -916,7 +901,6 @@ amba_id=0 ignore_access=false pio_addr=269357056 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[16] @@ -926,7 +910,6 @@ amba_id=0 ignore_access=true pio_addr=268439552 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[17] @@ -936,7 +919,6 @@ amba_id=0 ignore_access=false pio_addr=268488704 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[22] @@ -950,7 +932,6 @@ int_num0=36 int_num1=36 pio_addr=268505088 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[3] @@ -964,7 +945,6 @@ int_num0=37 int_num1=37 pio_addr=268509184 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[4] @@ -987,7 +967,6 @@ amba_id=0 ignore_access=false pio_addr=268476416 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[13] @@ -997,7 +976,6 @@ amba_id=0 ignore_access=false pio_addr=268480512 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[14] @@ -1007,7 +985,6 @@ amba_id=0 ignore_access=false pio_addr=268484608 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[15] @@ -1017,7 +994,6 @@ amba_id=0 ignore_access=false pio_addr=268500992 pio_latency=1000 -platform=system.realview system=system pio=system.iobus.port[18] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 231dec8b1..46d2cdea6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,14 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:21:22 -gem5 started Jan 23 2012 09:54:06 -gem5 executing on zizzer -command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM_FS/tests/opt/long/10.linux-boot/arm/linux/realview-o3 +gem5 compiled Feb 3 2012 14:00:40 +gem5 started Feb 3 2012 14:01:01 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503566110500 because m5_exit instruction encountered +Exiting @ tick 2503580880500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index ad6b1630f..b494abcbb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.503566 # Number of seconds simulated -sim_ticks 2503566110500 # Number of ticks simulated -final_tick 2503566110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503581 # Number of seconds simulated +sim_ticks 2503580880500 # Number of ticks simulated +final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76624 # Simulator instruction rate (inst/s) -host_tick_rate 2498140220 # Simulator tick rate (ticks/s) -host_mem_usage 386188 # Number of bytes of host memory used -host_seconds 1002.17 # Real time elapsed on the host -sim_insts 76790007 # Number of instructions simulated +host_inst_rate 56444 # Simulator instruction rate (inst/s) +host_tick_rate 1840259079 # Simulator tick rate (ticks/s) +host_mem_usage 413160 # Number of bytes of host memory used +host_seconds 1360.45 # Real time elapsed on the host +sim_insts 76789886 # Number of instructions simulated system.nvmem.bytes_read 64 # Number of bytes read from this memory system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory system.nvmem.bytes_written 0 # Number of bytes written to this memory @@ -18,107 +18,107 @@ system.nvmem.num_other 0 # Nu system.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) system.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) system.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read 130731152 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1101568 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585992 # Number of bytes written to this memory -system.physmem.num_reads 15117140 # Number of read requests responded to by this memory -system.physmem.num_writes 856673 # Number of write requests responded to by this memory +system.physmem.bytes_read 130729872 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1100224 # Number of instructions bytes read from this memory +system.physmem.bytes_written 9585224 # Number of bytes written to this memory +system.physmem.num_reads 15117120 # Number of read requests responded to by this memory +system.physmem.num_writes 856661 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 52217975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 440000 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3828935 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 56046910 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 119509 # number of replacements -system.l2c.tagsinuse 25929.897253 # Cycle average of tags in use -system.l2c.total_refs 1795434 # Total number of references to valid blocks. -system.l2c.sampled_refs 150343 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.942252 # Average number of references to valid blocks. +system.physmem.bw_read 52217155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 439460 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 3828606 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 56045761 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 119505 # number of replacements +system.l2c.tagsinuse 25834.929390 # Cycle average of tags in use +system.l2c.total_refs 1795685 # Total number of references to valid blocks. +system.l2c.sampled_refs 150314 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.946226 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11551.232252 # Average occupied blocks per context -system.l2c.occ_blocks::1 14378.665001 # Average occupied blocks per context -system.l2c.occ_percent::0 0.176258 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.219401 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1350292 # number of ReadReq hits -system.l2c.ReadReq_hits::1 153003 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1503295 # number of ReadReq hits -system.l2c.Writeback_hits::0 629881 # number of Writeback hits -system.l2c.Writeback_hits::total 629881 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 38 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 38 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::0 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::0 105934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 105934 # number of ReadExReq hits -system.l2c.demand_hits::0 1456226 # number of demand (read+write) hits -system.l2c.demand_hits::1 153003 # number of demand (read+write) hits -system.l2c.demand_hits::total 1609229 # number of demand (read+write) hits -system.l2c.overall_hits::0 1456226 # number of overall hits -system.l2c.overall_hits::1 153003 # number of overall hits -system.l2c.overall_hits::total 1609229 # number of overall hits -system.l2c.ReadReq_misses::0 36080 # number of ReadReq misses -system.l2c.ReadReq_misses::1 144 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36224 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 3255 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3255 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::0 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::0 140433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140433 # number of ReadExReq misses -system.l2c.demand_misses::0 176513 # number of demand (read+write) misses -system.l2c.demand_misses::1 144 # number of demand (read+write) misses -system.l2c.demand_misses::total 176657 # number of demand (read+write) misses -system.l2c.overall_misses::0 176513 # number of overall misses -system.l2c.overall_misses::1 144 # number of overall misses -system.l2c.overall_misses::total 176657 # number of overall misses -system.l2c.ReadReq_miss_latency 1894696500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 1006500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 7384268500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 9278965000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 9278965000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 1386372 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 153147 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1539519 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 629881 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 629881 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 3293 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3293 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::0 18 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.occ_blocks::0 11478.014025 # Average occupied blocks per context +system.l2c.occ_blocks::1 14356.915365 # Average occupied blocks per context +system.l2c.occ_percent::0 0.175141 # Average percentage of cache occupancy +system.l2c.occ_percent::1 0.219069 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::0 1349535 # number of ReadReq hits +system.l2c.ReadReq_hits::1 153277 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits +system.l2c.Writeback_hits::0 630148 # number of Writeback hits +system.l2c.Writeback_hits::total 630148 # number of Writeback hits +system.l2c.UpgradeReq_hits::0 47 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::0 105970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits +system.l2c.demand_hits::0 1455505 # number of demand (read+write) hits +system.l2c.demand_hits::1 153277 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits +system.l2c.overall_hits::0 1455505 # number of overall hits +system.l2c.overall_hits::1 153277 # number of overall hits +system.l2c.overall_hits::total 1608782 # number of overall hits +system.l2c.ReadReq_misses::0 36088 # number of ReadReq misses +system.l2c.ReadReq_misses::1 150 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses +system.l2c.UpgradeReq_misses::0 3252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::0 4 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::0 140397 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses +system.l2c.demand_misses::0 176485 # number of demand (read+write) misses +system.l2c.demand_misses::1 150 # number of demand (read+write) misses +system.l2c.demand_misses::total 176635 # number of demand (read+write) misses +system.l2c.overall_misses::0 176485 # number of overall misses +system.l2c.overall_misses::1 150 # number of overall misses +system.l2c.overall_misses::total 176635 # number of overall misses +system.l2c.ReadReq_miss_latency 1895542500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency 1059500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency 7383005500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency 9278548000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency 9278548000 # number of overall miss cycles +system.l2c.ReadReq_accesses::0 1385623 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 153427 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::0 630148 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::0 3299 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::0 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 1632739 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 153147 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785886 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 1632739 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 153147 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785886 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.026025 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.000940 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.026965 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.988460 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::0 0.111111 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.570015 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.108109 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.000940 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.109049 # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.108109 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.000940 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.109049 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52513.761086 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 13157614.583333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 13210128.344420 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 309.216590 # average UpgradeReq miss latency +system.l2c.demand_accesses::0 1631990 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 153427 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses +system.l2c.overall_accesses::0 1631990 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 153427 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::0 0.026045 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.000978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.027022 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::0 0.985753 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::0 0.190476 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::0 0.569869 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::0 0.108141 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.000978 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.109119 # miss rate for demand accesses +system.l2c.overall_miss_rate::0 0.108141 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.000978 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.109119 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::0 52525.562514 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 12636950 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 12689475.562514 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::0 325.799508 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52582.145934 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::0 52586.632905 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52568.167784 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 64437256.944444 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 64489825.112228 # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52568.167784 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 64437256.944444 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 64489825.112228 # average overall miss latency +system.l2c.demand_avg_miss_latency::0 52574.145111 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 61856986.666667 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 61909560.811778 # average overall miss latency +system.l2c.overall_avg_miss_latency::0 52574.145111 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 61856986.666667 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 61909560.811778 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -127,50 +127,50 @@ system.l2c.avg_blocked_cycles::no_mshrs no_value # av system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 102655 # number of writebacks +system.l2c.writebacks 102643 # number of writebacks system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits 94 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 36130 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 3255 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 140433 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 176563 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 176563 # number of overall MSHR misses +system.l2c.ReadReq_mshr_misses 36144 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 3252 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses 4 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses 140397 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses 176541 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses 176541 # number of overall MSHR misses system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 1449837500 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 131527500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency 80000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 5640075000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 7089912500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 7089912500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 131769527500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 32342636570 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 164112164070 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.026061 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.235917 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.261978 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.988460 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_latency 1450468000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency 131324500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency 160000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency 5639183500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency 7089651500 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency 7089651500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency 131770082500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency 32364127897 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency 164134210397 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.026085 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.235578 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.261663 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::0 0.985753 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.190476 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.570015 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::0 0.569869 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.108139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.152899 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 1.261038 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.108139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.152899 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 1.261038 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40128.355937 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40407.834101 # average UpgradeReq mshr miss latency +system.l2c.demand_mshr_miss_rate::0 0.108175 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.150651 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 1.258827 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::0 0.108175 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.150651 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 1.258827 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40162.034565 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40155.142923 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -185,27 +185,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 52217329 # DTB read hits -system.cpu.dtb.read_misses 90306 # DTB read misses -system.cpu.dtb.write_hits 11974176 # DTB write hits -system.cpu.dtb.write_misses 25588 # DTB write misses +system.cpu.dtb.read_hits 52219999 # DTB read hits +system.cpu.dtb.read_misses 90279 # DTB read misses +system.cpu.dtb.write_hits 11976179 # DTB write hits +system.cpu.dtb.write_misses 25577 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 5563 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 685 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4346 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 6089 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 654 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 2233 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 52307635 # DTB read accesses -system.cpu.dtb.write_accesses 11999764 # DTB write accesses +system.cpu.dtb.perms_faults 2193 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 52310278 # DTB read accesses +system.cpu.dtb.write_accesses 12001756 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 64191505 # DTB hits -system.cpu.dtb.misses 115894 # DTB misses -system.cpu.dtb.accesses 64307399 # DTB accesses -system.cpu.itb.inst_hits 14124795 # ITB inst hits -system.cpu.itb.inst_misses 9853 # ITB inst misses +system.cpu.dtb.hits 64196178 # DTB hits +system.cpu.dtb.misses 115856 # DTB misses +system.cpu.dtb.accesses 64312034 # DTB accesses +system.cpu.itb.inst_hits 14123674 # ITB inst hits +system.cpu.itb.inst_misses 9885 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -214,517 +214,517 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2606 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2599 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 7868 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 7902 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 14134648 # ITB inst accesses -system.cpu.itb.hits 14124795 # DTB hits -system.cpu.itb.misses 9853 # DTB misses -system.cpu.itb.accesses 14134648 # DTB accesses -system.cpu.numCycles 415912091 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 14133559 # ITB inst accesses +system.cpu.itb.hits 14123674 # DTB hits +system.cpu.itb.misses 9885 # DTB misses +system.cpu.itb.accesses 14133559 # DTB accesses +system.cpu.numCycles 415943429 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16206323 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12554772 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1108177 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 13916811 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 10226428 # Number of BTB hits +system.cpu.BPredUnit.lookups 16201364 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12549421 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1109380 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 13917593 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 10243002 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1423283 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 227054 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32931583 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 104747250 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16206323 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11649711 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24460631 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 7066944 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 130925 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 92852979 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 144764 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 217141 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 360 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 14116150 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1044696 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4826 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 155542524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.838034 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.183637 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1423675 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 227604 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 32912368 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 104836271 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16201364 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11666677 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24487466 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 7079059 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 131458 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 92859775 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145565 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 217503 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 362 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 14115008 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1041610 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4861 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 155569254 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.838536 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.184070 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131107701 84.29% 84.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1736645 1.12% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2606210 1.68% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3650547 2.35% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2167045 1.39% 90.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1435515 0.92% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2626627 1.69% 93.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 854151 0.55% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9358083 6.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131107551 84.28% 84.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1739904 1.12% 85.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2616632 1.68% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3657999 2.35% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2164577 1.39% 90.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1434404 0.92% 91.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2630326 1.69% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 851935 0.55% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9365926 6.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 155542524 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.038966 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.251849 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35137982 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 92713675 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 21969277 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1093477 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4628113 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2313056 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 177631 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 122001156 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 574106 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4628113 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37294552 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36817406 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49929047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20901153 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5972253 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 113826701 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4400 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 914485 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3979731 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 42252 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 118358543 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 523323093 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 523225639 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 97454 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77492718 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 40865824 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1204637 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1098724 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12304657 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21982315 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14168730 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1896802 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2281380 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 102860211 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1874616 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126873316 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 252471 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26973483 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 72956952 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 374923 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 155542524 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.815683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.505358 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 155569254 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.038951 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.252045 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35134284 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 92713878 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 21991115 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1092987 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4636990 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2313958 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 177730 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 122065816 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 573184 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4636990 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37283411 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36813700 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 49928995 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20929371 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5976787 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 113968448 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4165 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 915244 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3983499 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 42655 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 118524115 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 524000264 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 523903687 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 96577 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77492548 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 41031566 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1204512 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1098851 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12310506 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21988549 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14164932 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1902928 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2266136 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 102902284 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1875395 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126904684 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 253228 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27017748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 72978464 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 375688 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 155569254 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.815744 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.505343 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108919716 70.03% 70.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 15115277 9.72% 79.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7538109 4.85% 84.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6517896 4.19% 88.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12766129 8.21% 96.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2735746 1.76% 98.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1395145 0.90% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 422031 0.27% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132475 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108923700 70.02% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 15131938 9.73% 79.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7543329 4.85% 84.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6524442 4.19% 88.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12759852 8.20% 96.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2730334 1.76% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1400610 0.90% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 422368 0.27% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 132681 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 155542524 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 155569254 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 45891 0.52% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 6 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8417784 94.58% 95.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 436630 4.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 45526 0.51% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8417505 94.61% 95.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 433723 4.88% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.08% 0.08% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60069482 47.35% 47.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 96615 0.08% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 8 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2251 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53942685 42.52% 90.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12655733 9.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60099266 47.36% 47.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 96421 0.08% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 5 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2248 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53941927 42.51% 90.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12658279 9.97% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126873316 # Type of FU issued -system.cpu.iq.rate 0.305048 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8900311 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070151 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 418533128 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131726191 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87292108 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 24017 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13690 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10446 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 135654305 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12792 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 614767 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126904684 # Type of FU issued +system.cpu.iq.rate 0.305101 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8896761 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070106 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 418619840 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131813494 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87332577 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23940 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13540 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10418 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 135682181 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12734 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 614286 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6301517 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11128 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 32657 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2389653 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6307786 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11074 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 32675 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2385852 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34061869 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1153605 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34061916 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1151020 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4628113 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28345943 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 419499 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 104949442 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 473979 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21982315 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14168730 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1228031 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 85187 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7556 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 32657 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 850397 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 257130 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1107527 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123429779 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52914304 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3443537 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4636990 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28345844 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 418518 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 104992332 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 473238 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21988549 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14164932 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1227782 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 852505 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1109320 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 214615 # number of nop insts executed -system.cpu.iew.exec_refs 65401525 # number of memory reference insts executed -system.cpu.iew.exec_branches 11705842 # Number of branches executed -system.cpu.iew.exec_stores 12487221 # Number of stores executed -system.cpu.iew.exec_rate 0.296769 # Inst execution rate -system.cpu.iew.wb_sent 121771133 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87302554 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47043389 # num instructions producing a value -system.cpu.iew.wb_consumers 86638668 # num instructions consuming a value +system.cpu.iew.exec_nop 214653 # number of nop insts executed +system.cpu.iew.exec_refs 65406640 # number of memory reference insts executed +system.cpu.iew.exec_branches 11708135 # Number of branches executed +system.cpu.iew.exec_stores 12489378 # Number of stores executed +system.cpu.iew.exec_rate 0.296843 # Inst execution rate +system.cpu.iew.wb_sent 121811310 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87342995 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47060292 # num instructions producing a value +system.cpu.iew.wb_consumers 86666260 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.209906 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.542984 # average fanout of values written-back +system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 76940388 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 27793277 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1499693 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 977065 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 150996763 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.509550 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459324 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 76940267 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151014616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.509489 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.459114 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 122144480 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14839804 9.83% 90.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4110999 2.72% 93.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2181780 1.44% 94.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1788910 1.18% 96.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1360879 0.90% 96.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1262027 0.84% 97.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 662023 0.44% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2645861 1.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122165210 80.90% 80.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14833013 9.82% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4110348 2.72% 93.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2186082 1.45% 94.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1788351 1.18% 96.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1361296 0.90% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1264343 0.84% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 665414 0.44% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2640559 1.75% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 150996763 # Number of insts commited each cycle -system.cpu.commit.count 76940388 # Number of instructions committed +system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle +system.cpu.commit.count 76940267 # Number of instructions committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27459875 # Number of memory references committed -system.cpu.commit.loads 15680798 # Number of loads committed -system.cpu.commit.membars 413062 # Number of memory barriers committed -system.cpu.commit.branches 9891038 # Number of branches committed +system.cpu.commit.refs 27459843 # Number of memory references committed +system.cpu.commit.loads 15680763 # Number of loads committed +system.cpu.commit.membars 413065 # Number of memory barriers committed +system.cpu.commit.branches 9891047 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68493475 # Number of committed integer instructions. -system.cpu.commit.function_calls 995603 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2645861 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68493330 # Number of committed integer instructions. +system.cpu.commit.function_calls 995601 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2640559 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 251328068 # The number of ROB reads -system.cpu.rob.rob_writes 214226863 # The number of ROB writes -system.cpu.timesIdled 1877486 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260369567 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591132146 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 76790007 # Number of Instructions Simulated -system.cpu.committedInsts_total 76790007 # Number of Instructions Simulated -system.cpu.cpi 5.416227 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.416227 # CPI: Total CPI of All Threads -system.cpu.ipc 0.184630 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.184630 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 559625786 # number of integer regfile reads -system.cpu.int_regfile_writes 89694789 # number of integer regfile writes -system.cpu.fp_regfile_reads 8322 # number of floating regfile reads -system.cpu.fp_regfile_writes 2832 # number of floating regfile writes -system.cpu.misc_regfile_reads 137256850 # number of misc regfile reads -system.cpu.misc_regfile_writes 912282 # number of misc regfile writes -system.cpu.icache.replacements 991618 # number of replacements -system.cpu.icache.tagsinuse 511.615309 # Cycle average of tags in use -system.cpu.icache.total_refs 13036767 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992130 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 13.140180 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 251393815 # The number of ROB reads +system.cpu.rob.rob_writes 214319630 # The number of ROB writes +system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 76789886 # Number of Instructions Simulated +system.cpu.committedInsts_total 76789886 # Number of Instructions Simulated +system.cpu.cpi 5.416643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.416643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.184616 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.184616 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 559798057 # number of integer regfile reads +system.cpu.int_regfile_writes 89741069 # number of integer regfile writes +system.cpu.fp_regfile_reads 8257 # number of floating regfile reads +system.cpu.fp_regfile_writes 2814 # number of floating regfile writes +system.cpu.misc_regfile_reads 137366935 # number of misc regfile reads +system.cpu.misc_regfile_writes 912292 # number of misc regfile writes +system.cpu.icache.replacements 991177 # number of replacements +system.cpu.icache.tagsinuse 511.615293 # Cycle average of tags in use +system.cpu.icache.total_refs 13035657 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 511.615309 # Average occupied blocks per context +system.cpu.icache.occ_blocks::0 511.615293 # Average occupied blocks per context system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 13036767 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13036767 # number of ReadReq hits -system.cpu.icache.demand_hits::0 13036767 # number of demand (read+write) hits +system.cpu.icache.ReadReq_hits::0 13035657 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13035657 # number of ReadReq hits +system.cpu.icache.demand_hits::0 13035657 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13036767 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 13036767 # number of overall hits +system.cpu.icache.demand_hits::total 13035657 # number of demand (read+write) hits +system.cpu.icache.overall_hits::0 13035657 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 13036767 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1079261 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1079261 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1079261 # number of demand (read+write) misses +system.cpu.icache.overall_hits::total 13035657 # number of overall hits +system.cpu.icache.ReadReq_misses::0 1079227 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1079227 # number of ReadReq misses +system.cpu.icache.demand_misses::0 1079227 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1079261 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1079261 # number of overall misses +system.cpu.icache.demand_misses::total 1079227 # number of demand (read+write) misses +system.cpu.icache.overall_misses::0 1079227 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1079261 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15910722989 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15910722989 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15910722989 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 14116028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14116028 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 14116028 # number of demand (read+write) accesses +system.cpu.icache.overall_misses::total 1079227 # number of overall misses +system.cpu.icache.ReadReq_miss_latency 15906225491 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency 15906225491 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency 15906225491 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::0 14114884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14114884 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::0 14114884 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14116028 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 14116028 # number of overall (read+write) accesses +system.cpu.icache.demand_accesses::total 14114884 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::0 14114884 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14116028 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076456 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076456 # miss rate for demand accesses +system.cpu.icache.overall_accesses::total 14114884 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::0 0.076460 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::0 0.076460 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076456 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::0 0.076460 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14742.238429 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14742.238429 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::0 14738.535536 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14742.238429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::0 14738.535536 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2475992 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 2390996 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 368 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 341 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6728.239130 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7011.718475 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 57161 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 87101 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 87101 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 87101 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 992160 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 992160 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 992160 # number of overall MSHR misses +system.cpu.icache.writebacks 57255 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits 87505 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits 87505 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits 87505 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses 991722 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses 991722 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses 991722 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11856676492 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11856676492 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11856676492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency 11850340996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency 11850340996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency 11850340996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency 6359500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 6359500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070286 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.070261 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.070286 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::0 0.070261 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.070286 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::0 0.070261 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11950.367372 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11950.367372 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643915 # number of replacements +system.cpu.dcache.replacements 643728 # number of replacements system.cpu.dcache.tagsinuse 511.991681 # Cycle average of tags in use -system.cpu.dcache.total_refs 22265831 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644427 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 34.551363 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 22270301 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644240 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 34.568330 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 48663000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::0 511.991681 # Average occupied blocks per context system.cpu.dcache.occ_percent::0 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 14412375 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 14412375 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 7264610 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7264610 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 299966 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 299966 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 285484 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285484 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 21676985 # number of demand (read+write) hits +system.cpu.dcache.ReadReq_hits::0 14416609 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 14416609 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::0 7264899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7264899 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::0 299899 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 299899 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::0 285488 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285488 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::0 21681508 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21676985 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 21676985 # number of overall hits +system.cpu.dcache.demand_hits::total 21681508 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::0 21681508 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 21676985 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 724119 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 724119 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 2966647 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2966647 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 13487 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13487 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::0 18 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::0 3690766 # number of demand (read+write) misses +system.cpu.dcache.overall_hits::total 21681508 # number of overall hits +system.cpu.dcache.ReadReq_misses::0 722544 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 722544 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::0 2966373 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2966373 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::0 13502 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13502 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::0 21 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::0 3688917 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3690766 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 3690766 # number of overall misses +system.cpu.dcache.demand_misses::total 3688917 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::0 3688917 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3690766 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 10885048500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 110351571736 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 219032000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency 343000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency 121236620236 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 121236620236 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 15136494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 15136494 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 10231257 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10231257 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 313453 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 313453 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 285502 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285502 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 25367751 # number of demand (read+write) accesses +system.cpu.dcache.overall_misses::total 3688917 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency 10864923000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency 110367485740 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency 219139000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency 467500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency 121232408740 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency 121232408740 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::0 15139153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 15139153 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::0 10231272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10231272 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::0 313401 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 313401 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::0 285509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285509 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::0 25370425 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 25367751 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 25367751 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::total 25370425 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::0 25370425 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 25367751 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.047839 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.289959 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043027 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000063 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::0 0.145490 # miss rate for demand accesses +system.cpu.dcache.overall_accesses::total 25370425 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::0 0.047727 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::0 0.289932 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.043082 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000074 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::0 0.145402 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.145490 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::0 0.145402 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 15032.126626 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 37197.405602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16240.231334 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::0 19055.555556 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 32848.633654 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::0 32863.956749 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 32848.633654 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::0 32863.956749 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 16787932 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7490000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2999 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 273 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5597.843281 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27435.897436 # average number of cycles each access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 16658435 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7526500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2975 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 277 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5599.473950 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 572720 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 338008 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 2717083 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 3055091 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 3055091 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 386111 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 249564 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 12045 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses 18 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses 635675 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 635675 # number of overall MSHR misses +system.cpu.dcache.writebacks 572893 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits 336628 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits 2716799 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits 3053427 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits 3053427 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses 385916 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses 249574 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses 12049 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses 21 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses 635490 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses 635490 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5247540500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8926098932 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161654000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency 282500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 14173639432 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 14173639432 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147158749000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42258178710 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 189416927710 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025509 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency 5245615500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency 8926036935 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161663500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency 398500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency 14171652435 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency 14171652435 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42287348315 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025491 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038427 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000074 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.025058 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::0 0.025048 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.025058 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::0 0.025048 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13590.756285 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35766.772980 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13420.838522 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 15694.444444 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 22296.990494 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency @@ -785,8 +785,8 @@ system.iocache.overall_mshr_misses 0 # nu system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_uncacheable_latency 1307898920918 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency 1307898920918 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency 1307927966543 # number of overall MSHR uncacheable cycles system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses @@ -801,6 +801,6 @@ system.iocache.mshr_cap_events 0 # nu system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 87985 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |