diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-06-27 05:49:51 -0400 |
| commit | 5a15909bac241dc795c691d49c4e2c68cab745f4 (patch) | |
| tree | d0ae694e320c725ed8116943c7179516567279f3 /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | ac515d7a9b131ffc9e128bd209fcddb2f383808b (diff) | |
| download | gem5-5a15909bac241dc795c691d49c4e2c68cab745f4.tar.xz | |
stats: Update stats for monitor, cache and bus changes
This patch removes the sparse histogram total from the CommMonitor
stats. It also bumps the stats after the unit fixes in the atomic
cache access. Lastly, it updates the stats to match the new port
ordering. All numbers are the same, and the only thing that changes is
which master corresponds to what port index.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
6 files changed, 8490 insertions, 8497 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index bab672da1..03035c465 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534279 # Number of seconds simulated -sim_ticks 2534279149500 # Number of ticks simulated -final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534332 # Number of seconds simulated +sim_ticks 2534332336000 # Number of ticks simulated +final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43780 # Simulator instruction rate (inst/s) -host_op_rate 56332 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1839722930 # Simulator tick rate (ticks/s) -host_mem_usage 400528 # Number of bytes of host memory used -host_seconds 1377.53 # Real time elapsed on the host -sim_insts 60307893 # Number of instructions simulated -sim_ops 77599512 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +host_inst_rate 47356 # Simulator instruction rate (inst/s) +host_op_rate 60934 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1990051953 # Simulator tick rate (ticks/s) +host_mem_usage 400524 # Number of bytes of host memory used +host_seconds 1273.50 # Real time elapsed on the host +sim_insts 60307773 # Number of instructions simulated +sim_ops 77599321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory -system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory +system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15098054 # Total number of read requests seen -system.physmem.writeReqs 813133 # Total number of write requests seen -system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966275456 # Total number of bytes read from memory -system.physmem.bytesWritten 52040512 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15101237 # Total number of read requests seen +system.physmem.writeReqs 813162 # Total number of write requests seen +system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966479168 # Total number of bytes read from memory +system.physmem.bytesWritten 52042368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534279100000 # Total gap between requests +system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534332242000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14943424 # Categorize read packet sizes +system.physmem.readPktSize::3 14946576 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154594 # Categorize read packet sizes +system.physmem.readPktSize::6 154625 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59115 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59144 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,326 +139,316 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation -system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests -system.physmem.totBusLat 75488575000 # Total cycles spent in databus access -system.physmem.totBankLat 15730536250 # Total cycles spent in bank access -system.physmem.avgQLat 23521.25 # Average queueing delay per request -system.physmem.avgBankLat 1041.92 # Average bank access latency per request +system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation +system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests +system.physmem.totBusLat 75504790000 # Total cycles spent in databus access +system.physmem.totBankLat 15713238750 # Total cycles spent in bank access +system.physmem.avgQLat 23320.54 # Average queueing delay per request +system.physmem.avgBankLat 1040.55 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29563.16 # Average memory access latency -system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 29361.08 # Average memory access latency +system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 11.71 # Average write queue length over time -system.physmem.readRowHits 15070837 # Number of row buffer hits during reads -system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 10.77 # Average write queue length over time +system.physmem.readRowHits 15074158 # Number of row buffer hits during reads +system.physmem.writeRowHits 797610 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes -system.physmem.avgGap 159276.56 # Average gap between requests +system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes +system.physmem.avgGap 159247.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -471,60 +461,60 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54705448 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16150672 # Transaction distribution -system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.throughput 54715776 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16153842 # Transaction distribution +system.membus.trans_dist::ReadResp 16153842 # Transaction distribution system.membus.trans_dist::WriteReq 763336 # Transaction distribution system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59115 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution -system.membus.trans_dist::ReadExReq 131424 # Transaction distribution -system.membus.trans_dist::ReadExResp 131424 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution +system.membus.trans_dist::ReadExReq 131438 # Transaction distribution +system.membus.trans_dist::ReadExResp 131438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138667961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -532,13 +522,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48115298 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution -system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.throughput 48124265 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution +system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution system.iobus.trans_dist::WriteReq 8158 # Transaction distribution system.iobus.trans_dist::WriteResp 8158 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -560,11 +550,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -586,10 +576,10 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -611,11 +601,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +627,12 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121962881 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -686,26 +676,26 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14673159 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits +system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu.branchPred.lookups 14663186 # Number of BP lookups +system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 14987453 # DTB read hits +system.cpu.checker.dtb.read_hits 14987443 # DTB read hits system.cpu.checker.dtb.read_misses 7307 # DTB read misses -system.cpu.checker.dtb.write_hits 11227781 # DTB write hits +system.cpu.checker.dtb.write_hits 11227745 # DTB write hits system.cpu.checker.dtb.write_misses 2189 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -716,13 +706,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 178 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 14994760 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229970 # DTB write accesses +system.cpu.checker.dtb.read_accesses 14994750 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229934 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26215234 # DTB hits +system.cpu.checker.dtb.hits 26215188 # DTB hits system.cpu.checker.dtb.misses 9496 # DTB misses -system.cpu.checker.dtb.accesses 26224730 # DTB accesses -system.cpu.checker.itb.inst_hits 61481893 # ITB inst hits +system.cpu.checker.dtb.accesses 26224684 # DTB accesses +system.cpu.checker.itb.inst_hits 61481774 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -739,36 +729,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61486364 # ITB inst accesses -system.cpu.checker.itb.hits 61481893 # DTB hits +system.cpu.checker.itb.inst_accesses 61486245 # ITB inst accesses +system.cpu.checker.itb.hits 61481774 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61486364 # DTB accesses -system.cpu.checker.numCycles 77885319 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61486245 # DTB accesses +system.cpu.checker.numCycles 77885129 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51397173 # DTB read hits -system.cpu.dtb.read_misses 63986 # DTB read misses -system.cpu.dtb.write_hits 11699533 # DTB write hits -system.cpu.dtb.write_misses 15890 # DTB write misses +system.cpu.dtb.read_hits 51389107 # DTB read hits +system.cpu.dtb.read_misses 64168 # DTB read misses +system.cpu.dtb.write_hits 11699261 # DTB write hits +system.cpu.dtb.write_misses 15977 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6549 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6541 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51461159 # DTB read accesses -system.cpu.dtb.write_accesses 11715423 # DTB write accesses +system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51453275 # DTB read accesses +system.cpu.dtb.write_accesses 11715238 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096706 # DTB hits -system.cpu.dtb.misses 79876 # DTB misses -system.cpu.dtb.accesses 63176582 # DTB accesses -system.cpu.itb.inst_hits 12260245 # ITB inst hits -system.cpu.itb.inst_misses 11468 # ITB inst misses +system.cpu.dtb.hits 63088368 # DTB hits +system.cpu.dtb.misses 80145 # DTB misses +system.cpu.dtb.accesses 63168513 # DTB accesses +system.cpu.itb.inst_hits 12244686 # ITB inst hits +system.cpu.itb.inst_misses 11272 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -777,148 +767,148 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4980 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4958 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12271713 # ITB inst accesses -system.cpu.itb.hits 12260245 # DTB hits -system.cpu.itb.misses 11468 # DTB misses -system.cpu.itb.accesses 12271713 # DTB accesses -system.cpu.numCycles 475189978 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12255958 # ITB inst accesses +system.cpu.itb.hits 12244686 # DTB hits +system.cpu.itb.misses 11272 # DTB misses +system.cpu.itb.accesses 12255958 # DTB accesses +system.cpu.numCycles 475312551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued @@ -931,397 +921,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued -system.cpu.iq.rate 0.261620 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued +system.cpu.iq.rate 0.261503 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221659 # number of nop insts executed -system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed -system.cpu.iew.exec_branches 11560329 # Number of branches executed -system.cpu.iew.exec_stores 12210910 # Number of stores executed -system.cpu.iew.exec_rate 0.255996 # Inst execution rate -system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268053 # num instructions producing a value -system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value +system.cpu.iew.exec_nop 222537 # number of nop insts executed +system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed +system.cpu.iew.exec_branches 11556571 # Number of branches executed +system.cpu.iew.exec_stores 12211191 # Number of stores executed +system.cpu.iew.exec_rate 0.255895 # Inst execution rate +system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268516 # num instructions producing a value +system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458274 # Number of instructions committed -system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458154 # Number of instructions committed +system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386690 # Number of memory references committed -system.cpu.commit.loads 15654575 # Number of loads committed -system.cpu.commit.membars 403596 # Number of memory barriers committed -system.cpu.commit.branches 9961373 # Number of branches committed +system.cpu.commit.refs 27386643 # Number of memory references committed +system.cpu.commit.loads 15654562 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961356 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. -system.cpu.commit.function_calls 991268 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. +system.cpu.commit.function_calls 991265 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243879966 # The number of ROB reads -system.cpu.rob.rob_writes 201882555 # The number of ROB writes -system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307893 # Number of Instructions Simulated -system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated -system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550704703 # number of integer regfile reads -system.cpu.int_regfile_writes 88578313 # number of integer regfile writes -system.cpu.fp_regfile_reads 8302 # number of floating regfile reads -system.cpu.fp_regfile_writes 2882 # number of floating regfile writes -system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.rob.rob_reads 243752783 # The number of ROB reads +system.cpu.rob.rob_writes 201807644 # The number of ROB writes +system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307773 # Number of Instructions Simulated +system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated +system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550637147 # number of integer regfile reads +system.cpu.int_regfile_writes 88566596 # number of integer regfile writes +system.cpu.fp_regfile_reads 8370 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 980157 # number of replacements -system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use -system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits -system.cpu.icache.overall_hits::total 11196212 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses -system.cpu.icache.overall_misses::total 1060409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.086517 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.086517 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.086517 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.086517 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13445.472446 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13445.472446 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13445.472446 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13445.472446 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13445.472446 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked +system.cpu.icache.tags.replacements 980590 # number of replacements +system.cpu.icache.tags.tagsinuse 511.580932 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 11180201 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 981102 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.395554 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 6861342250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.580932 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999182 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999182 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11180201 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11180201 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11180201 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11180201 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11180201 # number of overall hits +system.cpu.icache.overall_hits::total 11180201 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1060929 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1060929 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1060929 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1060929 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1060929 # number of overall misses +system.cpu.icache.overall_misses::total 1060929 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14286603183 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14286603183 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14286603183 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14286603183 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14286603183 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14286603183 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12241130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12241130 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12241130 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12241130 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12241130 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12241130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086669 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.086669 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.086669 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.086669 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.086669 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.086669 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13466.125615 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13466.125615 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13466.125615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13466.125615 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13466.125615 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8464 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 372 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 385 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.473118 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 21.984416 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79698 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79698 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79698 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79698 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79698 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79698 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980711 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980711 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980711 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980711 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980711 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980711 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11583440602 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11583440602 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11583440602 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11583440602 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11583440602 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11583440602 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 9547000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 9547000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 9547000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 9547000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.080015 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.080015 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26354291876 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26354291876 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 7076250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193278593876 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193285670126 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016014 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985165 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985165 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.176471 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541421 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000839 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000194 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012604 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1442,161 +1432,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643353 # number of replacements -system.cpu.dcache.tagsinuse 511.992092 # Cycle average of tags in use -system.cpu.dcache.total_refs 21505591 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643865 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.400777 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 48193000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.992092 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999985 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13753583 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13753583 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258444 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258444 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242854 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242854 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21012027 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21012027 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21012027 # 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number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256439 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256439 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247618 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24705277 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24705277 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24705277 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24705277 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050837 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050837 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289871 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289871 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052831 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052831 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000069 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149742 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149742 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149742 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149742 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13687.983840 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13687.983840 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32140 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 25391 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2640 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 284 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.174242 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 89.404930 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607669 # number of writebacks -system.cpu.dcache.writebacks::total 607669 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351798 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351798 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2715004 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2715004 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1354 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066802 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066802 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066802 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066802 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385700 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385700 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248938 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248938 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12185 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 15 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 15 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634638 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634638 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4965601859 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4965601859 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10500826931 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10500826931 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144262002 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144262002 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15466428790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15466428790 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15466428790 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15466428790 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182333907000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182333907000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35770060494 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35770060494 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218103967494 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 218103967494 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026616 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024352 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000061 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025680 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025680 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025680 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12874.259422 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12874.259422 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42182.498980 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42182.498980 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11839.310792 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11839.310792 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13400 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24370.473861 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24370.473861 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607541 # number of writebacks +system.cpu.dcache.writebacks::total 607541 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 350669 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 350669 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714279 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3064948 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3064948 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3064948 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3064948 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385593 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385593 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248882 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12204 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12204 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634475 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634475 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634475 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634475 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1604,12 +1594,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1618,16 +1608,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 7f7f9360b..5451e0c81 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.613797 # Number of seconds simulated -sim_ticks 2613796876500 # Number of ticks simulated -final_tick 2613796876500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.114023 # Number of seconds simulated +sim_ticks 1114022852000 # Number of ticks simulated +final_tick 1114022852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54493 # Simulator instruction rate (inst/s) -host_op_rate 70162 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2268463215 # Simulator tick rate (ticks/s) -host_mem_usage 404628 # Number of bytes of host memory used -host_seconds 1152.23 # Real time elapsed on the host -sim_insts 62788171 # Number of instructions simulated -sim_ops 80843130 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory +host_inst_rate 79652 # Simulator instruction rate (inst/s) +host_op_rate 102538 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1440387686 # Simulator tick rate (ticks/s) +host_mem_usage 404604 # Number of bytes of host memory used +host_seconds 773.42 # Real time elapsed on the host +sim_insts 61604368 # Number of instructions simulated +sim_ops 79304455 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4352820 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5278640 # Number of bytes read from this memory -system.physmem.bytes_read::total 131565412 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821440 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4275200 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 409408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4367220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 406208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory +system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4263872 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory +system.physmem.bytes_written::total 7291216 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68085 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82505 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302272 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66800 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6397 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6347 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66623 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824084 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46335096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 163147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2019530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50334979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151124 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 163147 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314271 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1635628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1152399 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2794531 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1635628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46335096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671828 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 441 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 163147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3171928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53129510 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302272 # Total number of read requests seen -system.physmem.writeReqs 824084 # Total number of write requests seen -system.physmem.cpureqs 244248 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979345408 # Total number of bytes read from memory -system.physmem.bytesWritten 52741376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131565412 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7304336 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 446 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14097 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956408 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956129 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956336 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956715 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 957144 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956669 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 956165 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955908 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956711 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956880 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955935 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955453 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956251 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956326 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956540 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 956256 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49946 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49763 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51937 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 52171 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 52441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51960 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51720 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51713 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51876 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 52086 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51540 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51490 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51756 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51508 # Track writes on a per bank basis +system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823459 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43768208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 367504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3920225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 364632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4710438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53132845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 367504 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 364632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 732136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3827455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15260 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2702228 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6544943 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3827455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43768208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 367504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3935485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 804 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 364632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7412667 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59677788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257953 # Total number of read requests seen +system.physmem.writeReqs 823459 # Total number of write requests seen +system.physmem.cpureqs 242171 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508992 # Total number of bytes read from memory +system.physmem.bytesWritten 52701376 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7291216 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12548 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391121 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391049 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 391102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391825 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 391535 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 391243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391065 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 391482 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390728 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 390299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 390904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 391045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391022 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49919 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49928 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51967 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51963 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 52290 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51965 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51872 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51692 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51949 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51308 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51134 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51585 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51529 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32582 # Number of times wr buffer was full causing retry -system.physmem.totGap 2613795718500 # Total gap between requests +system.physmem.numWrRetry 32580 # Number of times wr buffer was full causing retry +system.physmem.totGap 1114021721000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes -system.physmem.readPktSize::3 15138816 # Categorize read packet sizes +system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163351 # Categorize read packet sizes +system.physmem.readPktSize::6 163000 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 757284 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66800 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1071823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1000587 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1004460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3729147 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2791599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2788638 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2744704 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17899 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28056 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27838 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13794 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6509 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66623 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 508306 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 436400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 409055 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1494610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1111724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1109849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1096192 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 9300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 11963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 16960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 11777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 8816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8727 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 12128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5024 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -156,350 +156,366 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2919 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32792 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32644 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32605 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48021 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 21491.760022 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1412.636943 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31347.507834 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 10706 22.29% 22.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 4255 8.86% 31.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2654 5.53% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 2034 4.24% 40.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1364 2.84% 43.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1232 2.57% 46.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 971 2.02% 48.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 916 1.91% 50.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 629 1.31% 51.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 621 1.29% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 497 1.03% 53.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 447 0.93% 54.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 308 0.64% 55.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 288 0.60% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 206 0.43% 56.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 291 0.61% 57.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 124 0.26% 57.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 166 0.35% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 102 0.21% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 142 0.30% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 76 0.16% 58.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 430 0.90% 59.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 2116 4.41% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 511 1.06% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 96 0.20% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 187 0.39% 65.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 61 0.13% 65.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 129 0.27% 65.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 42 0.09% 65.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 82 0.17% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 32 0.07% 66.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 81 0.17% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 30 0.06% 66.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 40 0.08% 66.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 20 0.04% 66.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 38 0.08% 66.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 8 0.02% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 24 0.05% 66.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 13 0.03% 66.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 21 0.04% 66.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 4 0.01% 66.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 15 0.03% 66.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 7 0.01% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 25 0.05% 66.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 10 0.02% 66.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 14 0.03% 66.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 5 0.01% 66.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 16 0.03% 66.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 3 0.01% 66.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 10 0.02% 66.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 6 0.01% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 12 0.02% 66.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 12 0.02% 66.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 7 0.01% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 8 0.02% 66.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 5 0.01% 66.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 6 0.01% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 4 0.01% 66.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 10 0.02% 67.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 8 0.02% 67.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 9 0.02% 67.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 7 0.01% 67.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 36 0.07% 67.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 3 0.01% 67.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 8 0.02% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 3 0.01% 67.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 8 0.02% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 1 0.00% 67.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 7 0.01% 67.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 1 0.00% 67.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 5 0.01% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 4 0.01% 67.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 2 0.00% 67.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 3 0.01% 67.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 3 0.01% 67.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 10 0.02% 67.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 3 0.01% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 3 0.01% 67.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 2 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 1 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 67.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 2 0.00% 67.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 3 0.01% 67.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 4 0.01% 67.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 2 0.00% 67.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 5 0.01% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 2 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 1 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 67.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 7 0.01% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 4 0.01% 67.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.00% 67.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 2 0.00% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 67.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 1 0.00% 67.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.00% 67.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 13 0.03% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 6 0.01% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 1 0.00% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 3 0.01% 67.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 5 0.01% 67.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7263 3 0.01% 67.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 2 0.00% 67.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 6 0.01% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 1 0.00% 67.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 4 0.01% 67.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 1 0.00% 67.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 4 0.01% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 67.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 6 0.01% 67.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 67.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 6 0.01% 67.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 67.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 320 0.67% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8479 2 0.00% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 3 0.01% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 2 0.00% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9439 1 0.00% 68.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 3 0.01% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9759 1 0.00% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9920-9951 1 0.00% 68.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 16 0.03% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10463 1 0.00% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10783 1 0.00% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 4 0.01% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11359 1 0.00% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12895 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12959 1 0.00% 68.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13855 1 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14111 1 0.00% 68.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 1 0.00% 68.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 2 0.00% 68.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14879 2 0.00% 68.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 2 0.00% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15455 1 0.00% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16159 2 0.00% 68.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 68.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 1 0.00% 68.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 2 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 1 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 1 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 1 0.00% 68.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17823 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17887 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 1 0.00% 68.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19072-19103 1 0.00% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 3 0.01% 68.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 1 0.00% 68.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 1 0.00% 68.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 15 0.03% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20639 1 0.00% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 4 0.01% 68.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22303 2 0.00% 68.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 1 0.00% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 3 0.01% 68.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 3 0.01% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23360-23391 1 0.00% 68.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 3 0.01% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23872-23903 1 0.00% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 2 0.00% 68.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 1 0.00% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 3 0.01% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24863 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25119 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 1 0.00% 68.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25951 1 0.00% 68.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 2 0.00% 68.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 2 0.00% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 2 0.00% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27167 1 0.00% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27423 2 0.00% 68.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27584-27615 1 0.00% 68.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 3 0.01% 68.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28191 1 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 2 0.00% 68.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 4 0.01% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 68.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 2 0.00% 68.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 68.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 2 0.00% 68.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 7 0.01% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31519 1 0.00% 68.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 3 0.01% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 68.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 3 0.01% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33055 3 0.01% 68.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 2 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 1 0.00% 68.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 55 0.11% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33984-34015 1 0.00% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34079 1 0.00% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 2 0.00% 68.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35359 1 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35968-35999 1 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36127 2 0.00% 68.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36480-36511 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36639 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38175 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39199 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39263 1 0.00% 68.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39616-39647 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40384-40415 1 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41247 2 0.00% 68.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 2 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42271 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42719 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42783 1 0.00% 68.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43039 1 0.00% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44063 3 0.01% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44416-44447 1 0.00% 68.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44703 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46623 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46943 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-47007 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 68.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49408-49439 2 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50719 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50880-50911 1 0.00% 68.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 2 0.00% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 2 0.00% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52608-52639 1 0.00% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54815 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55296-55327 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::55616-55647 1 0.00% 68.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56095 1 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57088-57119 2 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58143 1 0.00% 68.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59584-59615 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59648-59679 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60447 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61184-61215 1 0.00% 68.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61568-61599 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61952-61983 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62976-63007 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64064-64095 1 0.00% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64543 1 0.00% 68.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65055 25 0.05% 68.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65088-65119 6 0.01% 68.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 7 0.01% 68.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 19 0.04% 68.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65439 7 0.01% 68.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 18 0.04% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14562 30.32% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::97536-97567 1 0.00% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::103680-103711 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130207 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130624-130655 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130688-130719 1 0.00% 99.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 321 0.67% 99.96% # Bytes accessed per row activation +system.physmem.wrQLenPdf::0 2907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32793 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32597 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11677.106800 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 598.829081 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 25969.144286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 10478 27.00% 27.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 4256 10.97% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2718 7.00% 44.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 2024 5.22% 50.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1422 3.66% 53.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1213 3.13% 56.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 997 2.57% 59.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 905 2.33% 61.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 654 1.69% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 573 1.48% 65.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 456 1.17% 66.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 470 1.21% 67.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 308 0.79% 68.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 261 0.67% 68.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 192 0.49% 69.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 284 0.73% 70.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 136 0.35% 70.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 144 0.37% 70.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 111 0.29% 71.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 147 0.38% 71.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 83 0.21% 71.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 412 1.06% 72.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1956 5.04% 77.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 510 1.31% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 94 0.24% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 178 0.46% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 53 0.14% 79.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 122 0.31% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 38 0.10% 80.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 83 0.21% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 40 0.10% 80.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 68 0.18% 80.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 23 0.06% 80.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 47 0.12% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 17 0.04% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 43 0.11% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 13 0.03% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 28 0.07% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 13 0.03% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 25 0.06% 81.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 10 0.03% 81.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 18 0.05% 81.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 7 0.02% 81.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 19 0.05% 81.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 4 0.01% 81.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 20 0.05% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.02% 81.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 20 0.05% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 6 0.02% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 9 0.02% 81.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 7 0.02% 81.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 18 0.05% 81.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 81.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 11 0.03% 81.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 6 0.02% 81.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 12 0.03% 81.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.02% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 2 0.01% 81.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 6 0.02% 81.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 7 0.02% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 5 0.01% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 10 0.03% 81.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 2 0.01% 81.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 40 0.10% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 1 0.00% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 7 0.02% 82.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 2 0.01% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 5 0.01% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 3 0.01% 82.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 4 0.01% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 3 0.01% 82.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 9 0.02% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 2 0.01% 82.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 2 0.01% 82.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5087 1 0.00% 82.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 7 0.02% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 4 0.01% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.01% 82.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 2 0.01% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.01% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 2 0.01% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 2 0.01% 82.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5599 3 0.01% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 3 0.01% 82.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 2 0.01% 82.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 1 0.00% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 2 0.01% 82.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 2 0.01% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 3 0.01% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 2 0.01% 82.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 5 0.01% 82.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 3 0.01% 82.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 4 0.01% 82.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.01% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 4 0.01% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 1 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 82.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 1 0.00% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.01% 82.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 2 0.01% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 14 0.04% 82.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 3 0.01% 82.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 3 0.01% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 2 0.01% 82.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 82.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 3 0.01% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7263 1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 6 0.02% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 82.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 4 0.01% 82.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.02% 82.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 2 0.01% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 2 0.01% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 2 0.01% 82.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 7 0.02% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 82.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 7 0.02% 82.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 316 0.81% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8256-8287 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 2 0.01% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 5 0.01% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9344-9375 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9503 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9664-9695 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-10015 2 0.01% 83.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 15 0.04% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10368-10399 1 0.00% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 1 0.00% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10783 1 0.00% 83.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 3 0.01% 83.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 3 0.01% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 2 0.01% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12063 1 0.00% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 5 0.01% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 83.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 2 0.01% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12864-12895 1 0.00% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 83.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.01% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13504-13535 1 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13599 1 0.00% 83.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 4 0.01% 83.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15135 3 0.01% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 1 0.00% 83.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15424-15455 1 0.00% 83.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15744-15775 1 0.00% 83.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16671 3 0.01% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16927 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17183 1 0.00% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 1 0.00% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17344-17375 1 0.00% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 2 0.01% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17695 2 0.01% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17728-17759 1 0.00% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17984-18015 1 0.00% 83.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18207 3 0.01% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 83.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18560-18591 1 0.00% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 2 0.01% 83.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 2 0.01% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 1 0.00% 83.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 4 0.01% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19615 1 0.00% 83.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19999 3 0.01% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20096-20127 1 0.00% 83.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20255 1 0.00% 83.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 12 0.03% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20767 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 1 0.00% 83.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 2 0.01% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21791 1 0.00% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21952-21983 2 0.01% 83.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22047 1 0.00% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 4 0.01% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22656-22687 1 0.00% 83.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22784-22815 3 0.01% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23327 1 0.00% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 83.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24031 1 0.00% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 2 0.01% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24192-24223 1 0.00% 83.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 1 0.00% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 2 0.01% 83.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24704-24735 2 0.01% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25375 1 0.00% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25408-25439 1 0.00% 83.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.01% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 1 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26079 1 0.00% 83.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 4 0.01% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26335 1 0.00% 83.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26399 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 1 0.00% 83.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27167 3 0.01% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27423 2 0.01% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27456-27487 1 0.00% 83.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 2 0.01% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 83.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 1 0.00% 83.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 2 0.01% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30495 1 0.00% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30528-30559 1 0.00% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 3 0.01% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30943 1 0.00% 83.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 2 0.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31040-31071 1 0.00% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.01% 83.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31808-31839 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32192-32223 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32287 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32384-32415 1 0.00% 83.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 2 0.01% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32799 2 0.01% 83.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33344-33375 1 0.00% 83.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 5 0.01% 83.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33631 2 0.01% 83.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 3 0.01% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33759 2 0.01% 83.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 43 0.11% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34496-34527 1 0.00% 83.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 2 0.01% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35167 1 0.00% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 1 0.00% 83.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36127 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36288-36319 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36383 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37824-37855 1 0.00% 83.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38175 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39263 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39455 1 0.00% 84.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39519 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40287 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40832-40863 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 1 0.00% 84.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41503 2 0.01% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41664-41695 1 0.00% 84.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42271 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43039 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44127 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45599 1 0.00% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 2 0.01% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46367 2 0.01% 84.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46879 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-47007 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48671 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48927 1 0.00% 84.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49183 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49472-49503 1 0.00% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 2 0.01% 84.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51776-51807 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 2 0.01% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 84.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54559 2 0.01% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54815 1 0.00% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56064-56095 1 0.00% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56351 1 0.00% 84.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57280-57311 1 0.00% 84.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57600-57631 2 0.01% 84.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57792-57823 1 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57856-57887 1 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 84.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59840-59871 1 0.00% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59968-59999 1 0.00% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60416-60447 1 0.00% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::61440-61471 4 0.01% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62208-62239 1 0.00% 84.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62400-62431 1 0.00% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62495 1 0.00% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63488-63519 2 0.01% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::63744-63775 1 0.00% 84.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64543 1 0.00% 84.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65152-65183 6 0.02% 84.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 6 0.02% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65439 1 0.00% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 5797 14.94% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129920-129951 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130880-130911 1 0.00% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 326 0.84% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131328-131359 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 2 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::132096-132127 2 0.01% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::133632-133663 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::140032-140063 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::162560-162591 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::165568-165599 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::182528-182559 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48021 # Bytes accessed per row activation -system.physmem.totQLat 359781455750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 452374882000 # Sum of mem lat for all requests -system.physmem.totBusLat 76509130000 # Total cycles spent in databus access -system.physmem.totBankLat 16084296250 # Total cycles spent in bank access -system.physmem.avgQLat 23512.32 # Average queueing delay per request -system.physmem.avgBankLat 1051.14 # Average bank access latency per request +system.physmem.bytesPerActivate::175552-175583 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::189440-189471 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 6 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38811 # Bytes accessed per row activation +system.physmem.totQLat 182252409750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 221627859750 # Sum of mem lat for all requests +system.physmem.totBusLat 31289130000 # Total cycles spent in databus access +system.physmem.totBankLat 8086320000 # Total cycles spent in bank access +system.physmem.avgQLat 29123.92 # Average queueing delay per request +system.physmem.avgBankLat 1292.19 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29563.46 # Average memory access latency -system.physmem.avgRdBW 374.68 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.18 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.33 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.79 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 35416.11 # Average memory access latency +system.physmem.avgRdBW 359.52 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.31 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.13 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.54 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.08 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 13.40 # Average write queue length over time -system.physmem.readRowHits 15272830 # Number of row buffer hits during reads -system.physmem.writeRowHits 805042 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.81 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.69 # Row buffer hit rate for writes -system.physmem.avgGap 162082.23 # Average gap between requests +system.physmem.busUtil 3.18 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.avgWrQLen 11.52 # Average write queue length over time +system.physmem.readRowHits 6237911 # Number of row buffer hits during reads +system.physmem.writeRowHits 804550 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes +system.physmem.avgGap 157316.33 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -509,307 +525,307 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54057191 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16352590 # Transaction distribution -system.membus.trans_dist::ReadResp 16352590 # Transaction distribution -system.membus.trans_dist::WriteReq 769166 # Transaction distribution -system.membus.trans_dist::WriteResp 769166 # Transaction distribution -system.membus.trans_dist::Writeback 66800 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35679 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 18283 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14097 # Transaction distribution -system.membus.trans_dist::ReadExReq 138270 # Transaction distribution -system.membus.trans_dist::ReadExResp 137887 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 57 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 345 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 402 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 57 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 345 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 402 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 57 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 345 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 402 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 61845817 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306747 # Transaction distribution +system.membus.trans_dist::ReadResp 7306747 # Transaction distribution +system.membus.trans_dist::WriteReq 767893 # Transaction distribution +system.membus.trans_dist::WriteResp 767893 # Transaction distribution +system.membus.trans_dist::Writeback 66623 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33809 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17757 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12548 # Transaction distribution +system.membus.trans_dist::ReadExReq 138043 # Transaction distribution +system.membus.trans_dist::ReadExResp 137663 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1976722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1970999 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4376896 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2384276 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32254354 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 13830 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 14160695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34654528 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 16555723 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17759220 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17723636 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20183988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2392552 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20138869 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 138869748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 27660 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 66482420 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141294516 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141294516 # Total data (bytes) +system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 68897653 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68897653 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1493240500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475761000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17657749750 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 11792000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 8620588249 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) +system.membus.reqLayer3.occupancy 9828000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 1805500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 756000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4833822840 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34180950731 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 73069 # number of replacements -system.l2c.tagsinuse 53059.477869 # Cycle average of tags in use -system.l2c.total_refs 1873536 # Total number of references to valid blocks. -system.l2c.sampled_refs 138222 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.554543 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37743.094868 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.500926 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000358 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4196.922721 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2968.415869 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.090066 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4030.052193 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4103.400867 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575914 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000069 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064040 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045294 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000200 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061494 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062613 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809623 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 23020 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4625 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 393598 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 165506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 32735 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5728 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 607995 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 201851 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1435058 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583280 # number of Writeback hits -system.l2c.Writeback_hits::total 583280 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1128 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 710 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 170 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 374 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48355 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58837 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107192 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 23020 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4625 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 393598 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 213861 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 32735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5728 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 607995 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 260688 # number of demand (read+write) hits -system.l2c.demand_hits::total 1542250 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 23020 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4625 # number of overall hits -system.l2c.overall_hits::cpu0.inst 393598 # number of overall hits -system.l2c.overall_hits::cpu0.data 213861 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 32735 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5728 # number of overall hits -system.l2c.overall_hits::cpu1.inst 607995 # number of overall hits -system.l2c.overall_hits::cpu1.data 260688 # number of overall hits -system.l2c.overall_hits::total 1542250 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses +system.membus.respLayer1.occupancy 4823074562 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.respLayer2.occupancy 13762899732 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.l2c.tags.replacements 72713 # number of replacements +system.l2c.tags.tagsinuse 53848.744123 # Cycle average of tags in use +system.l2c.tags.total_refs 1839089 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137893 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.337073 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39490.919089 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.921030 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000842 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4011.444595 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2831.104153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.348710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3706.565293 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3793.440412 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.602584 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000090 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061210 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043199 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056558 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821667 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22072 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4261 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386985 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31010 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5009 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589730 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198052 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403774 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581377 # number of Writeback hits +system.l2c.Writeback_hits::total 581377 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1341 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 735 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2076 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 150 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 360 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48293 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58659 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106952 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22072 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4261 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386985 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214948 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 31010 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5009 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256711 # number of demand (read+write) hits +system.l2c.demand_hits::total 1510726 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22072 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4261 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386985 # number of overall hits +system.l2c.overall_hits::cpu0.data 214948 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 31010 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5009 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589730 # number of overall hits +system.l2c.overall_hits::cpu1.data 256711 # number of overall hits +system.l2c.overall_hits::total 1510726 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6054 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6310 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6631 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6355 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25381 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5662 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4388 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10050 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 778 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 584 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1362 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63189 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77383 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140572 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6279 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6380 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25250 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5158 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3783 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 636 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 418 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76953 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140216 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 16 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69499 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6631 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83738 # number of demand (read+write) misses -system.l2c.demand_misses::total 165953 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6279 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69643 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83197 # number of demand (read+write) misses +system.l2c.demand_misses::total 165466 # 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mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.097105 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000478 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015141 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.245126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010776 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.243045 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.097105 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 380765750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3846158862 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1453000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 407670750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 4948402170 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 9585910782 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 7151250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12399747242 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2451249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154593597491 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167002947232 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1054895750 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25482276685 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 26537172435 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 7151250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13454642992 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2451249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180075874176 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 193540119667 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036657 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030436 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017618 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793661 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.837317 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811564 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.751773 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.735915 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.745403 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567096 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567450 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567290 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098671 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010581 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098671 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61102.112440 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66724.991783 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63327.411493 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10028.099965 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10029.024613 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.503682 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10047.908740 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10031.811644 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.006608 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54663.358211 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 58809.379683 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56945.687406 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61029.875296 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65172.040849 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62905.227161 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.604692 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10028.486386 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.093278 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.941824 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.858852 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10039.891841 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54677.242037 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59038.145621 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57070.582409 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60710.915551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55244.578629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 72805.555556 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64546.768836 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59407.747799 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57919.172045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1000,67 +1016,67 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58542991 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2739841 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2739840 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 769166 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 769166 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583280 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 34832 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18657 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 53489 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 259511 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 259511 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 800088 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073172 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13793 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 57051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1229933 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4820895 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 15468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 74350 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 8084750 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25585472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34695904 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 18508 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 92124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 39339008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 48266196 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 22912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 131012 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148151136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148151136 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4868352 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4921338984 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1802175919 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1506283904 # Layer occupancy (ticks) +system.toL2Bus.throughput 135543504 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2708876 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2708875 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767893 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767893 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581377 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33332 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18117 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51449 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258856 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258856 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 787342 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073883 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 55968 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1192763 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4801194 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 14594 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 72477 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 8011689 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25176640 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34854805 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 17052 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 88352 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 38149824 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 47763808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 20036 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 124096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 146194613 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146194613 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4803948 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4894718895 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1774755611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1516721983 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9191448 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9224710 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34164696 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 34035182 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2769642515 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3249270250 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9767440 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2687171756 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 3246383092 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 9605952 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41898883 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41732428 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47250451 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322888 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322888 # Transaction distribution -system.iobus.trans_dist::WriteReq 8066 # Transaction distribution -system.iobus.trans_dist::WriteResp 8066 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.throughput 45913386 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution +system.iobus.trans_dist::WriteReq 7946 # Transaction distribution +system.iobus.trans_dist::WriteResp 7946 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1077,16 +1093,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30842 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1103,15 +1119,15 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661908 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 14572206 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1128,16 +1144,16 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392552 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 17696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1154,25 +1170,25 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503080 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503080 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21645000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 51148561 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148561 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4430000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4018000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 369000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 297000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -1203,44 +1219,44 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376210000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu0.branchPred.lookups 6073314 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4627623 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295826 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3795187 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2949225 # Number of BTB hits +system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374564000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 16693526268 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 6007013 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4581243 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296095 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3784394 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2916091 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.709610 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 683153 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28183 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.055692 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673819 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28621 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8970256 # DTB read hits -system.cpu0.dtb.read_misses 29375 # DTB read misses -system.cpu0.dtb.write_hits 5214738 # DTB write hits -system.cpu0.dtb.write_misses 5731 # DTB write misses +system.cpu0.dtb.read_hits 8911671 # DTB read hits +system.cpu0.dtb.read_misses 28579 # DTB read misses +system.cpu0.dtb.write_hits 5140325 # DTB write hits +system.cpu0.dtb.write_misses 5457 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 935 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 591 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8999631 # DTB read accesses -system.cpu0.dtb.write_accesses 5220469 # DTB write accesses +system.cpu0.dtb.perms_faults 555 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8940250 # DTB read accesses +system.cpu0.dtb.write_accesses 5145782 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14184994 # DTB hits -system.cpu0.dtb.misses 35106 # DTB misses -system.cpu0.dtb.accesses 14220100 # DTB accesses -system.cpu0.itb.inst_hits 4276462 # ITB inst hits -system.cpu0.itb.inst_misses 5070 # ITB inst misses +system.cpu0.dtb.hits 14051996 # DTB hits +system.cpu0.dtb.misses 34036 # DTB misses +system.cpu0.dtb.accesses 14086032 # DTB accesses +system.cpu0.itb.inst_hits 4224524 # ITB inst hits +system.cpu0.itb.inst_misses 5106 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1249,530 +1265,534 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1351 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1346 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1356 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1478 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4281532 # ITB inst accesses -system.cpu0.itb.hits 4276462 # DTB hits -system.cpu0.itb.misses 5070 # DTB misses -system.cpu0.itb.accesses 4281532 # DTB accesses -system.cpu0.numCycles 69613456 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4229630 # ITB inst accesses +system.cpu0.itb.hits 4224524 # DTB hits +system.cpu0.itb.misses 5106 # DTB misses +system.cpu0.itb.accesses 4229630 # DTB accesses +system.cpu0.numCycles 69191123 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11926468 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32461716 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6073314 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3632378 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7613392 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1460130 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 63151 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20074417 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5834 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46093 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1371911 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 309 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4274981 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157877 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2111 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42149460 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.995068 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.376418 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11726999 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32040106 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6007013 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3589910 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7522223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1454890 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60839 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19594371 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47034 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1322790 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4222942 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157135 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2060 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41323427 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001891 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.382270 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34543319 81.95% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 572779 1.36% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 825233 1.96% 85.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 684006 1.62% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 778589 1.85% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 565339 1.34% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 679715 1.61% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 356870 0.85% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3143610 7.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33808589 81.81% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565594 1.37% 83.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817189 1.98% 85.16% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676917 1.64% 86.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774557 1.87% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 561158 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 668023 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352527 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098873 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42149460 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.087243 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.466314 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12452855 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21284567 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6905227 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 522550 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 984261 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 948796 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64785 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40574738 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212216 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 984261 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13028707 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5941224 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13201317 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6800913 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2193038 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39456506 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 442978 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1248488 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 66 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39834265 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 178291734 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 178257443 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34291 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31450110 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8384154 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 420012 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 376763 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5452877 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7762434 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5776236 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132872 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1233884 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37360552 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 904892 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37716432 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82271 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6323448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13282471 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257104 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42149460 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.894826 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.507768 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41323427 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086818 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.463067 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12228313 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20776644 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6830919 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 507068 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 980483 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935966 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64632 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40044073 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213118 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 980483 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12794933 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5974902 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12785484 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6719608 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2068017 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38935181 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1840 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 426390 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1152446 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 100 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39283995 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175854037 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175819876 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34161 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30939461 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8344533 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411347 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370357 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5351975 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7655764 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5689444 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124222 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1281984 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36848399 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895286 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37254672 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81509 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6299557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13203578 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256355 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41323427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901539 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514633 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26809075 63.60% 63.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5821539 13.81% 77.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3209963 7.62% 85.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2497911 5.93% 90.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2123670 5.04% 96.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 939017 2.23% 98.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502938 1.19% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188935 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56412 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26248165 63.52% 63.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5684023 13.75% 77.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3115322 7.54% 84.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2467752 5.97% 90.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2139591 5.18% 95.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 926164 2.24% 98.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 502996 1.22% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185723 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53691 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42149460 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41323427 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27471 2.55% 2.55% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 463 0.04% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 839894 78.10% 80.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207538 19.30% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27493 2.57% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842638 78.71% 81.32% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200034 18.68% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22648900 60.05% 60.19% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47937 0.13% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9431477 25.01% 85.32% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5535066 14.68% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22336809 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46914 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9369783 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5448235 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37716432 # Type of FU issued -system.cpu0.iq.rate 0.541798 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1075366 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028512 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 118766388 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44596758 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34851054 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8389 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 37254672 # Type of FU issued +system.cpu0.iq.rate 0.538431 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070617 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028738 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117010237 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44051144 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34347967 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8478 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38735073 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4381 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 316422 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 38268613 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4462 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307627 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1379018 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2578 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13049 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 541624 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1377452 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2519 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13094 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537577 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149592 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 6129 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192819 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5737 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 984261 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4297602 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 105996 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38383622 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 87186 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7762434 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5776236 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 577553 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40750 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2975 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13049 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150118 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117853 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267971 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37335026 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9287293 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 381406 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 980483 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4321779 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103852 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37861161 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83824 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7655764 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5689444 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571291 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39684 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13815 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13094 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150380 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118124 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268504 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36875907 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9227090 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378765 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118178 # number of nop insts executed -system.cpu0.iew.exec_refs 14774953 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4916788 # Number of branches executed -system.cpu0.iew.exec_stores 5487660 # Number of stores executed -system.cpu0.iew.exec_rate 0.536319 # Inst execution rate -system.cpu0.iew.wb_sent 37140556 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34854926 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18563816 # num instructions producing a value -system.cpu0.iew.wb_consumers 35689656 # num instructions consuming a value +system.cpu0.iew.exec_nop 117476 # number of nop insts executed +system.cpu0.iew.exec_refs 14627584 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4856181 # Number of branches executed +system.cpu0.iew.exec_stores 5400494 # Number of stores executed +system.cpu0.iew.exec_rate 0.532957 # Inst execution rate +system.cpu0.iew.wb_sent 36680744 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34351839 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18317228 # num instructions producing a value +system.cpu0.iew.wb_consumers 35218038 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.500692 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520146 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496478 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520109 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6130188 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 647788 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232202 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41165199 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.772263 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.733134 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6105741 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638931 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232529 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40342944 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775737 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.743782 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29286812 71.14% 71.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5810011 14.11% 85.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1968218 4.78% 90.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 996844 2.42% 92.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 804428 1.95% 94.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515457 1.25% 95.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 392582 0.95% 96.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 223885 0.54% 97.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1166962 2.83% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28719843 71.19% 71.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5706970 14.15% 85.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1863125 4.62% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 981446 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 776304 1.92% 94.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 515472 1.28% 95.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 394004 0.98% 96.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 214891 0.53% 97.10% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1170889 2.90% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41165199 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24069809 # Number of instructions committed -system.cpu0.commit.committedOps 31790359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40342944 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23687602 # Number of instructions committed +system.cpu0.commit.committedOps 31295507 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11618028 # Number of memory references committed -system.cpu0.commit.loads 6383416 # Number of loads committed -system.cpu0.commit.membars 231880 # Number of memory barriers committed -system.cpu0.commit.branches 4307208 # Number of branches committed +system.cpu0.commit.refs 11430179 # Number of memory references committed +system.cpu0.commit.loads 6278312 # Number of loads committed +system.cpu0.commit.membars 229695 # Number of memory barriers committed +system.cpu0.commit.branches 4246577 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28099612 # Number of committed integer instructions. -system.cpu0.commit.function_calls 498731 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1166962 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27650890 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489495 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1170889 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77052413 # The number of ROB reads -system.cpu0.rob.rob_writes 76827079 # The number of ROB writes -system.cpu0.timesIdled 370271 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27463996 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5157937915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23989067 # Number of Instructions Simulated -system.cpu0.committedOps 31709617 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23989067 # Number of Instructions Simulated -system.cpu0.cpi 2.901883 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.901883 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.344604 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.344604 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174143996 # number of integer regfile reads -system.cpu0.int_regfile_writes 34604534 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3264 # number of floating regfile reads -system.cpu0.fp_regfile_writes 896 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13203658 # number of misc regfile reads -system.cpu0.misc_regfile_writes 457594 # number of misc regfile writes -system.cpu0.icache.replacements 399659 # number of replacements -system.cpu0.icache.tagsinuse 511.575445 # Cycle average of tags in use -system.cpu0.icache.total_refs 3842942 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 400171 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.603250 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6980726000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.575445 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999171 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999171 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3842942 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3842942 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3842942 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3842942 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3842942 # number of overall hits -system.cpu0.icache.overall_hits::total 3842942 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 431911 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 431911 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 431911 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 431911 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 431911 # number of overall misses -system.cpu0.icache.overall_misses::total 431911 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5969636493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5969636493 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5969636493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5969636493 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5969636493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5969636493 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4274853 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4274853 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4274853 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4274853 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4274853 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4274853 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.101035 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.101035 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.101035 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.101035 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.101035 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.101035 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13821.450468 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13821.450468 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13821.450468 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13821.450468 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13821.450468 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3644 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75722045 # The number of ROB reads +system.cpu0.rob.rob_writes 75784919 # The number of ROB writes +system.cpu0.timesIdled 368023 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27867696 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2158812857 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23606860 # Number of Instructions Simulated +system.cpu0.committedOps 31214765 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23606860 # Number of Instructions Simulated +system.cpu0.cpi 2.930975 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.930975 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341183 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341183 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171887932 # number of integer regfile reads +system.cpu0.int_regfile_writes 34101589 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads +system.cpu0.fp_regfile_writes 874 # number of floating regfile writes +system.cpu0.misc_regfile_reads 12983242 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451267 # number of misc regfile writes +system.cpu0.icache.tags.replacements 393301 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.011114 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3798020 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393813 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.644222 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6979217250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.011114 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998069 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3798020 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3798020 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3798020 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3798020 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3798020 # number of overall hits +system.cpu0.icache.overall_hits::total 3798020 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424793 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424793 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424793 # 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average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.919608 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13909.919608 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.919608 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13909.919608 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3571 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.942529 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.620879 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9682500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9682500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 9682500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093616 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093616 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093616 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093616 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12156.026155 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12156.026155 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12156.026155 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30958 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30958 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30958 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30958 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30958 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30958 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393835 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393835 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393835 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393835 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393835 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393835 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4811729884 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4811729884 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4811729884 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4811729884 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4811729884 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4811729884 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 9686500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 9686500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 9686500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 9686500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093264 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093264 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093264 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093264 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.628916 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.628916 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.628916 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275313 # number of replacements -system.cpu0.dcache.tagsinuse 479.702966 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9426114 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275825 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.174255 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49336000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.702966 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.936920 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.936920 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5876643 # 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number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76877974883 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 76877974883 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 89351500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 89351500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 49685500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 49685500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 82392704883 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 82392704883 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 82392704883 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 82392704883 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6269229 # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178461 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178461 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14047.189660 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14047.189660 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48497.120492 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48497.120492 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10116.791214 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10116.791214 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6407.725045 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6407.725045 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41658.912173 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41658.912173 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41658.912173 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 10507 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 10018 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 605 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 134 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.366942 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 74.761194 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 276277 # number of replacements +system.cpu0.dcache.tags.tagsinuse 458.508643 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9265297 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276789 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.474224 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 49564250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 458.508643 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.895525 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.895525 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5784459 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5784459 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159328 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159328 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139329 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139329 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137110 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137110 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8943787 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8943787 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8943787 # number of overall hits +system.cpu0.dcache.overall_hits::total 8943787 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392022 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392022 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1584787 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1584787 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8757 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8757 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7526 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7526 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976809 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976809 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976809 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976809 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5532398989 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5532398989 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77338129003 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77338129003 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88246985 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88246985 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46297127 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46297127 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82870527992 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82870527992 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82870527992 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82870527992 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744115 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744115 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148086 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148086 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144636 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920596 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920596 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920596 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920596 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063470 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063470 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334053 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334053 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059135 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059135 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052034 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052034 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181017 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181017 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181017 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181017 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14112.470701 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14112.470701 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48800.330267 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48800.330267 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10077.307868 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10077.307868 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6151.624635 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6151.624635 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41921.363163 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41921.363163 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9474 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7234 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 614 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 133 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.429967 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 54.390977 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255296 # number of writebacks -system.cpu0.dcache.writebacks::total 255296 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203565 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203565 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454109 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454109 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 475 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 475 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657674 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657674 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657674 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657674 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189021 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189021 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131098 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131098 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8357 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8357 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7751 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7751 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320119 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320119 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2392342380 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2392342380 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5118910660 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5118910660 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67659513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67659513 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34183001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34183001 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7511253040 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7511253040 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7511253040 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7511253040 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13429863028 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13429863028 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1251424879 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1251424879 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14681287907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14681287907 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030151 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030151 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027237 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027237 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056286 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056286 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053472 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053472 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028885 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028885 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028885 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12656.489914 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12656.489914 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39046.443577 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39046.443577 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8096.148498 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8096.148498 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4410.140756 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4410.140756 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23463.940097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23463.940097 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256588 # number of writebacks +system.cpu0.dcache.writebacks::total 256588 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203202 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203202 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454368 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454368 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 460 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657570 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657570 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657570 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657570 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188820 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188820 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130419 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130419 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8297 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7522 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7522 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319239 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319239 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319239 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319239 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2408343372 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2408343372 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110867707 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110867707 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66642015 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66642015 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31254873 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31254873 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7519211079 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7519211079 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7519211079 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7519211079 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504631783 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504631783 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180253969 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180253969 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14684885752 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14684885752 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030571 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030571 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027491 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052006 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029233 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029233 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8032.061589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8032.061589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4155.128024 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4155.128024 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1780,38 +1800,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9253585 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7592303 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 416171 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6192388 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5325484 # Number of BTB hits +system.cpu1.branchPred.lookups 9066954 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7451944 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 406719 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6049384 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5236824 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.000490 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 798470 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43798 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.567889 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772531 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42321 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43179554 # DTB read hits -system.cpu1.dtb.read_misses 37431 # DTB read misses -system.cpu1.dtb.write_hits 6972554 # DTB write hits -system.cpu1.dtb.write_misses 10848 # DTB write misses +system.cpu1.dtb.read_hits 42909677 # DTB read hits +system.cpu1.dtb.read_misses 36560 # DTB read misses +system.cpu1.dtb.write_hits 6823585 # DTB write hits +system.cpu1.dtb.write_misses 10691 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2005 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2926 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 258 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2608 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 669 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43216985 # DTB read accesses -system.cpu1.dtb.write_accesses 6983402 # DTB write accesses +system.cpu1.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42946237 # DTB read accesses +system.cpu1.dtb.write_accesses 6834276 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50152108 # DTB hits -system.cpu1.dtb.misses 48279 # DTB misses -system.cpu1.dtb.accesses 50200387 # DTB accesses -system.cpu1.itb.inst_hits 8467709 # ITB inst hits -system.cpu1.itb.inst_misses 5542 # ITB inst misses +system.cpu1.dtb.hits 49733262 # DTB hits +system.cpu1.dtb.misses 47251 # DTB misses +system.cpu1.dtb.accesses 49780513 # DTB accesses +system.cpu1.itb.inst_hits 8323198 # ITB inst hits +system.cpu1.itb.inst_misses 5400 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1820,113 +1840,113 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1529 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1492 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8473251 # ITB inst accesses -system.cpu1.itb.hits 8467709 # DTB hits -system.cpu1.itb.misses 5542 # DTB misses -system.cpu1.itb.accesses 8473251 # DTB accesses -system.cpu1.numCycles 412553366 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8328598 # ITB inst accesses +system.cpu1.itb.hits 8323198 # DTB hits +system.cpu1.itb.misses 5400 # DTB misses +system.cpu1.itb.accesses 8328598 # DTB accesses +system.cpu1.numCycles 410695591 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 20142179 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 67124404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9253585 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6123954 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14367636 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3996679 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 69030 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77666254 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41513 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1490350 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8465907 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 710561 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2899 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 116503477 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.698188 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.043258 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19628666 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66104666 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9066954 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6009355 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14131573 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3952223 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 62853 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77248707 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42228 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1436171 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 176 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8321388 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 704092 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2736 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115246116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.694374 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.038205 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 102143196 87.67% 87.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 814134 0.70% 88.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 962782 0.83% 89.20% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1912655 1.64% 90.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1508621 1.29% 92.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 586161 0.50% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2143967 1.84% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 421141 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6010820 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101121884 87.74% 87.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796637 0.69% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937162 0.81% 89.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1885853 1.64% 90.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1499695 1.30% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570142 0.49% 92.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2110638 1.83% 94.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410756 0.36% 94.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5913349 5.13% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 116503477 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022430 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.162705 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21695015 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78657608 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12988209 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 540911 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2621734 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1137928 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100371 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 76331637 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 334218 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2621734 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 23056356 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33279261 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41089956 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12073504 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4382666 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 71129037 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18835 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 684998 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3107715 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 374 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 75211284 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 327489941 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 327430919 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50108296 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 25102988 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 461152 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 401338 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8025308 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13414582 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8304810 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1056481 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1432553 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 64611179 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1174620 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90302569 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94169 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16313013 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45540722 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 275640 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 116503477 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.775106 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513735 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115246116 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022077 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.160958 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21155925 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78195753 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12775663 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524358 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2594417 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105836 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98153 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75067660 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 326745 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2594417 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22501379 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33242741 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40762154 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11860446 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4284979 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69913296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18816 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 670004 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3042907 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 379 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73978163 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321899381 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321840484 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58897 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49060581 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24917582 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444517 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387690 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7870912 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13163327 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8127092 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1028302 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1543452 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63442447 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157372 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89134089 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93553 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16181139 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45168283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 276533 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115246116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.773424 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513958 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 85607171 73.48% 73.48% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8609069 7.39% 80.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4398916 3.78% 84.65% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3887525 3.34% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10612061 9.11% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1964931 1.69% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1085414 0.93% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 259410 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 78980 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84850695 73.63% 73.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8420843 7.31% 80.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4255514 3.69% 84.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3817238 3.31% 87.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10566074 9.17% 97.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1932638 1.68% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1074262 0.93% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 253370 0.22% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75482 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 116503477 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115246116 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32357 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32069 0.41% 0.41% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available @@ -1955,395 +1975,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572484 95.70% 96.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 307046 3.88% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550960 95.79% 96.21% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298953 3.79% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38359652 42.48% 42.83% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61197 0.07% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 14 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 10 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1701 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44223929 48.97% 91.87% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7342124 8.13% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37650996 42.24% 42.59% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59191 0.07% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.66% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43937068 49.29% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171235 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90302569 # Type of FU issued -system.cpu1.iq.rate 0.218887 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7912883 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087626 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 305148356 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 82107584 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54845197 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15407 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8039 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6808 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 97893314 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8206 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 355446 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89134089 # Type of FU issued +system.cpu1.iq.rate 0.217032 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7882978 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088440 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 301522554 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80789150 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53744584 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15343 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8026 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96694852 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8153 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 340284 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3436601 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3841 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17378 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1303587 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3407112 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 16742 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1286559 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31958921 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 917809 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31912923 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 915604 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2621734 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25482277 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363023 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 65889169 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 115264 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13414582 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8304810 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 878172 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 66494 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3874 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17378 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 205598 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 157346 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 362944 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87965313 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43561744 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2337256 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2594417 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25467221 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 361914 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64703269 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112618 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13163327 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8127092 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869000 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64609 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6290 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 16742 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 200151 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154994 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355145 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86813167 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43279828 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2320922 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103370 # number of nop insts executed -system.cpu1.iew.exec_refs 50840273 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7156944 # Number of branches executed -system.cpu1.iew.exec_stores 7278529 # Number of stores executed -system.cpu1.iew.exec_rate 0.213222 # Inst execution rate -system.cpu1.iew.wb_sent 86983330 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54852005 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30529736 # num instructions producing a value -system.cpu1.iew.wb_consumers 54511543 # num instructions consuming a value +system.cpu1.iew.exec_nop 103450 # number of nop insts executed +system.cpu1.iew.exec_refs 50389574 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6997831 # Number of branches executed +system.cpu1.iew.exec_stores 7109746 # Number of stores executed +system.cpu1.iew.exec_rate 0.211381 # Inst execution rate +system.cpu1.iew.wb_sent 85834090 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53751385 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29958578 # num instructions producing a value +system.cpu1.iew.wb_consumers 53322000 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132957 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560060 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.130879 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.561843 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16208484 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 898980 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 317402 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 113881743 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.432055 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.398122 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16054832 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880839 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310229 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112651699 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.427506 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.393608 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 96739305 84.95% 84.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8399776 7.38% 92.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2206670 1.94% 94.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1295256 1.14% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1289720 1.13% 96.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 586162 0.51% 97.05% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 954092 0.84% 97.88% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 596070 0.52% 98.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1814692 1.59% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95929787 85.16% 85.16% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8195439 7.28% 92.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2121242 1.88% 94.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1255081 1.11% 95.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1260461 1.12% 96.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 575308 0.51% 97.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 943355 0.84% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 590559 0.52% 98.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1780467 1.58% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 113881743 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38868743 # Number of instructions committed -system.cpu1.commit.committedOps 49203152 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112651699 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38067147 # Number of instructions committed +system.cpu1.commit.committedOps 48159329 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16979204 # Number of memory references committed -system.cpu1.commit.loads 9977981 # Number of loads committed -system.cpu1.commit.membars 195491 # Number of memory barriers committed -system.cpu1.commit.branches 6119212 # Number of branches committed +system.cpu1.commit.refs 16596748 # Number of memory references committed +system.cpu1.commit.loads 9756215 # Number of loads committed +system.cpu1.commit.membars 190139 # Number of memory barriers committed +system.cpu1.commit.branches 5967970 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43616743 # Number of committed integer instructions. -system.cpu1.commit.function_calls 553203 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1814692 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42694003 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534679 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1780467 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 176412864 # The number of ROB reads -system.cpu1.rob.rob_writes 133542996 # The number of ROB writes -system.cpu1.timesIdled 1428534 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 296049889 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4814402067 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38799104 # Number of Instructions Simulated -system.cpu1.committedOps 49133513 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38799104 # Number of Instructions Simulated -system.cpu1.cpi 10.633064 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.633064 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.094046 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.094046 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393827212 # number of integer regfile reads -system.cpu1.int_regfile_writes 57409312 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5077 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2342 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18946986 # number of misc regfile reads -system.cpu1.misc_regfile_writes 419134 # number of misc regfile writes -system.cpu1.icache.replacements 614670 # number of replacements -system.cpu1.icache.tagsinuse 498.803951 # Cycle average of tags in use -system.cpu1.icache.total_refs 7804426 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 615182 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.686369 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74831061000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.803951 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974226 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974226 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7804426 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7804426 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7804426 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7804426 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7804426 # number of overall hits -system.cpu1.icache.overall_hits::total 7804426 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661434 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661434 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661434 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661434 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661434 # number of overall misses -system.cpu1.icache.overall_misses::total 661434 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8993382992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8993382992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8993382992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8993382992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8993382992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8993382992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8465860 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8465860 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8465860 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8465860 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8465860 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8465860 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078130 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.078130 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.078130 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.078130 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.078130 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.078130 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.795738 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13596.795738 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13596.795738 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13596.795738 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13596.795738 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3054 # number of cycles access was blocked +system.cpu1.rob.rob_reads 174041277 # The number of ROB reads +system.cpu1.rob.rob_writes 131120872 # The number of ROB writes +system.cpu1.timesIdled 1414866 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295449475 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1816711228 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37997508 # Number of Instructions Simulated +system.cpu1.committedOps 48089690 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37997508 # Number of Instructions Simulated +system.cpu1.cpi 10.808488 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.808488 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092520 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092520 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 388394171 # number of integer regfile reads +system.cpu1.int_regfile_writes 56329363 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2330 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18495746 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405487 # number of misc regfile writes +system.cpu1.icache.tags.replacements 596092 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.837460 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7679654 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 596604 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 12.872280 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74828235500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.837460 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.939136 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.939136 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7679654 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7679654 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7679654 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7679654 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7679654 # number of overall hits +system.cpu1.icache.overall_hits::total 7679654 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641686 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641686 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641686 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641686 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641686 # number of overall misses +system.cpu1.icache.overall_misses::total 641686 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8725652874 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8725652874 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8725652874 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8725652874 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8725652874 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8725652874 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8321340 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8321340 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8321340 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8321340 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8321340 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8321340 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077113 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.077113 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077113 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.077113 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077113 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.077113 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.010357 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13598.010357 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13598.010357 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13598.010357 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 3474 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 210 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.897561 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.542857 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46219 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46219 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46219 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 46219 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 46219 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 46219 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615215 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 615215 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 615215 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 615215 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 615215 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 615215 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7348125977 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7348125977 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7348125977 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7348125977 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7348125977 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7348125977 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3395500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3395500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3395500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3395500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.072670 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.072670 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.072670 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.072670 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11943.996777 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11943.996777 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11943.996777 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11943.996777 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 45060 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 45060 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 45060 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 45060 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 45060 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 45060 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596626 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596626 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596626 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596626 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596626 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596626 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7121155232 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7121155232 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7121155232 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7121155232 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7121155232 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7121155232 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3411250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3411250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3411250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071698 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071698 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071698 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11935.710532 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363541 # number of replacements -system.cpu1.dcache.tagsinuse 487.194544 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13012998 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363907 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.759131 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70879256000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.194544 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951552 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951552 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8508304 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8508304 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4270423 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4270423 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 99789 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 99789 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 97069 # 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number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1967323 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1967323 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1967323 # number of overall misses -system.cpu1.dcache.overall_misses::total 1967323 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6229483500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6229483500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 75673370015 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 75673370015 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131282500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 57807000 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 107977 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 107977 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14746050 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14746050 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14746050 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14746050 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045224 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045224 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.268104 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.268104 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124535 # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.924941 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8311494 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8311494 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138859 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138859 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97571 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97571 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94878 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94878 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12450353 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12450353 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12450353 # 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miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135793 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135793 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135793 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135793 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15400.682271 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15400.682271 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48568.361549 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48568.361549 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9259.612339 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9259.612339 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5024.428248 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5024.428248 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 41817.666438 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 41817.666438 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 41817.666438 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 41817.666438 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29976 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 17316 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3303 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 173 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.075386 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 100.092486 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327984 # number of writebacks -system.cpu1.dcache.writebacks::total 327984 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171525 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171525 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1401265 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1401265 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1449 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1449 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572790 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1572790 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572790 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1572790 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231477 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231477 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163056 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163056 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10906 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10906 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394533 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394533 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 394533 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 394533 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2900781135 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2900781135 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6520340298 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6520340298 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90030007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90030007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 35995000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 35995000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9421121433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9421121433 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9421121433 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9421121433 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169236235005 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169236235005 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34877229187 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34877229187 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204113464192 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204113464192 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025976 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025976 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027946 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027946 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111823 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101003 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101003 # 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average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3300.476802 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3300.476802 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23879.172168 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23879.172168 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324789 # number of writebacks +system.cpu1.dcache.writebacks::total 324789 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170095 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170095 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396532 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396532 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1437 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1437 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566627 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566627 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566627 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566627 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228081 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228081 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161620 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161620 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12503 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12503 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10598 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10598 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389701 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389701 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389701 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389701 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2839406051 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2839406051 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6490016907 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6490016907 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88435503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88435503 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32057085 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32057085 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9329422958 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9329422958 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9329422958 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9329422958 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34787133815 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34787133815 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026187 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112123 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112123 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40156.025906 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40156.025906 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7073.142686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7073.142686 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.824023 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.824023 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2351,12 +2371,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2365,18 +2385,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1508067529269 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1508067529269 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1508067529269 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 644226028268 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42383 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 50336 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b3687441c..49ef0687e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.534279 # Number of seconds simulated -sim_ticks 2534279149500 # Number of ticks simulated -final_tick 2534279149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.534332 # Number of seconds simulated +sim_ticks 2534332336000 # Number of ticks simulated +final_tick 2534332336000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51469 # Simulator instruction rate (inst/s) -host_op_rate 66227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2162854547 # Simulator tick rate (ticks/s) -host_mem_usage 400508 # Number of bytes of host memory used -host_seconds 1171.73 # Real time elapsed on the host -sim_insts 60307893 # Number of instructions simulated -sim_ops 77599512 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119547392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory +host_inst_rate 60160 # Simulator instruction rate (inst/s) +host_op_rate 77409 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2528112838 # Simulator tick rate (ticks/s) +host_mem_usage 401532 # Number of bytes of host memory used +host_seconds 1002.46 # Real time elapsed on the host +sim_insts 60307773 # Number of instructions simulated +sim_ops 77599321 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119572608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094160 # Number of bytes read from this memory -system.physmem.bytes_read::total 129441552 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783360 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 798144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9095056 # Number of bytes read from this memory +system.physmem.bytes_read::total 129468752 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799432 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14943424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14946576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 44 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12453 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142130 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15098054 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59115 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12471 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142144 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15101237 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813133 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47172148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1136 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47181108 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1111 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3588460 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51076280 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314485 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1492874 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1190110 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2682985 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1492874 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47172148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3588738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51085941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314933 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493575 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1190085 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2683661 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47181108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1111 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4778571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53759265 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15098054 # Total number of read requests seen -system.physmem.writeReqs 813133 # Total number of write requests seen -system.physmem.cpureqs 218381 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966275456 # Total number of bytes read from memory -system.physmem.bytesWritten 52040512 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129441552 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799432 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 339 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4672 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 944601 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943409 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943592 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943465 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943701 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943525 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 944001 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943648 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 942809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943923 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943684 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943779 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943691 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49135 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48909 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50973 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51086 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51003 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51258 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51261 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51198 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51347 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51095 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50750 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50404 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51353 # Track writes on a per bank basis +system.physmem.bw_total::cpu.inst 314933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4778824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53769602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15101237 # Total number of read requests seen +system.physmem.writeReqs 813162 # Total number of write requests seen +system.physmem.cpureqs 218445 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966479168 # Total number of bytes read from memory +system.physmem.bytesWritten 52042368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129468752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 279 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4676 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 944611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 944270 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 944423 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944612 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943754 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943694 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943515 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 944002 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943653 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 942812 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943784 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943693 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48913 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50969 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51083 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51011 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51258 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51200 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51098 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50757 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50407 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50977 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51264 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51120 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51124 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32444 # Number of times wr buffer was full causing retry -system.physmem.totGap 2534279100000 # Total gap between requests +system.physmem.numWrRetry 32457 # Number of times wr buffer was full causing retry +system.physmem.totGap 2534332242000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes -system.physmem.readPktSize::3 14943424 # Categorize read packet sizes +system.physmem.readPktSize::3 14946576 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154594 # Categorize read packet sizes +system.physmem.readPktSize::6 154625 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59115 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1052560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 988227 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3681755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2757300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2755283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2712082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 17052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 39830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27503 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10257 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 10197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 13755 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59144 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1052232 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 984006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 974713 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3682136 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2757823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2756219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2725955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 17025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28723 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28643 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9083 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 12526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5326 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -139,326 +139,316 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2647 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2818 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2892 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32507 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2885 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32578 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32505 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32462 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 42559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 23924.789210 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1816.195393 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32272.883514 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 8308 19.52% 19.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3417 8.03% 27.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2234 5.25% 32.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1796 4.22% 37.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1258 2.96% 39.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1103 2.59% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 837 1.97% 44.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 830 1.95% 46.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 538 1.26% 47.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 533 1.25% 49.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 414 0.97% 49.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 384 0.90% 50.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 258 0.61% 51.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 273 0.64% 52.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 193 0.45% 52.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 240 0.56% 53.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 148 0.35% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.34% 53.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 105 0.25% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 120 0.28% 54.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 89 0.21% 54.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 396 0.93% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1932 4.54% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 440 1.03% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 89 0.21% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 139 0.33% 61.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 56 0.13% 61.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 104 0.24% 61.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 40 0.09% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 62 0.15% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 22 0.05% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 58 0.14% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 29 0.07% 62.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.11% 62.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 13 0.03% 62.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 37 0.09% 62.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 11 0.03% 62.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 62.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 17 0.04% 62.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 62.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 62.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.04% 62.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 4 0.01% 62.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 18 0.04% 63.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 6 0.01% 63.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 14 0.03% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 63.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 12 0.03% 63.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 2 0.00% 63.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 7 0.02% 63.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 6 0.01% 63.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 17 0.04% 63.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 5 0.01% 63.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 8 0.02% 63.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 3 0.01% 63.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 5 0.01% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 63.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 1 0.00% 63.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 5 0.01% 63.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 9 0.02% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 39 0.09% 63.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 5 0.01% 63.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 63.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 6 0.01% 63.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 2 0.00% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 3 0.01% 63.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 4 0.01% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 6 0.01% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 63.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 8 0.02% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 63.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 1 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.00% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 3 0.01% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 1 0.00% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 2 0.00% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 3 0.01% 63.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 63.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 1 0.00% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 3 0.01% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 63.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 3 0.01% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 18 0.04% 63.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 5 0.01% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 8 0.02% 63.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 6 0.01% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 8 0.02% 63.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 9 0.02% 63.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7647 2 0.00% 63.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.01% 63.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 63.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 63.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 5 0.01% 63.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 63.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9152-9183 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 2 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9536-9567 1 0.00% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 19 0.04% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 64.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 1 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 2 0.00% 64.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11935 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 2 0.00% 64.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 4 0.01% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 64.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13855 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 2 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14879 2 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15040-15071 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 64.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15647 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16159 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 1 0.00% 64.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 3 0.01% 64.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 2 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 64.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17823 1 0.00% 64.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 2 0.00% 64.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 2 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19840-19871 1 0.00% 64.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 3 0.01% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20544-20575 1 0.00% 64.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22303 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22400-22431 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 1 0.00% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22592-22623 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23839 2 0.00% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25119 1 0.00% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 3 0.01% 64.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25664-25695 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25759 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 64.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 2 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27328-27359 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 2 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29376-29407 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29727 1 0.00% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30016-30047 1 0.00% 64.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 3 0.01% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31424-31455 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31519 1 0.00% 64.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 2 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 1 0.00% 64.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 44 0.10% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34176-34207 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34752-34783 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36639 1 0.00% 65.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36895 2 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37279 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39296-39327 1 0.00% 65.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39839 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40000-40031 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42015 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42048-42079 1 0.00% 65.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42527 2 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43295 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44703 1 0.00% 65.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44831 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45343 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47647 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47967 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48159 1 0.00% 65.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49920-49951 1 0.00% 65.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50176-50207 2 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50432-50463 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50719 1 0.00% 65.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54303 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56000-56031 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56832-56863 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57344-57375 1 0.00% 65.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58368-58399 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58944-58975 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62848-62879 1 0.00% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63232-63263 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64256-64287 1 0.00% 65.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64704-64735 1 0.00% 65.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65024-65055 13 0.03% 65.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 18 0.04% 65.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65344-65375 8 0.02% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65472-65503 18 0.04% 65.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14406 33.85% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::113216-113247 1 0.00% 99.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129664-129695 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129792-129823 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129984-130015 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130432-130463 1 0.00% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 325 0.76% 99.96% # Bytes accessed per row activation +system.physmem.wrQLenPdf::31 32470 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 42332 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 24053.235566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1833.734815 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32311.504914 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 8211 19.40% 19.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3440 8.13% 27.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2237 5.28% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1775 4.19% 37.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1231 2.91% 39.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1031 2.44% 42.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 888 2.10% 44.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 774 1.83% 46.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 547 1.29% 47.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 559 1.32% 48.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 426 1.01% 49.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 432 1.02% 50.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 287 0.68% 51.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 279 0.66% 52.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 159 0.38% 52.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 249 0.59% 53.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 131 0.31% 53.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 141 0.33% 53.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 101 0.24% 54.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 136 0.32% 54.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 82 0.19% 54.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 379 0.90% 55.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 1813 4.28% 59.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 447 1.06% 60.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.20% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 158 0.37% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 41 0.10% 61.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 104 0.25% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 37 0.09% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 64 0.15% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 25 0.06% 62.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 71 0.17% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 17 0.04% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 45 0.11% 62.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 11 0.03% 62.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 40 0.09% 62.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 10 0.02% 62.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 26 0.06% 62.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 12 0.03% 62.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 19 0.04% 62.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 3 0.01% 62.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 16 0.04% 62.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 8 0.02% 62.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 18 0.04% 62.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 12 0.03% 62.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 13 0.03% 62.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 25 0.06% 62.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 6 0.01% 62.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 62.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 9 0.02% 62.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 13 0.03% 62.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 6 0.01% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 6 0.01% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 2 0.00% 63.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 9 0.02% 63.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 6 0.01% 63.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 63.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 5 0.01% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 1 0.00% 63.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 4 0.01% 63.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 6 0.01% 63.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 4 0.01% 63.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 43 0.10% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 2 0.00% 63.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 3 0.01% 63.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 7 0.02% 63.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 8 0.02% 63.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 8 0.02% 63.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 6 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 4 0.01% 63.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 63.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 4 0.01% 63.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 2 0.00% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 63.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 2 0.00% 63.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 10 0.02% 63.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 3 0.01% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 63.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5663 1 0.00% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5727 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5791 1 0.00% 63.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5855 3 0.01% 63.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 5 0.01% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 63.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 1 0.00% 63.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 7 0.02% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6239 1 0.00% 63.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 2 0.00% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 4 0.01% 63.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 3 0.01% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6687 2 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 63.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 20 0.05% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 3 0.01% 63.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6943 3 0.01% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7007 1 0.00% 63.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 1 0.00% 63.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 4 0.01% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 1 0.00% 63.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 4 0.01% 63.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7519 1 0.00% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 63.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 63.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 7 0.02% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 63.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 3 0.01% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 2 0.00% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 3 0.01% 63.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 3 0.01% 63.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 11 0.03% 63.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 4 0.01% 63.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 322 0.76% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8991 1 0.00% 64.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9247 1 0.00% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 18 0.04% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10527 2 0.00% 64.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11039 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11295 2 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11551 1 0.00% 64.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11807 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 3 0.01% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12480-12511 1 0.00% 64.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12575 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12831 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13087 1 0.00% 64.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 2 0.00% 64.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14367 5 0.01% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14464-14495 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 64.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15391 3 0.01% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15808-15839 1 0.00% 64.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16415 2 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16960-16991 1 0.00% 64.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17216-17247 4 0.01% 64.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17439 5 0.01% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17951 2 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18368-18399 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18719 1 0.00% 64.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18816-18847 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-18975 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19167 1 0.00% 64.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 3 0.01% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19584-19615 1 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20511 2 0.00% 64.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21279 2 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21343 1 0.00% 64.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21535 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21919 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22336-22367 1 0.00% 64.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 2 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23071 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24000-24031 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24095 1 0.00% 64.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24351 2 0.00% 64.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24607 4 0.01% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24640-24671 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 64.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24863 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25280-25311 1 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25631 2 0.00% 64.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25887 2 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26240-26271 1 0.00% 64.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 3 0.01% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26911 1 0.00% 64.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27679 3 0.01% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27712-27743 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 64.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28447 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28608-28639 1 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28703 2 0.00% 64.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28736-28767 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28959 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29215 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 64.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29568-29599 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29727 3 0.01% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29983 1 0.00% 64.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30272-30303 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30495 1 0.00% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 3 0.01% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31007 2 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31104-31135 1 0.00% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31263 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31775 2 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31936-31967 1 0.00% 64.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32128-32159 1 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32543 2 0.00% 64.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 2 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 1 0.00% 64.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 6 0.01% 64.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33631 2 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33695 1 0.00% 64.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 44 0.10% 64.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34591 2 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35200-35231 1 0.00% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 2 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37504-37535 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37952-37983 1 0.00% 64.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38943 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40256-40287 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40735 1 0.00% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 3 0.01% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44575 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 1 0.00% 64.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47647 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50176-50207 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51200-51231 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52255 1 0.00% 64.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52992-53023 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53056-53087 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53760-53791 1 0.00% 64.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54528-54559 2 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57344-57375 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57856-57887 1 0.00% 64.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 2 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62464-62495 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::62528-62559 1 0.00% 64.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65088-65119 8 0.02% 64.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65216-65247 18 0.04% 65.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65280-65311 18 0.04% 65.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65344-65375 12 0.03% 65.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65472-65503 12 0.03% 65.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14415 34.05% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130816-130847 1 0.00% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 330 0.78% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 3 0.01% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168704-168735 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169664-169695 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::190464-190495 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 9 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 42559 # Bytes accessed per row activation -system.physmem.totQLat 355117101750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 446336213000 # Sum of mem lat for all requests -system.physmem.totBusLat 75488575000 # Total cycles spent in databus access -system.physmem.totBankLat 15730536250 # Total cycles spent in bank access -system.physmem.avgQLat 23521.25 # Average queueing delay per request -system.physmem.avgBankLat 1041.92 # Average bank access latency per request +system.physmem.bytesPerActivate::159168-159199 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160704-160735 1 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192512-192543 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196416-196447 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196608-196639 8 0.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 42332 # Bytes accessed per row activation +system.physmem.totQLat 352162436750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 443380465500 # Sum of mem lat for all requests +system.physmem.totBusLat 75504790000 # Total cycles spent in databus access +system.physmem.totBankLat 15713238750 # Total cycles spent in bank access +system.physmem.avgQLat 23320.54 # Average queueing delay per request +system.physmem.avgBankLat 1040.55 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29563.16 # Average memory access latency -system.physmem.avgRdBW 381.28 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 29361.08 # Average memory access latency +system.physmem.avgRdBW 381.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.53 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.08 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.18 # Average read queue length over time -system.physmem.avgWrQLen 11.71 # Average write queue length over time -system.physmem.readRowHits 15070837 # Number of row buffer hits during reads -system.physmem.writeRowHits 797438 # Number of row buffer hits during writes +system.physmem.avgRdQLen 0.17 # Average read queue length over time +system.physmem.avgWrQLen 10.77 # Average write queue length over time +system.physmem.readRowHits 15074158 # Number of row buffer hits during reads +system.physmem.writeRowHits 797610 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.07 # Row buffer hit rate for writes -system.physmem.avgGap 159276.56 # Average gap between requests +system.physmem.writeRowHitRate 98.09 # Row buffer hit rate for writes +system.physmem.avgGap 159247.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -471,60 +461,60 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54705448 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16150672 # Transaction distribution -system.membus.trans_dist::ReadResp 16150669 # Transaction distribution +system.membus.throughput 54715776 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16153842 # Transaction distribution +system.membus.trans_dist::ReadResp 16153842 # Transaction distribution system.membus.trans_dist::WriteReq 763336 # Transaction distribution system.membus.trans_dist::WriteResp 763336 # Transaction distribution -system.membus.trans_dist::Writeback 59115 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4669 # Transaction distribution +system.membus.trans_dist::Writeback 59144 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4673 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4672 # Transaction distribution -system.membus.trans_dist::ReadExReq 131424 # Transaction distribution -system.membus.trans_dist::ReadExResp 131424 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4676 # Transaction distribution +system.membus.trans_dist::ReadExReq 131438 # Transaction distribution +system.membus.trans_dist::ReadExResp 131438 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885755 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885854 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272475 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 29886845 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382946 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 29893152 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 31772600 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 31779006 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3770 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34159320 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34165728 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16693592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16697432 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19091509 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 119547368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19095353 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 119572608 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390313 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 136240960 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 136270040 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7540 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138638877 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138638877 # Total data (bytes) +system.membus.tot_pkt_size::total 138667961 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138667961 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1491846000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475262000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17371820500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17374745000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3645000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3634500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4719558707 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4718589198 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33739093743 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33742309741 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -532,13 +522,13 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48115298 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16126739 # Transaction distribution -system.iobus.trans_dist::ReadResp 16126726 # Transaction distribution +system.iobus.throughput 48124265 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16129900 # Transaction distribution +system.iobus.trans_dist::ReadResp 16129887 # Transaction distribution system.iobus.trans_dist::WriteReq 8158 # Transaction distribution system.iobus.trans_dist::WriteResp 8158 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -560,11 +550,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 29886835 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 29893155 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7938 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 518 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -586,10 +576,10 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 29886835 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32269781 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 29893155 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32276103 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -611,11 +601,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390309 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119547288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390313 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 119572568 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15876 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1036 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -637,12 +627,12 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 119547288 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 121937597 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 121937597 # Total data (bytes) +system.iobus.tot_pkt_size::system.iocache.cpu_side 119572568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 121962881 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 121962881 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3974000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 518000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -686,44 +676,44 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 14943424000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 14946584000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374788000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374790000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 29886822000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu.branchPred.lookups 14673159 # Number of BP lookups -system.cpu.branchPred.condPredicted 11756965 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9767663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7945266 # Number of BTB hits +system.iobus.respLayer1.occupancy 40962341509 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu.branchPred.lookups 14663186 # Number of BP lookups +system.cpu.branchPred.condPredicted 11751443 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 703165 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9748962 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7940354 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.342548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399657 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72413 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 81.448199 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1396465 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72132 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51397173 # DTB read hits -system.cpu.dtb.read_misses 63986 # DTB read misses -system.cpu.dtb.write_hits 11699533 # DTB write hits -system.cpu.dtb.write_misses 15890 # DTB write misses +system.cpu.dtb.read_hits 51389107 # DTB read hits +system.cpu.dtb.read_misses 64168 # DTB read misses +system.cpu.dtb.write_hits 11699261 # DTB write hits +system.cpu.dtb.write_misses 15977 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3562 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2402 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3558 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2439 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1410 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51461159 # DTB read accesses -system.cpu.dtb.write_accesses 11715423 # DTB write accesses +system.cpu.dtb.perms_faults 1367 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51453275 # DTB read accesses +system.cpu.dtb.write_accesses 11715238 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63096706 # DTB hits -system.cpu.dtb.misses 79876 # DTB misses -system.cpu.dtb.accesses 63176582 # DTB accesses -system.cpu.itb.inst_hits 12260245 # ITB inst hits -system.cpu.itb.inst_misses 11468 # ITB inst misses +system.cpu.dtb.hits 63088368 # DTB hits +system.cpu.dtb.misses 80145 # DTB misses +system.cpu.dtb.accesses 63168513 # DTB accesses +system.cpu.itb.inst_hits 12244686 # ITB inst hits +system.cpu.itb.inst_misses 11272 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -732,148 +722,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2492 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2481 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2998 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2937 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12271713 # ITB inst accesses -system.cpu.itb.hits 12260245 # DTB hits -system.cpu.itb.misses 11468 # DTB misses -system.cpu.itb.accesses 12271713 # DTB accesses -system.cpu.numCycles 475189978 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12255958 # ITB inst accesses +system.cpu.itb.hits 12244686 # DTB hits +system.cpu.itb.misses 11272 # DTB misses +system.cpu.itb.accesses 12255958 # DTB accesses +system.cpu.numCycles 475312551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30497823 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96057374 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14673159 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9344923 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21151922 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5296118 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123395 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 94706901 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2678 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 86562 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2683934 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12256747 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 864492 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5531 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.777320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.141699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30486466 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96013812 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14663186 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9336819 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21137847 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5287329 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 121734 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94652697 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 3821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 86418 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2672948 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 439 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12241258 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 862361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5349 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.777398 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.141854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131751310 86.18% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303513 0.85% 87.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1714679 1.12% 88.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2493622 1.63% 89.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2205066 1.44% 91.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1108856 0.73% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2738323 1.79% 93.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743817 0.49% 94.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8828458 5.77% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131667661 86.18% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1302340 0.85% 87.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1711403 1.12% 88.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2491779 1.63% 89.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2204039 1.44% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1109873 0.73% 91.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2734812 1.79% 93.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 742969 0.49% 94.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8825405 5.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 152887644 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030879 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.202145 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32458089 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96821111 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19172249 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 971461 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3464734 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1958214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171741 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112504503 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568893 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3464734 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34365136 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38157390 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52654113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18177530 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6068741 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106257538 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20628 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016430 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4078403 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 665 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110740396 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 486151881 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 486061534 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90347 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78390288 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32350107 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830682 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737164 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12219946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20282216 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13494315 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1963339 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2435947 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97859231 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1984036 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124319403 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 165680 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21668523 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 56420296 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 152887644 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813142 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528360 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 152790281 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030850 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.202001 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32434469 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96765795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19163623 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 968040 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3458354 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1955309 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172027 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112442167 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568180 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3458354 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34339332 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38106819 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52671042 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18167139 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6047595 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106212332 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004586 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4065982 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 631 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110697957 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485950395 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485859311 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91084 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78390094 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32307862 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830633 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736877 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12210661 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20268413 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13492534 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1964739 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2435625 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97824738 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983401 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124295624 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 165509 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21636439 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 56320984 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501000 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152790281 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528895 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108584137 71.02% 71.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13613798 8.90% 79.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7066944 4.62% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5988746 3.92% 88.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12566780 8.22% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2768589 1.81% 98.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1723460 1.13% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 446866 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 128324 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108515921 71.02% 71.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13589329 8.89% 79.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7066338 4.62% 84.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5978859 3.91% 88.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12565558 8.22% 96.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2772936 1.81% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1725765 1.13% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 449060 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 126515 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 152887644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152790281 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62053 0.70% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365072 94.62% 95.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413828 4.68% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 62738 0.71% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365929 94.58% 95.29% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 416628 4.71% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58665929 47.19% 47.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93120 0.07% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58652585 47.19% 47.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93247 0.08% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.56% # Type of FU issued @@ -886,397 +876,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.56% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 16 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 47.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.56% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52876194 42.53% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318342 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52864927 42.53% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319034 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124319403 # Type of FU issued -system.cpu.iq.rate 0.261620 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8840956 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 410589228 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121528348 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 86069861 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23359 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12446 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132784241 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12452 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624311 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124295624 # Type of FU issued +system.cpu.iq.rate 0.261503 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8845299 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071163 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 410448757 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121460975 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 86059539 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23386 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12542 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10302 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132764827 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12430 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 625909 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4627641 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6443 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30069 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1762200 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4613851 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6375 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30092 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1760453 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 918337 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107892 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 916935 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3464734 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29357042 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 436051 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100064926 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205472 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20282216 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13494315 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1410818 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 114442 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3537 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30069 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350642 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 268888 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121646726 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52084248 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2672677 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3458354 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29328857 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 436741 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100030676 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203650 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20268413 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13492534 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410837 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 115234 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3326 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30092 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 349264 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268145 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 617409 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121630045 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52076046 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2665579 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221659 # number of nop insts executed -system.cpu.iew.exec_refs 64295158 # number of memory reference insts executed -system.cpu.iew.exec_branches 11560329 # Number of branches executed -system.cpu.iew.exec_stores 12210910 # Number of stores executed -system.cpu.iew.exec_rate 0.255996 # Inst execution rate -system.cpu.iew.wb_sent 120490085 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 86080146 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47268053 # num instructions producing a value -system.cpu.iew.wb_consumers 88199499 # num instructions consuming a value +system.cpu.iew.exec_nop 222537 # number of nop insts executed +system.cpu.iew.exec_refs 64287237 # number of memory reference insts executed +system.cpu.iew.exec_branches 11556571 # Number of branches executed +system.cpu.iew.exec_stores 12211191 # Number of stores executed +system.cpu.iew.exec_rate 0.255895 # Inst execution rate +system.cpu.iew.wb_sent 120479293 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 86069841 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47268516 # num instructions producing a value +system.cpu.iew.wb_consumers 88195904 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.181149 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535922 # average fanout of values written-back +system.cpu.iew.wb_rate 0.181081 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535949 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21408137 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482395 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 535479 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149422910 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520334 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507055 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 21374007 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482401 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 533608 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149331927 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.520650 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.508241 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121949451 81.61% 81.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13299405 8.90% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3946740 2.64% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2141050 1.43% 94.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1955041 1.31% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 959721 0.64% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1537792 1.03% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 781343 0.52% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2852367 1.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121887208 81.62% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290460 8.90% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3923979 2.63% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2130804 1.43% 94.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1950357 1.31% 95.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 968781 0.65% 96.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1543061 1.03% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 783043 0.52% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2854234 1.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149422910 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60458274 # Number of instructions committed -system.cpu.commit.committedOps 77749893 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149331927 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60458154 # Number of instructions committed +system.cpu.commit.committedOps 77749702 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27386690 # Number of memory references committed -system.cpu.commit.loads 15654575 # Number of loads committed -system.cpu.commit.membars 403596 # Number of memory barriers committed -system.cpu.commit.branches 9961373 # Number of branches committed +system.cpu.commit.refs 27386643 # Number of memory references committed +system.cpu.commit.loads 15654562 # Number of loads committed +system.cpu.commit.membars 403601 # Number of memory barriers committed +system.cpu.commit.branches 9961356 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68855105 # Number of committed integer instructions. -system.cpu.commit.function_calls 991268 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2852367 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68854920 # Number of committed integer instructions. +system.cpu.commit.function_calls 991265 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2854234 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 243879966 # The number of ROB reads -system.cpu.rob.rob_writes 201882555 # The number of ROB writes -system.cpu.timesIdled 1780421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322302334 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593285278 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60307893 # Number of Instructions Simulated -system.cpu.committedOps 77599512 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60307893 # Number of Instructions Simulated -system.cpu.cpi 7.879399 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.879399 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126913 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126913 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550704700 # number of integer regfile reads -system.cpu.int_regfile_writes 88578312 # number of integer regfile writes -system.cpu.fp_regfile_reads 8302 # number of floating regfile reads -system.cpu.fp_regfile_writes 2882 # number of floating regfile writes -system.cpu.misc_regfile_reads 30116391 # number of misc regfile reads +system.cpu.rob.rob_reads 243752783 # The number of ROB reads +system.cpu.rob.rob_writes 201807644 # The number of ROB writes +system.cpu.timesIdled 1781061 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322522270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4593269077 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60307773 # Number of Instructions Simulated +system.cpu.committedOps 77599321 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60307773 # Number of Instructions Simulated +system.cpu.cpi 7.881448 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.881448 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126880 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126880 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 550637144 # number of integer regfile reads +system.cpu.int_regfile_writes 88566595 # number of integer regfile writes +system.cpu.fp_regfile_reads 8370 # number of floating regfile reads +system.cpu.fp_regfile_writes 2906 # number of floating regfile writes +system.cpu.misc_regfile_reads 30124157 # number of misc regfile reads system.cpu.misc_regfile_writes 831896 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58661050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2657246 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2657245 # Transaction distribution +system.cpu.toL2Bus.throughput 58663468 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2657447 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2657446 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763336 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763336 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607669 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2958 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2973 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246055 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1960500 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5796171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30982 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126318 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 7913971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62698816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85512245 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 42284 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 208804 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148462149 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148462149 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 201328 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128322117 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607541 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 17 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2983 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 245999 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 245999 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1961368 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5795761 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 30461 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 126683 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 7914273 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 62726656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 85494329 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 41328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 209684 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148471997 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148471997 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 200728 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 3128200875 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1471549889 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1474731013 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2533210636 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2562590429 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 20419483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 20135737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74237753 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74394752 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.replacements 980157 # number of replacements -system.cpu.icache.tagsinuse 511.579914 # Cycle average of tags in use -system.cpu.icache.total_refs 11196212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980669 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.416912 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6837358000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.579914 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11196212 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11196212 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11196212 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11196212 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11196212 # number of overall hits -system.cpu.icache.overall_hits::total 11196212 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1060409 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1060409 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1060409 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1060409 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060409 # number of overall misses -system.cpu.icache.overall_misses::total 1060409 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14257699991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14257699991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14257699991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14257699991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14257699991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12256621 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12256621 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12256621 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12256621 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12256621 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.086517 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.086517 # 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average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45454.842720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45454.842720 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13619.740921 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15206.058824 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39132.578126 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39132.578126 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4967192840 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10605079278 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 144959500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 224497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15572272118 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15572272118 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182317512000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 35728890492 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 218046402492 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024347 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047590 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000069 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12881.958023 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42610.872936 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11878.031793 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13205.705882 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24543.555094 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24543.555094 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1559,12 +1549,12 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1573,16 +1563,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1488848485257 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1488848485257 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1488848485257 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1486035968259 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1486035968259 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1486035968259 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83044 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83045 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index edfc62ccf..2906c8c25 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,165 +1,165 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401127 # Number of seconds simulated -sim_ticks 2401127269500 # Number of ticks simulated -final_tick 2401127269500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403594 # Number of seconds simulated +sim_ticks 2403594294500 # Number of ticks simulated +final_tick 2403594294500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 142330 # Simulator instruction rate (inst/s) -host_op_rate 182788 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5664980832 # Simulator tick rate (ticks/s) -host_mem_usage 401540 # Number of bytes of host memory used -host_seconds 423.85 # Real time elapsed on the host -sim_insts 60327009 # Number of instructions simulated -sim_ops 77475387 # Number of ops (including micro ops) simulated +host_inst_rate 127977 # Simulator instruction rate (inst/s) +host_op_rate 164357 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5098961801 # Simulator tick rate (ticks/s) +host_mem_usage 401544 # Number of bytes of host memory used +host_seconds 471.39 # Real time elapsed on the host +sim_insts 60327163 # Number of instructions simulated +sim_ops 77476179 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7145552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 511136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7143248 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 78912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 687680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 78528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 688768 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 173184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1243936 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 78912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 173184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3744064 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1523456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 157860 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1334500 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759880 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.inst 171584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1244640 # Number of bytes read from this memory +system.physmem.bytes_read::total 124657616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 511136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 78528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 171584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 761248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3742592 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1523692 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 157804 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1334320 # Number of bytes written to this memory +system.physmem.bytes_written::total 6758408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 111683 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14189 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111647 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10762 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2706 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 19444 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512400 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58501 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 380864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39465 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 333625 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812455 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47818820 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.inst 2681 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 19455 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512355 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58478 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 380923 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 333580 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812432 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47769739 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2975916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212655 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2971903 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32865 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 286399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286558 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 72126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 518063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51917488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 72126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318024 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1559294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 634475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 65744 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 555781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815294 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1559294 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47818820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 71386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 517824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212655 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32671 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 71386 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557081 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 633922 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 65653 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 555135 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557081 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47769739 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3610391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3605825 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32865 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 352143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 352211 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 72126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1073844 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54732782 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12420439 # Total number of read requests seen -system.physmem.writeReqs 390212 # Total number of write requests seen -system.physmem.cpureqs 53603 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 794908096 # Total number of bytes read from memory -system.physmem.bytesWritten 24973568 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 101274592 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2588168 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2354 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 776339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 775940 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 776092 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 776425 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 777292 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 776809 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 775620 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 775424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 775584 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 776041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 775688 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 776201 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 777483 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 777433 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 776149 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 775918 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 25457 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 25320 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 25407 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25903 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 26305 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 71386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1072960 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54674794 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13478004 # Total number of read requests seen +system.physmem.writeReqs 390132 # Total number of write requests seen +system.physmem.cpureqs 53582 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 862592256 # Total number of bytes read from memory +system.physmem.bytesWritten 24968448 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 109734944 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2586588 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2357 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 837777 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 837385 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 837533 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 838713 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 839756 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 839804 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 839650 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 840522 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 841715 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 844141 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 844930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 846498 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 848135 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 848079 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 846803 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 846563 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 25455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 25327 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 25409 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25902 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 26300 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 26088 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 23374 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 23183 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 23262 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 21306 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 21574 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24259 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 23496 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25421 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 23356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 23184 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 23261 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 21260 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 21580 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24253 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 23500 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25208 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 14413 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400092064000 # Total gap between requests +system.physmem.totGap 2402559124000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 12386304 # Categorize read packet sizes +system.physmem.readPktSize::3 13443872 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 34127 # Categorize read packet sizes +system.physmem.readPktSize::6 34124 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 373090 # Categorize write packet sizes +system.physmem.writePktSize::2 373031 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17122 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 803531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 778993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 809862 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3060255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2298083 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2298065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2262695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 12148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 12111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 22591 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 33065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 22584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1614 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17101 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 870514 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 846629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 868006 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3320451 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2492641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2492474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2466384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 13873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 13526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 25989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 38321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 25827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 820 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -173,161 +173,191 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2548 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 16974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 16970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 16964 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 16959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 16952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 16947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 16944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 16942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 16934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16933 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 16973 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 16965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 16963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 16956 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 16951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 16946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 16941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 16929 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16923 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 16918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16918 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 14497 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14472 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 14454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14453 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 14449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14427 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 20861 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 39302.074493 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6009.687839 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33098.413312 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 3004 14.40% 14.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 1328 6.37% 20.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 811 3.89% 24.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 565 2.71% 27.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 381 1.83% 29.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 362 1.74% 30.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 265 1.27% 32.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 238 1.14% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 172 0.82% 34.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 151 0.72% 34.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 130 0.62% 35.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 127 0.61% 36.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 66 0.32% 36.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 86 0.41% 36.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 45 0.22% 37.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 78 0.37% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 36 0.17% 37.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 26 0.12% 37.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 22 0.11% 37.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 43 0.21% 38.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 28 0.13% 38.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 87 0.42% 38.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 101 0.48% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 96 0.46% 39.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 23 0.11% 39.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 38 0.18% 39.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 20 0.10% 39.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 38 0.18% 40.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 12 0.06% 40.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 22 0.11% 40.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 8 0.04% 40.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 17 0.08% 40.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 10 0.05% 40.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 9 0.04% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 4 0.02% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 3 0.01% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 5 0.02% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 9 0.04% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 4 0.02% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 4 0.02% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 2 0.01% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 2 0.01% 40.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 6 0.03% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 3 0.01% 40.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 7 0.03% 40.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 1 0.00% 40.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 2 0.01% 40.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 4 0.02% 40.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 1 0.00% 40.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 3 0.01% 40.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 3 0.01% 40.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 8 0.04% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 2 0.01% 40.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 3 0.01% 40.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 1 0.00% 40.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 3 0.01% 40.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 2 0.01% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 2 0.01% 40.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 2 0.01% 40.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 1 0.00% 40.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 1 0.00% 40.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 1 0.00% 40.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 6 0.03% 40.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 2 0.01% 40.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 3 0.01% 40.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 40.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 40.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 2 0.01% 40.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 1 0.00% 40.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 1 0.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 1 0.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 1 0.00% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 1 0.00% 41.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 41.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 4 0.02% 41.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 41.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 41.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 1 0.00% 41.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 2 0.01% 41.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 1 0.00% 41.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 2 0.01% 41.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 41.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 41.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 1 0.00% 41.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 2 0.01% 41.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11167 1 0.00% 41.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 1 0.00% 41.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 41.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15168-15199 1 0.00% 41.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 41.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 1 0.00% 41.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 1 0.00% 41.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 2 0.01% 41.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 1 0.00% 41.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 12093 57.97% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::127424-127455 1 0.00% 99.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 181 0.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 20861 # Bytes accessed per row activation -system.physmem.totQLat 241895050750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 315493767000 # Sum of mem lat for all requests -system.physmem.totBusLat 62102190000 # Total cycles spent in databus access -system.physmem.totBankLat 11496526250 # Total cycles spent in bank access -system.physmem.avgQLat 19475.57 # Average queueing delay per request -system.physmem.avgBankLat 925.61 # Average bank access latency per request +system.physmem.wrQLenPdf::29 14444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14424 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22008 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 40328.985823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 6672.817905 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32794.691650 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 2992 13.60% 13.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 1338 6.08% 19.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 840 3.82% 23.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 568 2.58% 26.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 356 1.62% 27.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 350 1.59% 29.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 274 1.25% 30.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 258 1.17% 31.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 159 0.72% 32.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 152 0.69% 33.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 129 0.59% 33.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 166 0.75% 34.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 85 0.39% 34.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 79 0.36% 35.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 56 0.25% 35.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 66 0.30% 35.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 41 0.19% 35.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 34 0.15% 36.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 24 0.11% 36.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 38 0.17% 36.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 28 0.13% 36.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 94 0.43% 36.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 111 0.50% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 95 0.43% 37.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 19 0.09% 37.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 37 0.17% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 24 0.11% 38.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 40 0.18% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 12 0.05% 38.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 17 0.08% 38.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 8 0.04% 38.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 19 0.09% 38.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 12 0.05% 38.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 11 0.05% 38.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 5 0.02% 38.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 5 0.02% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 3 0.01% 38.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 10 0.05% 38.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 2 0.01% 38.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 1 0.00% 38.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 1 0.00% 38.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 5 0.02% 38.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 5 0.02% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 5 0.02% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 3 0.01% 38.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 1 0.00% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 1 0.00% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 7 0.03% 39.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 2 0.01% 39.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 3 0.01% 39.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 4 0.02% 39.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 7 0.03% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 2 0.01% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 2 0.01% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 3 0.01% 39.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 2 0.01% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 1 0.00% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 2 0.01% 39.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 3 0.01% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 3 0.01% 39.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 7 0.03% 39.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 3 0.01% 39.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 1 0.00% 39.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 39.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 2 0.01% 39.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4831 3 0.01% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 1 0.00% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 1 0.00% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 1 0.00% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 2 0.01% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 1 0.00% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 2 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 8 0.04% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 1 0.00% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6431 1 0.00% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 1 0.00% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 4 0.02% 39.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 2 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.01% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7455 1 0.00% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 2 0.01% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 1 0.00% 39.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 1 0.00% 39.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 2 0.01% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 1 0.00% 39.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 3 0.01% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8479 1 0.00% 39.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8607 1 0.00% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8735 1 0.00% 39.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12319 3 0.01% 39.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 1 0.00% 39.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13952-13983 1 0.00% 39.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14623 1 0.00% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19231 1 0.00% 39.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19487 1 0.00% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19999 1 0.00% 39.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21791 1 0.00% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22559 2 0.01% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23327 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23583 1 0.00% 39.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28191 1 0.00% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30751 1 0.00% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32031 2 0.01% 39.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33055 2 0.01% 39.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33311 2 0.01% 39.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33567 2 0.01% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 1 0.00% 39.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 1 0.00% 39.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35871 1 0.00% 39.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36895 1 0.00% 39.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37919 1 0.00% 39.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38943 1 0.00% 39.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40991 1 0.00% 39.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-42015 1 0.00% 39.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42783 1 0.00% 39.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46111 1 0.00% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49408-49439 1 0.00% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::50944-50975 1 0.00% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53248-53279 1 0.00% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54303 1 0.00% 39.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54464-54495 1 0.00% 39.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56576-56607 1 0.00% 39.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58240-58271 1 0.00% 39.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58624-58655 1 0.00% 39.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::59392-59423 1 0.00% 39.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 13106 59.55% 99.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131103 181 0.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22008 # Bytes accessed per row activation +system.physmem.totQLat 259991264250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 339839911750 # Sum of mem lat for all requests +system.physmem.totBusLat 67390020000 # Total cycles spent in databus access +system.physmem.totBankLat 12458627500 # Total cycles spent in bank access +system.physmem.avgQLat 19290.04 # Average queueing delay per request +system.physmem.avgBankLat 924.37 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25401.18 # Average memory access latency -system.physmem.avgRdBW 331.06 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.18 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25214.41 # Average memory access latency +system.physmem.avgRdBW 358.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 45.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.08 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.67 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.busUtil 2.88 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.14 # Average read queue length over time system.physmem.avgWrQLen 0.40 # Average write queue length over time -system.physmem.readRowHits 12404411 # Number of row buffer hits during reads -system.physmem.writeRowHits 385376 # Number of row buffer hits during writes +system.physmem.readRowHits 13460829 # Number of row buffer hits during reads +system.physmem.writeRowHits 385299 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.76 # Row buffer hit rate for writes -system.physmem.avgGap 187351.30 # Average gap between requests +system.physmem.avgGap 173243.12 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -340,315 +370,315 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55731119 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 12759502 # Transaction distribution -system.membus.trans_dist::ReadResp 12759502 # Transaction distribution -system.membus.trans_dist::WriteReq 375940 # Transaction distribution -system.membus.trans_dist::WriteResp 375940 # Transaction distribution -system.membus.trans_dist::Writeback 17122 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2354 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2354 # Transaction distribution -system.membus.trans_dist::ReadExReq 26440 # Transaction distribution -system.membus.trans_dist::ReadExResp 26440 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836280 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1572986 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 24772608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 24772608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 736482 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 25608888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 224 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 26345594 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4772328 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5513215 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 99090432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 99090432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 740439 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 103862760 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 104603647 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817510 # Total data (bytes) +system.membus.throughput 55672102 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13817032 # Transaction distribution +system.membus.trans_dist::ReadResp 13817032 # Transaction distribution +system.membus.trans_dist::WriteReq 375870 # Transaction distribution +system.membus.trans_dist::WriteResp 375870 # Transaction distribution +system.membus.trans_dist::Writeback 17101 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2357 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2357 # Transaction distribution +system.membus.trans_dist::ReadExReq 26474 # Transaction distribution +system.membus.trans_dist::ReadExResp 26474 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 836141 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1572823 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887744 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26887744 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 736448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 27723885 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28460567 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 4770556 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5511420 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107550976 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 740396 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 112321532 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113062396 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133813146 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 420513000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 415491000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 13413227250 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 14469192250 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.6 # Layer utilization (%) -system.membus.reqLayer3.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 218000 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 1495675396 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1494318294 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 27962648500 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.replacements 63244 # number of replacements -system.l2c.tagsinuse 50337.430960 # Cycle average of tags in use -system.l2c.total_refs 1749337 # Total number of references to valid blocks. -system.l2c.sampled_refs 128639 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.598808 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374950539000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36831.801957 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5222.807479 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3773.258681 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993312 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 729.926692 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 767.531716 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 5.853930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1434.252547 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1571.004504 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562009 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.079694 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057575 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.011138 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011712 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000089 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.021885 # 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number of ReadReq hits -system.l2c.ReadReq_hits::total 1290913 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597640 # number of Writeback hits -system.l2c.Writeback_hits::total 597640 # number of Writeback hits +system.membus.respLayer2.occupancy 30346616000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.l2c.tags.replacements 63199 # number of replacements +system.l2c.tags.tagsinuse 50350.442050 # Cycle average of tags in use +system.l2c.tags.total_refs 1748255 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128595 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.595046 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375554811500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36868.064409 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5218.650868 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3758.862884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 721.252750 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 766.461515 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 4.929404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1435.478788 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1575.747972 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562562 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # 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number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18369 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4267 # number of overall hits -system.l2c.overall_hits::cpu2.inst 282351 # number of overall hits -system.l2c.overall_hits::cpu2.data 174550 # number of overall hits -system.l2c.overall_hits::total 1404564 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60793 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19412 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33407 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113612 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3220 # 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mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.114726 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.103023 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.022453 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000386 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009039 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.114726 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000332 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009416 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.103023 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022453 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61622.920133 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63731.587239 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63532.977755 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61304.661716 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 63428.656361 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63943.823529 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.054852 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50485.006212 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57409.873306 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 54920.116075 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.336700 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51311.783715 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 57383.588094 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 55202.081548 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60302.311436 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51699.757372 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65644.401330 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58211.212881 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56811.908735 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60051.344743 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52409.126121 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 67371.036927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 58144.499451 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57112.994971 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -801,52 +831,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58868329 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1038711 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1038710 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 375940 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 375940 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 275281 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80190 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80190 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 843862 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2343005 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15512 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 51160 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 3253539 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26980864 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38469375 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 84004 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 65556143 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141250094 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100256 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2175069728 # Layer occupancy (ticks) +system.toL2Bus.throughput 58801079 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1037457 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1037456 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 375870 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 375870 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 275194 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1507 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80165 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80165 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 841603 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 2342492 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 15419 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50807 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 3250321 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 26910144 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 38454204 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 21476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 82556 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 65468380 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141234858 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 99080 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2173969472 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1900577406 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1896208409 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1863798035 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1871332229 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10055959 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10065963 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30318675 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30326428 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48814240 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 12751762 # Transaction distribution -system.iobus.trans_dist::ReadResp 12751762 # Transaction distribution -system.iobus.trans_dist::WriteReq 2783 # Transaction distribution -system.iobus.trans_dist::WriteResp 2783 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48764132 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13809327 # Transaction distribution +system.iobus.trans_dist::ReadResp 13809327 # Transaction distribution +system.iobus.trans_dist::WriteReq 2769 # Transaction distribution +system.iobus.trans_dist::WriteResp 2769 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -862,17 +892,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736482 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 24772608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 11428 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 3102 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 736448 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26887744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.uart.pio 11368 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 3090 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 262 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 721384 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.cf_ctrl.pio 721420 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -888,16 +918,16 @@ system.iobus.pkt_count::system.realview.sci_fake.pio 16 system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 24772608 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 25509090 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::system.iocache.cpu_side 26887744 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27624192 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -913,17 +943,17 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740439 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 99090432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 15392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 6204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 740396 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550976 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.uart.pio 15332 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 6180 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 524 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717707 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 717744 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -939,14 +969,14 @@ system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 99090432 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 99830871 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209202 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7987000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::system.iocache.cpu_side 107550976 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108291372 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209190 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7942000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1551000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1545000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 131000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) @@ -956,7 +986,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361193000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 361211000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -988,34 +1018,34 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 12386304000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733699000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13443872000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 733679000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 24772608000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 36855511000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8064428 # DTB read hits -system.cpu0.dtb.read_misses 6238 # DTB read misses -system.cpu0.dtb.write_hits 6663212 # DTB write hits -system.cpu0.dtb.write_misses 2045 # DTB write misses +system.cpu0.dtb.read_hits 8066197 # DTB read hits +system.cpu0.dtb.read_misses 6232 # DTB read misses +system.cpu0.dtb.write_hits 6664992 # DTB write hits +system.cpu0.dtb.write_misses 2050 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5690 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5697 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 114 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8070666 # DTB read accesses -system.cpu0.dtb.write_accesses 6665257 # DTB write accesses +system.cpu0.dtb.read_accesses 8072429 # DTB read accesses +system.cpu0.dtb.write_accesses 6667042 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14727640 # DTB hits -system.cpu0.dtb.misses 8283 # DTB misses -system.cpu0.dtb.accesses 14735923 # DTB accesses -system.cpu0.itb.inst_hits 32885888 # ITB inst hits +system.cpu0.dtb.hits 14731189 # DTB hits +system.cpu0.dtb.misses 8282 # DTB misses +system.cpu0.dtb.accesses 14739471 # DTB accesses +system.cpu0.itb.inst_hits 32886560 # ITB inst hits system.cpu0.itb.inst_misses 3493 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1023,409 +1053,409 @@ system.cpu0.itb.write_hits 0 # DT system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2597 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2599 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32889381 # ITB inst accesses -system.cpu0.itb.hits 32885888 # DTB hits +system.cpu0.itb.inst_accesses 32890053 # ITB inst accesses +system.cpu0.itb.hits 32886560 # DTB hits system.cpu0.itb.misses 3493 # DTB misses -system.cpu0.itb.accesses 32889381 # DTB accesses -system.cpu0.numCycles 114194187 # number of cpu cycles simulated +system.cpu0.itb.accesses 32890053 # DTB accesses +system.cpu0.numCycles 114224752 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32400694 # Number of instructions committed -system.cpu0.committedOps 42604041 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37748945 # Number of integer alu accesses +system.cpu0.committedInsts 32403519 # Number of instructions committed +system.cpu0.committedOps 42610516 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37756553 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1185552 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4241024 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37748945 # number of integer instructions +system.cpu0.num_func_calls 1186218 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4240514 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37756553 # number of integer instructions system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 192241357 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39867524 # number of times the integer registers were written +system.cpu0.num_int_register_reads 192274568 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39869839 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15390684 # number of memory refs -system.cpu0.num_load_insts 8430090 # Number of load instructions -system.cpu0.num_store_insts 6960594 # Number of store instructions -system.cpu0.num_idle_cycles 13437222906.022394 # Number of idle cycles -system.cpu0.num_busy_cycles -13323028719.022394 # Number of busy cycles -system.cpu0.not_idle_fraction -116.669938 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.669938 # Percentage of idle cycles +system.cpu0.num_mem_refs 15395098 # number of memory refs +system.cpu0.num_load_insts 8432454 # Number of load instructions +system.cpu0.num_store_insts 6962644 # Number of store instructions +system.cpu0.num_idle_cycles 13455441823.416426 # Number of idle cycles +system.cpu0.num_busy_cycles -13341217071.416426 # Number of busy cycles +system.cpu0.not_idle_fraction -116.797952 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.797952 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.replacements 891212 # number of replacements -system.cpu0.icache.tagsinuse 511.602596 # Cycle average of tags in use -system.cpu0.icache.total_refs 44302670 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 891724 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.682043 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8165076000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 482.545707 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 22.025938 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 7.030951 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.942472 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.043019 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.013732 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32419122 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8206609 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3676939 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44302670 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32419122 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8206609 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3676939 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44302670 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32419122 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8206609 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3676939 # number of overall hits -system.cpu0.icache.overall_hits::total 44302670 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469447 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 136775 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 309614 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 915836 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469447 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 136775 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 309614 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 915836 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469447 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 136775 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 309614 # number of overall misses -system.cpu0.icache.overall_misses::total 915836 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1859465000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4163389481 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6022854481 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1859465000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4163389481 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6022854481 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1859465000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4163389481 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6022854481 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32888569 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8343384 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3986553 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45218506 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32888569 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8343384 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3986553 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45218506 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32888569 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8343384 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3986553 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45218506 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014274 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016393 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.077665 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020254 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014274 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016393 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.077665 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020254 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014274 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016393 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.077665 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020254 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13595.064888 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13447.032373 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6576.346072 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13595.064888 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13447.032373 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6576.346072 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13595.064888 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13447.032373 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6576.346072 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3767 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 891011 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.603846 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 44299550 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891523 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 49.689744 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 482.268023 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 22.017936 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 7.317887 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.941930 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.043004 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.014293 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32418840 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8204019 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3676691 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44299550 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32418840 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8204019 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3676691 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44299550 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32418840 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8204019 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3676691 # number of overall hits +system.cpu0.icache.overall_hits::total 44299550 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 470403 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 136004 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 309613 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916020 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 470403 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 136004 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 309613 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5130878455 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1652150000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478728455 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5130878455 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27438525500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28895903000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56334428500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439019500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930302419 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15369321919 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28877545000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42826205419 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71703750419 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033512 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029420 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014862 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021489 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019306 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007991 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049609 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044631 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020906 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011943 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028508 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025777 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011943 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12248.784565 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12932.789238 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12715.795501 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28634.922499 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32101.463845 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30835.831035 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11121.992166 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11498.407590 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.013934 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597664 # number of writebacks +system.cpu0.dcache.writebacks::total 597664 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 148092 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 148092 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 531664 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 531664 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 435 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 435 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 679756 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 679756 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 679756 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 679756 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65173 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 140243 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 205416 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29715 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 51904 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81619 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1793 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3438 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5231 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94888 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 192147 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 287035 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94888 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 192147 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 287035 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 798815000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1812392117 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2611207117 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 862528251 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1666606492 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2529134743 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19945250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39526251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59471501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1661343251 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3478998609 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5140341860 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1661343251 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3478998609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5140341860 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27433716000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893863250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56327579250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1437767401 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13930226833 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15367994234 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28871483401 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42824090083 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71695573484 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033504 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029403 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014852 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021469 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019323 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049848 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044720 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020904 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011936 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028501 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025771 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011936 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12256.839489 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12923.226949 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12711.800040 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29026.695305 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32109.403745 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30987.083191 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11123.954267 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.873473 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11369.050086 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17389.405214 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18103.197085 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17867.042013 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17508.465254 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18105.922075 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17908.414862 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1438,34 +1468,34 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2160353 # DTB read hits -system.cpu1.dtb.read_misses 2072 # DTB read misses -system.cpu1.dtb.write_hits 1463428 # DTB write hits -system.cpu1.dtb.write_misses 375 # DTB write misses +system.cpu1.dtb.read_hits 2159851 # DTB read hits +system.cpu1.dtb.read_misses 2083 # DTB read misses +system.cpu1.dtb.write_hits 1460405 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1741 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1742 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 41 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 44 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2162425 # DTB read accesses -system.cpu1.dtb.write_accesses 1463803 # DTB write accesses +system.cpu1.dtb.read_accesses 2161934 # DTB read accesses +system.cpu1.dtb.write_accesses 1460778 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3623781 # DTB hits -system.cpu1.dtb.misses 2447 # DTB misses -system.cpu1.dtb.accesses 3626228 # DTB accesses -system.cpu1.itb.inst_hits 8343384 # ITB inst hits -system.cpu1.itb.inst_misses 1170 # ITB inst misses +system.cpu1.dtb.hits 3620256 # DTB hits +system.cpu1.dtb.misses 2456 # DTB misses +system.cpu1.dtb.accesses 3622712 # DTB accesses +system.cpu1.itb.inst_hits 8340023 # ITB inst hits +system.cpu1.itb.inst_misses 1172 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -1474,66 +1504,66 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8344554 # ITB inst accesses -system.cpu1.itb.hits 8343384 # DTB hits -system.cpu1.itb.misses 1170 # DTB misses -system.cpu1.itb.accesses 8344554 # DTB accesses -system.cpu1.numCycles 576594127 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8341195 # ITB inst accesses +system.cpu1.itb.hits 8340023 # DTB hits +system.cpu1.itb.misses 1172 # DTB misses +system.cpu1.itb.accesses 8341195 # DTB accesses +system.cpu1.numCycles 580203695 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8139213 # Number of instructions committed -system.cpu1.committedOps 10387341 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9296011 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses -system.cpu1.num_func_calls 319457 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1149983 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9296011 # number of integer instructions -system.cpu1.num_fp_insts 2143 # number of float instructions -system.cpu1.num_int_register_reads 53626328 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10059981 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read +system.cpu1.committedInsts 8134078 # Number of instructions committed +system.cpu1.committedOps 10379103 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9286356 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2127 # Number of float alu accesses +system.cpu1.num_func_calls 319009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1149936 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9286356 # number of integer instructions +system.cpu1.num_fp_insts 2127 # number of float instructions +system.cpu1.num_int_register_reads 53580768 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10053974 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1614 # number of times the floating registers were read system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3800206 # number of memory refs -system.cpu1.num_load_insts 2257531 # Number of load instructions -system.cpu1.num_store_insts 1542675 # Number of store instructions -system.cpu1.num_idle_cycles 550949024.070645 # Number of idle cycles -system.cpu1.num_busy_cycles 25645102.929355 # Number of busy cycles -system.cpu1.not_idle_fraction 0.044477 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.955523 # Percentage of idle cycles +system.cpu1.num_mem_refs 3795930 # number of memory refs +system.cpu1.num_load_insts 2256544 # Number of load instructions +system.cpu1.num_store_insts 1539386 # Number of store instructions +system.cpu1.num_idle_cycles 585938491.751716 # Number of idle cycles +system.cpu1.num_busy_cycles -5734796.751716 # Number of busy cycles +system.cpu1.not_idle_fraction -0.009884 # Percentage of non-idle cycles +system.cpu1.idle_fraction 1.009884 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4706679 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3828645 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 220746 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3114772 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2519361 # Number of BTB hits +system.cpu2.branchPred.lookups 4707573 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3829869 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221083 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3125328 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2519731 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.884283 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411150 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21524 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.622930 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 410392 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21556 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10881090 # DTB read hits -system.cpu2.dtb.read_misses 22334 # DTB read misses -system.cpu2.dtb.write_hits 3233578 # DTB write hits -system.cpu2.dtb.write_misses 5962 # DTB write misses +system.cpu2.dtb.read_hits 10881991 # DTB read hits +system.cpu2.dtb.read_misses 22472 # DTB read misses +system.cpu2.dtb.write_hits 3235005 # DTB write hits +system.cpu2.dtb.write_misses 5987 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2292 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 695 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.flush_entries 2290 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 674 # Number of TLB faults due to alignment restrictions system.cpu2.dtb.prefetch_faults 165 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10903424 # DTB read accesses -system.cpu2.dtb.write_accesses 3239540 # DTB write accesses +system.cpu2.dtb.perms_faults 480 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10904463 # DTB read accesses +system.cpu2.dtb.write_accesses 3240992 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14114668 # DTB hits -system.cpu2.dtb.misses 28296 # DTB misses -system.cpu2.dtb.accesses 14142964 # DTB accesses -system.cpu2.itb.inst_hits 3988029 # ITB inst hits -system.cpu2.itb.inst_misses 4597 # ITB inst misses +system.cpu2.dtb.hits 14116996 # DTB hits +system.cpu2.dtb.misses 28459 # DTB misses +system.cpu2.dtb.accesses 14145455 # DTB accesses +system.cpu2.itb.inst_hits 3987789 # ITB inst hits +system.cpu2.itb.inst_misses 4600 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1542,114 +1572,114 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1713 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1704 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 994 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1012 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 3992626 # ITB inst accesses -system.cpu2.itb.hits 3988029 # DTB hits -system.cpu2.itb.misses 4597 # DTB misses -system.cpu2.itb.accesses 3992626 # DTB accesses -system.cpu2.numCycles 88357796 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 3992389 # ITB inst accesses +system.cpu2.itb.hits 3987789 # DTB hits +system.cpu2.itb.misses 4600 # DTB misses +system.cpu2.itb.accesses 3992389 # DTB accesses +system.cpu2.numCycles 88356031 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9310481 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32575007 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4706679 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2930511 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6844695 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1834626 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50535 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18792292 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 211 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 834 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32689 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721380 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3986556 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 271694 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2030 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37012176 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.054575 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.442886 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9299223 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32583630 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4707573 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2930123 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6845670 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1836223 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50265 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18768642 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 458 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 865 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32747 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 722165 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3986309 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 272069 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2032 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36980430 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.055775 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.444098 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30172484 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 383589 1.04% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509700 1.38% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 816595 2.21% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 649845 1.76% 87.90% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 340688 0.92% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1002283 2.71% 91.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 233105 0.63% 92.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2903887 7.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30139736 81.50% 81.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382786 1.04% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509834 1.38% 83.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 817196 2.21% 86.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 649833 1.76% 87.88% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 340544 0.92% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1001875 2.71% 91.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 233328 0.63% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2905298 7.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37012176 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053268 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368672 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9923582 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19398911 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6192413 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 289708 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1206624 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608704 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53227 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36668894 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 179672 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1206624 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10457732 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6796532 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11090349 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5929465 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1530564 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34717207 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2441 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 375073 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 892617 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 118 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37295857 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 158754403 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 158727276 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27127 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25598469 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11697387 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231672 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208131 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3300393 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6518889 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3789656 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530954 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 691805 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31588093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511099 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34136489 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54725 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7434189 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19599124 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 154239 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37012176 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.922304 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.578312 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36980430 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053280 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.368777 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9914058 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19374148 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6194025 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 289491 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1207748 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608647 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53413 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36680754 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 180211 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1207748 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10448619 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6814881 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11054882 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5930497 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1522855 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34729839 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2439 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 374808 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 885539 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 119 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37310430 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 158812282 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 158784890 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27392 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25602072 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11708357 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 230914 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207478 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3294482 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6519802 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3791560 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 528920 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 689934 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31598942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 510602 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34143520 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55455 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7440971 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19631999 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154198 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36980430 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.923286 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.579350 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24481195 66.14% 66.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3912173 10.57% 76.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2318887 6.27% 82.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2014061 5.44% 88.42% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2743513 7.41% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 884212 2.39% 98.22% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 492586 1.33% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 130661 0.35% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34888 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24453619 66.13% 66.13% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3907365 10.57% 76.69% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2316831 6.27% 82.96% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2013006 5.44% 88.40% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2745101 7.42% 95.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 885827 2.40% 98.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 492123 1.33% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 131266 0.35% 99.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35292 0.10% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37012176 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36980430 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 18493 1.21% 1.21% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18547 1.21% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 1 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.21% # attempts to use FU when none available @@ -1678,13 +1708,13 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.21% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.21% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.21% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1405660 91.60% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110389 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407485 91.52% 92.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 111832 7.27% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61311 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19306288 56.56% 56.74% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 26277 0.08% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61314 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19310512 56.56% 56.74% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 26216 0.08% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.81% # Type of FU issued @@ -1697,135 +1727,135 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.81% # Ty system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 7 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 369 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.81% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 56.81% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.81% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11344167 33.23% 90.05% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3398057 9.95% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11345203 33.23% 90.04% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3399891 9.96% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34136489 # Type of FU issued -system.cpu2.iq.rate 0.386344 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534543 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044953 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106895526 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39538518 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27366143 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7075 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3717 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3145 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35605938 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3783 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206498 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34143520 # Type of FU issued +system.cpu2.iq.rate 0.386431 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537865 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.045041 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106882112 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39555566 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27370238 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7010 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3779 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3144 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35616337 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3734 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206224 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1561517 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1841 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9166 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 566678 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1563789 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2001 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9138 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 567371 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5349938 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 380447 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5351721 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 380538 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1206624 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5097630 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 92333 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32182024 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61203 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6518889 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3789656 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368677 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31621 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2335 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9166 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105355 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88176 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193531 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33238932 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11092763 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 897557 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1207748 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5118466 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 92736 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32192718 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 58170 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6519802 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3791560 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368228 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31927 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2425 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9138 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105201 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88411 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193612 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33245955 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11093572 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 897565 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82832 # number of nop insts executed -system.cpu2.iew.exec_refs 14457569 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3671446 # Number of branches executed -system.cpu2.iew.exec_stores 3364806 # Number of stores executed -system.cpu2.iew.exec_rate 0.376186 # Inst execution rate -system.cpu2.iew.wb_sent 32811396 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27369288 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15602510 # num instructions producing a value -system.cpu2.iew.wb_consumers 28268763 # num instructions consuming a value +system.cpu2.iew.exec_nop 83174 # number of nop insts executed +system.cpu2.iew.exec_refs 14459722 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3671566 # Number of branches executed +system.cpu2.iew.exec_stores 3366150 # Number of stores executed +system.cpu2.iew.exec_rate 0.376273 # Inst execution rate +system.cpu2.iew.wb_sent 32817620 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27373382 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15610718 # num instructions producing a value +system.cpu2.iew.wb_consumers 28284338 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309755 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.551935 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309808 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.551921 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7374898 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356860 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168297 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35805367 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.685358 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.714033 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7382656 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356404 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168463 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35772498 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.686059 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714745 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27231349 76.05% 76.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4142496 11.57% 87.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1257531 3.51% 91.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 645964 1.80% 92.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 562986 1.57% 94.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317406 0.89% 95.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 386660 1.08% 96.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 302677 0.85% 97.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 958298 2.68% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27202420 76.04% 76.04% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4136400 11.56% 87.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1256838 3.51% 91.12% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 645513 1.80% 92.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 564789 1.58% 94.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319868 0.89% 95.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 386889 1.08% 96.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302652 0.85% 97.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 957129 2.68% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35805367 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19842604 # Number of instructions committed -system.cpu2.commit.committedOps 24539507 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35772498 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19845047 # Number of instructions committed +system.cpu2.commit.committedOps 24542041 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8180350 # Number of memory references committed -system.cpu2.commit.loads 4957372 # Number of loads committed -system.cpu2.commit.membars 94561 # Number of memory barriers committed -system.cpu2.commit.branches 3152552 # Number of branches committed -system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21772655 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294654 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 958298 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8180202 # Number of memory references committed +system.cpu2.commit.loads 4956013 # Number of loads committed +system.cpu2.commit.membars 94398 # Number of memory barriers committed +system.cpu2.commit.branches 3153060 # Number of branches committed +system.cpu2.commit.fp_insts 3107 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21774748 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294560 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 957129 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66237138 # The number of ROB reads -system.cpu2.rob.rob_writes 65080734 # The number of ROB writes -system.cpu2.timesIdled 362582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51345620 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3559271384 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19787102 # Number of Instructions Simulated -system.cpu2.committedOps 24484005 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19787102 # Number of Instructions Simulated -system.cpu2.cpi 4.465424 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.465424 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.223943 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.223943 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153570043 # number of integer regfile reads -system.cpu2.int_regfile_writes 29228694 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22407 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes -system.cpu2.misc_regfile_reads 8993137 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241651 # number of misc regfile writes -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.rob.rob_reads 66215885 # The number of ROB reads +system.cpu2.rob.rob_writes 65102408 # The number of ROB writes +system.cpu2.timesIdled 362250 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51375601 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3556629546 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19789566 # Number of Instructions Simulated +system.cpu2.committedOps 24486560 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19789566 # Number of Instructions Simulated +system.cpu2.cpi 4.464779 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.464779 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.223975 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.223975 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153595531 # number of integer regfile reads +system.cpu2.int_regfile_writes 29235365 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22348 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20810 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8997423 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241258 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1834,10 +1864,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1181598504500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1181598504500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1181598504500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1279969503000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279969503000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1279969503000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 1abf69682..c58b97d9e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,150 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.548434 # Number of seconds simulated -sim_ticks 2548433543500 # Number of ticks simulated -final_tick 2548433543500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.548515 # Number of seconds simulated +sim_ticks 2548515380000 # Number of ticks simulated +final_tick 2548515380000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62524 # Simulator instruction rate (inst/s) -host_op_rate 80452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2641694597 # Simulator tick rate (ticks/s) -host_mem_usage 403600 # Number of bytes of host memory used -host_seconds 964.70 # Real time elapsed on the host -sim_insts 60316814 # Number of instructions simulated -sim_ops 77611972 # Number of ops (including micro ops) simulated +host_inst_rate 61977 # Simulator instruction rate (inst/s) +host_op_rate 79748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2618667230 # Simulator tick rate (ticks/s) +host_mem_usage 403588 # Number of bytes of host memory used +host_seconds 973.21 # Real time elapsed on the host +sim_insts 60316341 # Number of instructions simulated +sim_ops 77611368 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 441408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4859600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 357888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4231256 # Number of bytes read from this memory -system.physmem.bytes_read::total 131003368 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 441408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 357888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799296 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783552 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1678512 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1337588 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799652 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 440128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4850064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 360448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4242200 # Number of bytes read from this memory +system.physmem.bytes_read::total 131005928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 440128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 360448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785088 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1679112 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1336988 # Number of bytes written to this memory +system.physmem.bytes_written::total 6801188 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 75965 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5592 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 66119 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293431 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59118 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 419628 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 334397 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47523518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 452 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 6877 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 75816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5632 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 66290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293471 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59142 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 419778 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 334247 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813167 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47521992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 173208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1906897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 140435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1660336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51405448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 173208 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 140435 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 313642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1484658 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 658645 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 524867 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2668169 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1484658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47523518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 172700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1903094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 141435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1664577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51404802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 172700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 141435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1485213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 658859 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 524614 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2668686 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1485213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47521992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 173208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2565541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 140435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2185203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54073617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293431 # Total number of read requests seen -system.physmem.writeReqs 813143 # Total number of write requests seen -system.physmem.cpureqs 218375 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978779584 # Total number of bytes read from memory -system.physmem.bytesWritten 52041152 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131003368 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799652 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 955869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955530 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955690 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 955877 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 955758 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955993 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 955787 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956236 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955946 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955507 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955113 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956214 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 172700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2561953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 141435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2189191 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54073488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293471 # Total number of read requests seen +system.physmem.writeReqs 813167 # Total number of write requests seen +system.physmem.cpureqs 218464 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978782144 # Total number of bytes read from memory +system.physmem.bytesWritten 52042688 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131005928 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6801188 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 15 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4709 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 955865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955532 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955688 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 955892 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 955763 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955998 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 955786 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956235 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955940 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955116 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956216 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 955973 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956070 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955978 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49130 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 48908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51082 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51266 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51202 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51317 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51099 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50759 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50417 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50974 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51268 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51122 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 956077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955981 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49128 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 48906 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50979 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51091 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51008 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51270 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51265 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51310 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51097 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50763 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50416 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50976 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51272 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51123 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32387 # Number of times wr buffer was full causing retry -system.physmem.totGap 2548432371500 # Total gap between requests +system.physmem.numWrRetry 32396 # Number of times wr buffer was full causing retry +system.physmem.totGap 2548513467000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 42 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154573 # Categorize read packet sizes +system.physmem.readPktSize::6 154613 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754025 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59118 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1060830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 986831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 991569 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3738549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2806537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2806300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2762834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 15152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 14911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 40328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3599 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59142 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1060849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 977477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3738495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2806386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2806166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2776833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 15211 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 14905 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 28917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 42926 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28925 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2287 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 2286 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2959 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1551 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,222 +156,215 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2878 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35310 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32551 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32471 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2964 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2962 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32491 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32473 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32415 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40040 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 25744.741658 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2072.132686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 32880.697508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 6923 17.29% 17.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 3475 8.68% 25.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2293 5.73% 31.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 1778 4.44% 36.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1271 3.17% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1070 2.67% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 793 1.98% 43.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 869 2.17% 46.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 551 1.38% 47.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 489 1.22% 48.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 420 1.05% 49.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 393 0.98% 50.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 261 0.65% 51.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 255 0.64% 52.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 183 0.46% 52.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 282 0.70% 53.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 123 0.31% 53.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 156 0.39% 53.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 102 0.25% 54.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 126 0.31% 54.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 80 0.20% 54.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 383 0.96% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 613 1.53% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 451 1.13% 58.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 81 0.20% 58.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 160 0.40% 58.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 53 0.13% 59.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 109 0.27% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 41 0.10% 59.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 74 0.18% 59.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 65 0.16% 59.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 23 0.06% 59.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 42 0.10% 59.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 15 0.04% 60.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 29 0.07% 60.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 18 0.04% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 27 0.07% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 12 0.03% 60.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 7 0.02% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 22 0.05% 60.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 8 0.02% 60.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 11 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 11 0.03% 60.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 16 0.04% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 19 0.05% 60.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 8 0.02% 60.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 9 0.02% 60.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 8 0.02% 60.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 6 0.01% 60.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 6 0.01% 60.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 9 0.02% 60.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 4 0.01% 60.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 9 0.02% 60.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 6 0.01% 60.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 4 0.01% 60.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 3 0.01% 60.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 10 0.02% 60.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 40 0.10% 60.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 3 0.01% 60.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 5 0.01% 60.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 4 0.01% 60.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 4 0.01% 60.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 3 0.01% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 2 0.00% 60.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 3 0.01% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 3 0.01% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 2 0.00% 60.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 5 0.01% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 1 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.00% 60.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 4 0.01% 60.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 3 0.01% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 2 0.00% 61.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 5 0.01% 61.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 6 0.01% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.00% 61.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 5 0.01% 61.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 7 0.02% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 1 0.00% 61.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 2 0.00% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 1 0.00% 61.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 6 0.01% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 1 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 2 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 1 0.00% 61.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 3 0.01% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 61.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 5 0.01% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 2 0.00% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.00% 61.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 20 0.05% 61.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 1 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.00% 61.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7135 3 0.01% 61.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 2 0.00% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7391 1 0.00% 61.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 9 0.02% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 61.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 4 0.01% 61.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 7 0.02% 61.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 3 0.01% 61.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 4 0.01% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 2 0.00% 61.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 309 0.77% 62.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 1 0.00% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9695 1 0.00% 62.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 1 0.00% 62.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 1 0.00% 62.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21312-21343 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 1 0.00% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-29983 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30592-30623 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32031 1 0.00% 62.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32799 2 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 62.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 1 0.00% 62.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 6 0.01% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35359 1 0.00% 62.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42944-42975 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58112-58143 1 0.00% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61120-61151 1 0.00% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 14762 36.87% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::123712-123743 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130048-130079 1 0.00% 99.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.wrQLenPdf::30 32442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32421 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40074 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 25722.964516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2062.503898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 32877.713086 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-95 7020 17.52% 17.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-159 3450 8.61% 26.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-223 2302 5.74% 31.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-287 1762 4.40% 36.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-351 1221 3.05% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-415 1083 2.70% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-479 782 1.95% 43.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-543 826 2.06% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-607 552 1.38% 47.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-671 527 1.32% 48.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-735 441 1.10% 49.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-799 399 1.00% 50.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-863 278 0.69% 51.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-927 274 0.68% 52.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-991 181 0.45% 52.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1055 260 0.65% 53.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1119 121 0.30% 53.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1183 146 0.36% 53.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1247 103 0.26% 54.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1311 108 0.27% 54.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1375 77 0.19% 54.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1439 372 0.93% 55.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1503 611 1.52% 57.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1567 461 1.15% 58.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1631 86 0.21% 58.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1695 174 0.43% 58.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1759 54 0.13% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1823 96 0.24% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1887 48 0.12% 59.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1951 68 0.17% 59.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2015 31 0.08% 59.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2079 67 0.17% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2143 19 0.05% 59.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2207 52 0.13% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2271 17 0.04% 60.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2335 39 0.10% 60.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2399 17 0.04% 60.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2463 35 0.09% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2527 6 0.01% 60.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2591 20 0.05% 60.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2655 5 0.01% 60.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2719 15 0.04% 60.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2783 12 0.03% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2847 19 0.05% 60.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2911 10 0.02% 60.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2975 19 0.05% 60.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3039 6 0.01% 60.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3103 14 0.03% 60.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3167 5 0.01% 60.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3231 6 0.01% 60.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3295 5 0.01% 60.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3359 9 0.02% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3423 3 0.01% 60.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3487 12 0.03% 60.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3551 4 0.01% 60.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3615 10 0.02% 60.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3679 3 0.01% 60.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3743 8 0.02% 60.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3807 7 0.02% 60.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3871 6 0.01% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3935 1 0.00% 60.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3999 7 0.02% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4063 5 0.01% 60.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4127 35 0.09% 60.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4191 5 0.01% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4255 2 0.00% 60.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4319 3 0.01% 60.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4383 7 0.02% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4447 4 0.01% 60.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4511 5 0.01% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4575 1 0.00% 60.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4639 7 0.02% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4703 1 0.00% 61.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4767 7 0.02% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4895 3 0.01% 61.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4959 3 0.01% 61.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5023 5 0.01% 61.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5151 4 0.01% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5215 2 0.00% 61.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5279 2 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5343 1 0.00% 61.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5407 5 0.01% 61.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5471 4 0.01% 61.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5535 5 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5919 3 0.01% 61.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5983 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6047 1 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6111 2 0.00% 61.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6175 4 0.01% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6303 3 0.01% 61.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6367 2 0.00% 61.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6495 5 0.01% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6559 3 0.01% 61.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6623 4 0.01% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6751 1 0.00% 61.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6815 21 0.05% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6879 2 0.00% 61.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7071 4 0.01% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7135 2 0.00% 61.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7199 3 0.01% 61.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7327 5 0.01% 61.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7391 2 0.00% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7583 3 0.01% 61.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7647 1 0.00% 61.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7711 6 0.01% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7775 1 0.00% 61.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7839 7 0.02% 61.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7903 3 0.01% 61.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7967 7 0.02% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8031 1 0.00% 61.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8095 9 0.02% 61.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8159 3 0.01% 61.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8223 305 0.76% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10112-10143 1 0.00% 62.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10271 17 0.04% 62.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13343 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14111 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14208-14239 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16704-16735 1 0.00% 62.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18463 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21023 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24768-24799 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26143 1 0.00% 62.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26655 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27935 2 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29471 1 0.00% 62.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30208-30239 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30431 1 0.00% 62.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33823 5 0.01% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34847 1 0.00% 62.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35136-35167 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37663 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39455 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43136-43167 1 0.00% 62.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45632-45663 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51487 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56832-56863 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58399 1 0.00% 62.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60864-60895 1 0.00% 62.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65567 14763 36.84% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::126336-126367 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130496-130527 1 0.00% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131008-131039 1 0.00% 99.10% # Bytes accessed per row activation system.physmem.bytesPerActivate::131072-131103 346 0.86% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132127 4 0.01% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::161280-161311 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::168384-168415 1 0.00% 99.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::187392-187423 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::161792-161823 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::168960-168991 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::196608-196639 4 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40040 # Bytes accessed per row activation -system.physmem.totQLat 308881805250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 400754322750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467100000 # Total cycles spent in databus access -system.physmem.totBankLat 15405417500 # Total cycles spent in bank access -system.physmem.avgQLat 20197.04 # Average queueing delay per request -system.physmem.avgBankLat 1007.32 # Average bank access latency per request +system.physmem.bytesPerActivate::total 40074 # Bytes accessed per row activation +system.physmem.totQLat 305431681500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 397314004000 # Sum of mem lat for all requests +system.physmem.totBusLat 76467280000 # Total cycles spent in databus access +system.physmem.totBankLat 15415042500 # Total cycles spent in bank access +system.physmem.avgQLat 19971.40 # Average queueing delay per request +system.physmem.avgBankLat 1007.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26204.36 # Average memory access latency -system.physmem.avgRdBW 384.07 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25979.35 # Average memory access latency +system.physmem.avgRdBW 384.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.42 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.41 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.40 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.67 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 1.10 # Average write queue length over time -system.physmem.readRowHits 15267875 # Number of row buffer hits during reads -system.physmem.writeRowHits 798648 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.11 # Average write queue length over time +system.physmem.readRowHits 15267858 # Number of row buffer hits during reads +system.physmem.writeRowHits 798688 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.83 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.22 # Row buffer hit rate for writes -system.physmem.avgGap 158223.12 # Average gap between requests +system.physmem.avgGap 158227.53 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory @@ -384,289 +377,291 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55014580 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16346067 # Transaction distribution -system.membus.trans_dist::ReadResp 16346070 # Transaction distribution +system.membus.throughput 55014417 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16346104 # Transaction distribution +system.membus.trans_dist::ReadResp 16346107 # Transaction distribution system.membus.trans_dist::WriteReq 763348 # Transaction distribution system.membus.trans_dist::WriteResp 763348 # Transaction distribution -system.membus.trans_dist::Writeback 59118 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4682 # Transaction distribution +system.membus.trans_dist::Writeback 59142 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4707 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4684 # Transaction distribution -system.membus.trans_dist::ReadExReq 131411 # Transaction distribution -system.membus.trans_dist::ReadExResp 131411 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4709 # Transaction distribution +system.membus.trans_dist::ReadExReq 131412 # Transaction distribution +system.membus.trans_dist::ReadExResp 131412 # Transaction distribution system.membus.trans_dist::LoadLockedReq 3 # Transaction distribution system.membus.trans_dist::StoreCondReq 3 # Transaction distribution system.membus.trans_dist::StoreCondResp 3 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885920 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4272518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4272668 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382954 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32163398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32163552 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3790 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34550150 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 34550300 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16692492 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16696588 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19090473 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 19094561 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390333 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390325 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 137803020 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 137807116 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7580 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140201001 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140201001 # Total data (bytes) +system.membus.tot_pkt_size::total 140205089 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 140205089 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1492522500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1476111500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 17540815750 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 17555240750 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3583500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3581500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4705924038 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4707147287 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 34177393245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 34172276993 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 64346 # number of replacements -system.l2c.tagsinuse 51424.069961 # Cycle average of tags in use -system.l2c.total_refs 1905385 # Total number of references to valid blocks. -system.l2c.sampled_refs 129735 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.686746 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2511358439500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36974.185132 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 11.366489 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000367 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4621.370879 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3355.179290 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 15.725461 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3578.652286 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2867.590058 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.564181 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000173 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.070517 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.051196 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000240 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.054606 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.043756 # 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average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 61674.135507 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62787.378534 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61810.745390 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10005.201034 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.731529 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.573439 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60817.646245 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64195.633188 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61853.395911 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.303781 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.683527 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56143.257661 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55885.895105 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56022.680137 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56090.553308 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56116.480736 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56102.719595 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84486.111111 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 99434.210526 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61959.893837 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56582.283589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60868.919886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56352.841447 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 56876.555548 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61263.087844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 56464.459493 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95960.526316 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61535.422585 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56668.098479 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 56952.226652 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -861,49 +852,49 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58505331 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2677704 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2677706 # Transaction distribution +system.toL2Bus.throughput 58503668 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2677420 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2677422 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763348 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763348 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 608398 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 10 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2960 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246173 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246173 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 608377 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2971 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2984 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246105 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246105 # Transaction distribution system.toL2Bus.trans_dist::LoadLockedReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondReq 3 # Transaction distribution system.toL2Bus.trans_dist::StoreCondResp 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969441 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798176 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37507 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149666 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7954790 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62986112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85598825 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54648 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 148893553 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148893553 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 203396 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4965063678 # Layer occupancy (ticks) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1969614 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5798105 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 37248 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 149421 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7954388 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 62990656 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 85594465 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 54388 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 253832 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 148893341 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 148893341 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 204156 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4964785971 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4434793437 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4437766959 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4469014832 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4499076262 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23886909 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 23705637 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 86662497 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 86451768 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48461480 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322135 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322135 # Transaction distribution +system.iobus.throughput 48459921 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16322133 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322133 # Transaction distribution system.iobus.trans_dist::WriteReq 8160 # Transaction distribution system.iobus.trans_dist::WriteResp 8160 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -925,11 +916,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382954 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7936 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1030 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -952,9 +943,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660590 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 32660586 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -976,11 +967,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390325 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15872 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2060 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -1003,11 +994,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123500861 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123500861 # Total data (bytes) +system.iobus.tot_pkt_size::total 123500853 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 123500853 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3973000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1053,684 +1044,684 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374798000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 30277632000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) -system.cpu0.branchPred.lookups 7472736 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5963732 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 379354 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4914816 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4037140 # Number of BTB hits +system.iobus.respLayer1.occupancy 41501177007 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu0.branchPred.lookups 7460849 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5960235 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 378283 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4914778 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4045811 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 82.142241 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 698266 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 38240 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 82.319303 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 696591 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 38344 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 25723416 # DTB read hits -system.cpu0.dtb.read_misses 39440 # DTB read misses -system.cpu0.dtb.write_hits 6006462 # DTB write hits -system.cpu0.dtb.write_misses 9528 # DTB write misses +system.cpu0.dtb.read_hits 25704058 # DTB read hits +system.cpu0.dtb.read_misses 39030 # DTB read misses +system.cpu0.dtb.write_hits 5997479 # DTB write hits +system.cpu0.dtb.write_misses 9591 # DTB write misses system.cpu0.dtb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5597 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1333 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 268 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5605 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 680 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25762856 # DTB read accesses -system.cpu0.dtb.write_accesses 6015990 # DTB write accesses +system.cpu0.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25743088 # DTB read accesses +system.cpu0.dtb.write_accesses 6007070 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31729878 # DTB hits -system.cpu0.dtb.misses 48968 # DTB misses -system.cpu0.dtb.accesses 31778846 # DTB accesses -system.cpu0.itb.inst_hits 6261683 # ITB inst hits -system.cpu0.itb.inst_misses 7235 # ITB inst misses +system.cpu0.dtb.hits 31701537 # DTB hits +system.cpu0.dtb.misses 48621 # DTB misses +system.cpu0.dtb.accesses 31750158 # DTB accesses +system.cpu0.itb.inst_hits 6247488 # ITB inst hits +system.cpu0.itb.inst_misses 7199 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 258 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 791 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1762 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1719 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6268918 # ITB inst accesses -system.cpu0.itb.hits 6261683 # DTB hits -system.cpu0.itb.misses 7235 # DTB misses -system.cpu0.itb.accesses 6268918 # DTB accesses -system.cpu0.numCycles 237920120 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6254687 # ITB inst accesses +system.cpu0.itb.hits 6247488 # DTB hits +system.cpu0.itb.misses 7199 # DTB misses +system.cpu0.itb.accesses 6254687 # DTB accesses +system.cpu0.numCycles 237974378 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15748746 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 49352173 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7472736 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4735406 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10833707 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2792544 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 84623 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 47712542 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1287 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1922 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 50902 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1299242 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 340 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6259599 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 422561 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2976 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77655749 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.785029 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.152550 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15699723 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 49234228 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7460849 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4742402 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10819268 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2791638 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 83518 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 47679796 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1230 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1910 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 50382 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1297285 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 371 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6245426 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 421717 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2971 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77555768 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.784584 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.151481 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 66829888 86.06% 86.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 668416 0.86% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 858180 1.11% 88.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1304413 1.68% 89.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1126910 1.45% 91.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 549966 0.71% 91.86% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1380247 1.78% 93.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 376750 0.49% 94.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4560979 5.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 66744115 86.06% 86.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 668305 0.86% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 854486 1.10% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1301033 1.68% 89.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1140084 1.47% 91.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 550475 0.71% 91.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1373308 1.77% 93.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 375655 0.48% 94.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4548307 5.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77655749 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.031409 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.207432 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16823690 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 48684179 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9802416 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 509733 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1833567 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1006000 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91487 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 57560969 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 307020 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1833567 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17765952 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 19652864 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 25831801 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9294758 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3274685 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54590229 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 7255 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 552363 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2204905 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 211 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56896376 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 249980910 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 249932531 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48379 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 39701074 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 17195302 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410578 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 363043 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6638624 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10379903 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6907552 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1064074 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1362159 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50052762 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 969661 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 62837234 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92382 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11367794 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 29332821 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 250599 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77655749 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.809177 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.518047 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77555768 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031351 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.206889 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16771569 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48649935 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9795097 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 503008 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1834030 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1000504 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90828 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 57451762 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 304997 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1834030 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17711945 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 19691518 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 25851696 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9283653 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3180864 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 54475085 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 7298 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 545691 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2120831 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 197 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 56755313 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 249403500 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 249355386 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48114 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 39528436 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 17226877 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410327 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 362870 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6606046 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10343576 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6897280 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1045135 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1291149 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49940914 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 982735 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 62750040 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92397 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11407526 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 29277622 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 263780 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77555768 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.809096 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.520917 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55074638 70.92% 70.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6993608 9.01% 79.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3678555 4.74% 84.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3117743 4.01% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6240678 8.04% 96.72% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1479911 1.91% 98.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 787330 1.01% 99.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 219248 0.28% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 64038 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 55086998 71.03% 71.03% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6938242 8.95% 79.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3598420 4.64% 84.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3124608 4.03% 88.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6233139 8.04% 96.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1485765 1.92% 98.60% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 804564 1.04% 99.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219887 0.28% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 64145 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77655749 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77555768 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 30466 0.70% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4143838 94.53% 95.23% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209138 4.77% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 31748 0.72% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4146155 94.50% 95.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 209698 4.78% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 167413 0.27% 0.27% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29876413 47.55% 47.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48260 0.08% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 15 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 946 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26437550 42.07% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6306621 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 168420 0.27% 0.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29819854 47.52% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48156 0.08% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 937 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26415371 42.10% 89.96% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6297270 10.04% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 62837234 # Type of FU issued -system.cpu0.iq.rate 0.264111 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4383444 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.069759 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 207842642 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 62399132 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43895220 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12180 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6627 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5522 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67046851 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6414 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 320881 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 62750040 # Type of FU issued +system.cpu0.iq.rate 0.263684 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4387604 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.069922 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 207571986 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 62340159 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 43794455 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12289 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6579 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5482 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 66962707 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6517 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 317894 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2431860 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3521 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16133 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 922699 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2428904 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3600 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16156 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 921017 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 16864632 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 486760 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 16878789 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 486624 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1833567 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14994749 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 240124 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51146104 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 107104 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10379903 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6907552 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 682007 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 55746 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3189 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16133 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 183360 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 147814 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 331174 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 61530066 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26055329 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1307168 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1834030 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 15021196 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 239984 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 51041656 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 102587 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10343576 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6897280 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 695313 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 54984 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 10683 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16156 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 184294 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146657 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 330951 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 61443864 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26034265 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1306176 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 123681 # number of nop insts executed -system.cpu0.iew.exec_refs 32305514 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5821167 # Number of branches executed -system.cpu0.iew.exec_stores 6250185 # Number of stores executed -system.cpu0.iew.exec_rate 0.258616 # Inst execution rate -system.cpu0.iew.wb_sent 60920832 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 43900742 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 23943541 # num instructions producing a value -system.cpu0.iew.wb_consumers 43567103 # num instructions consuming a value +system.cpu0.iew.exec_nop 118007 # number of nop insts executed +system.cpu0.iew.exec_refs 32275135 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5809455 # Number of branches executed +system.cpu0.iew.exec_stores 6240870 # Number of stores executed +system.cpu0.iew.exec_rate 0.258195 # Inst execution rate +system.cpu0.iew.wb_sent 60834498 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 43799937 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 23902926 # num instructions producing a value +system.cpu0.iew.wb_consumers 43468500 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184519 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.549578 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184053 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.549891 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11253313 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 719062 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 289317 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75822182 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.520093 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.499421 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11258567 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 718955 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 288860 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75721738 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.518964 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.500316 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61770131 81.47% 81.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6789372 8.95% 90.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2077521 2.74% 93.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1107875 1.46% 94.62% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1001712 1.32% 95.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 557795 0.74% 96.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 684831 0.90% 97.58% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 401810 0.53% 98.11% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1431135 1.89% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61785849 81.60% 81.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6716034 8.87% 90.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2031673 2.68% 93.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1100696 1.45% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 996789 1.32% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 567209 0.75% 96.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 697121 0.92% 97.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 401495 0.53% 98.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1424872 1.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75822182 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 30629038 # Number of instructions committed -system.cpu0.commit.committedOps 39434598 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75721738 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 30484303 # Number of instructions committed +system.cpu0.commit.committedOps 39296836 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13932896 # Number of memory references committed -system.cpu0.commit.loads 7948043 # Number of loads committed -system.cpu0.commit.membars 201908 # Number of memory barriers committed -system.cpu0.commit.branches 4992421 # Number of branches committed -system.cpu0.commit.fp_insts 5469 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 34986832 # Number of committed integer instructions. -system.cpu0.commit.function_calls 490811 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1431135 # number cycles where commit BW limit reached +system.cpu0.commit.refs 13890935 # Number of memory references committed +system.cpu0.commit.loads 7914672 # Number of loads committed +system.cpu0.commit.membars 201566 # Number of memory barriers committed +system.cpu0.commit.branches 4969836 # Number of branches committed +system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 34871152 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489123 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1424872 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124149615 # The number of ROB reads -system.cpu0.rob.rob_writes 103265708 # The number of ROB writes -system.cpu0.timesIdled 892080 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 160264371 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2282472691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 30545540 # Number of Instructions Simulated -system.cpu0.committedOps 39351100 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 30545540 # Number of Instructions Simulated -system.cpu0.cpi 7.789030 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.789030 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.128386 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.128386 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 279175646 # number of integer regfile reads -system.cpu0.int_regfile_writes 45166448 # number of integer regfile writes -system.cpu0.fp_regfile_reads 23007 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19790 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15439802 # number of misc regfile reads -system.cpu0.misc_regfile_writes 404480 # number of misc regfile writes -system.cpu0.icache.replacements 984632 # number of replacements -system.cpu0.icache.tagsinuse 511.564307 # Cycle average of tags in use -system.cpu0.icache.total_refs 10914069 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 985144 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.078653 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6937099000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 153.323923 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 358.240384 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.299461 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.699688 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999149 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5710872 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5203197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 10914069 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5710872 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5203197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 10914069 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5710872 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5203197 # number of overall hits -system.cpu0.icache.overall_hits::total 10914069 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 548607 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 517852 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1066459 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 548607 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 517852 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1066459 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 548607 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 517852 # number of overall misses -system.cpu0.icache.overall_misses::total 1066459 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7528963984 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 7029593986 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14558557970 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7528963984 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 7029593986 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14558557970 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7528963984 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 7029593986 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14558557970 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6259479 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5721049 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 11980528 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6259479 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5721049 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 11980528 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6259479 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5721049 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 11980528 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087644 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090517 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.089016 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087644 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090517 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.089016 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087644 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090517 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.089016 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13723.784028 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13574.523196 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13651.305835 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13651.305835 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13723.784028 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13574.523196 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13651.305835 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 7371 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 409 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.022005 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.rob.rob_reads 123917155 # The number of ROB reads +system.cpu0.rob.rob_writes 103001078 # The number of ROB writes +system.cpu0.timesIdled 891630 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 160418610 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2282332434 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 30404601 # Number of Instructions Simulated +system.cpu0.committedOps 39217134 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 30404601 # Number of Instructions Simulated +system.cpu0.cpi 7.826920 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.826920 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.127764 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.127764 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 278728087 # number of integer regfile reads +system.cpu0.int_regfile_writes 45052561 # number of integer regfile writes +system.cpu0.fp_regfile_reads 23012 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19792 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15437173 # number of misc regfile reads +system.cpu0.misc_regfile_writes 403324 # number of misc regfile writes +system.cpu0.icache.tags.replacements 984712 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.392135 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10916124 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 985224 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 11.079840 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6946570250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 153.798869 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 356.593266 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.300388 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.696471 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.996860 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5698838 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5217286 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10916124 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5698838 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5217286 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 10916124 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5698838 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5217286 # number of overall hits +system.cpu0.icache.overall_hits::total 10916124 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 546469 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 520462 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1066931 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 546469 # 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number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7505000228 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 7078718225 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14583718453 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6245307 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5737748 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11983055 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6245307 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5737748 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11983055 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6245307 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5737748 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11983055 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.087501 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.090708 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.089037 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.087501 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.090708 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.089037 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.087501 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.090708 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.089037 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13733.624831 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13600.835844 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13668.848738 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13733.624831 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13600.835844 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13668.848738 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13733.624831 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13600.835844 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13668.848738 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 8644 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 575 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 416 # 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mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.025666 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13896.184228 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13279.234055 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13573.459198 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43991.095531 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42494.536818 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43275.068377 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12463.001758 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11481.453718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11985.354775 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13400 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26341.010256 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24116.618773 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25216.368057 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 109001574183 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 106248217570 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215249791753 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024652 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028587 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026577 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025073 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.051447 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043646 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047334 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000060 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000052 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025659 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.024826 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026525 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025659 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13865.405311 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13318.627137 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13577.694977 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43750.757830 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42789.411798 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43292.904137 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12465.426541 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11476.628417 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11984.657122 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14642.571429 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12961.384615 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 26299.954755 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24177.701661 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25224.774470 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1745,330 +1736,330 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7176614 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5748558 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 346164 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4712171 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3815419 # Number of BTB hits +system.cpu1.branchPred.lookups 7195832 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5758794 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 347995 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4705708 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3816103 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 80.969451 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 703194 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 35756 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 81.095193 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 703176 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35899 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25652921 # DTB read hits -system.cpu1.dtb.read_misses 36442 # DTB read misses -system.cpu1.dtb.write_hits 5708219 # DTB write hits -system.cpu1.dtb.write_misses 9483 # DTB write misses +system.cpu1.dtb.read_hits 25676963 # DTB read hits +system.cpu1.dtb.read_misses 36626 # DTB read misses +system.cpu1.dtb.write_hits 5717501 # DTB write hits +system.cpu1.dtb.write_misses 9454 # DTB write misses system.cpu1.dtb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5550 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1291 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 249 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1965 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 245 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25689363 # DTB read accesses -system.cpu1.dtb.write_accesses 5717702 # DTB write accesses +system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25713589 # DTB read accesses +system.cpu1.dtb.write_accesses 5726955 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31361140 # DTB hits -system.cpu1.dtb.misses 45925 # DTB misses -system.cpu1.dtb.accesses 31407065 # DTB accesses -system.cpu1.itb.inst_hits 5722854 # ITB inst hits -system.cpu1.itb.inst_misses 6790 # ITB inst misses +system.cpu1.dtb.hits 31394464 # DTB hits +system.cpu1.dtb.misses 46080 # DTB misses +system.cpu1.dtb.accesses 31440544 # DTB accesses +system.cpu1.itb.inst_hits 5739661 # ITB inst hits +system.cpu1.itb.inst_misses 6710 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 255 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 648 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2604 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2611 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1206 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1312 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5729644 # ITB inst accesses -system.cpu1.itb.hits 5722854 # DTB hits -system.cpu1.itb.misses 6790 # DTB misses -system.cpu1.itb.accesses 5729644 # DTB accesses -system.cpu1.numCycles 238719781 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5746371 # ITB inst accesses +system.cpu1.itb.hits 5739661 # DTB hits +system.cpu1.itb.misses 6710 # DTB misses +system.cpu1.itb.accesses 5746371 # DTB accesses +system.cpu1.numCycles 238752144 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 14663434 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 45610232 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7176614 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4518613 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10115214 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2414166 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79241 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 48437095 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1565 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1874 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 41135 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1402245 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 183 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5721051 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 343472 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3001 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 76398004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.741963 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.097795 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 14725732 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 45766952 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7195832 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4519279 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10135681 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2420409 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 79807 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 48403648 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 1533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1933 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42395 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1408034 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5737749 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 344300 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2901 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 76459821 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.743283 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.100006 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 66290194 86.77% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 639384 0.84% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 858446 1.12% 88.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1141205 1.49% 90.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1054322 1.38% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 565766 0.74% 92.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1279029 1.67% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 372986 0.49% 94.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4196672 5.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 66331645 86.75% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 641052 0.84% 87.59% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 862069 1.13% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1143637 1.50% 90.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1042629 1.36% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 566145 0.74% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1286339 1.68% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 374523 0.49% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4211782 5.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 76398004 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030063 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.191062 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15662136 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 49485106 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9174118 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 502006 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1572389 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 964164 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86078 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 53732667 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 284993 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1572389 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16517156 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 19371694 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 27019391 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8745759 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3169437 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51316953 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 13347 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 558580 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2084092 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 533 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53384018 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 234291448 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 234248948 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42500 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 38701877 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14682140 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 422621 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 375998 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6399704 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9755366 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6540913 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 899316 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1131463 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47221133 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1016692 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 61223636 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 83704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9695690 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 24360360 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252773 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 76398004 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.801377 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.509980 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 76459821 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030139 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.191692 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 15725454 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 49459208 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9192415 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 503929 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1576672 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 971007 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 86673 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53874532 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 286668 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1576672 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 16583861 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19404823 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 27005764 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8762969 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3123666 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51462507 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 13354 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 564319 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2029977 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 529 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53559967 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 234998901 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 234956394 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42507 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38873752 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14686214 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 422468 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375757 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6418869 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9803560 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6552959 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 903342 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1157992 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47368560 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1003626 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 61323847 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 88809 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 9695135 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 24547753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 239591 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 76459821 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.802040 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.511450 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54279894 71.05% 71.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6964982 9.12% 80.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3572105 4.68% 84.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2997144 3.92% 88.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6191464 8.10% 96.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1336331 1.75% 98.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 781274 1.02% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 210623 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 64187 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 54334795 71.06% 71.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6963817 9.11% 80.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3541064 4.63% 84.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3011943 3.94% 88.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6202034 8.11% 96.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1339759 1.75% 98.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 792493 1.04% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 211144 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 62772 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 76398004 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 76459821 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28625 0.64% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 3 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.64% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4232850 94.77% 95.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 204916 4.59% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28001 0.63% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.63% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4231917 94.82% 95.44% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 203383 4.56% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 196253 0.32% 0.32% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28636645 46.77% 47.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45275 0.07% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1166 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 13 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.17% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26314487 42.98% 90.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6029771 9.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 195246 0.32% 0.32% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28699765 46.80% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45365 0.07% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1174 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26341683 42.96% 90.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6040595 9.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 61223636 # Type of FU issued -system.cpu1.iq.rate 0.256467 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4466394 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072952 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 203430011 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57942058 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 42278659 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11099 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5883 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4799 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65487820 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5957 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 306320 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 61323847 # Type of FU issued +system.cpu1.iq.rate 0.256852 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4463304 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072783 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 203694277 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58075857 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 42386346 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11257 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5873 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65585843 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6062 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 307143 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2045827 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3210 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14938 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 792022 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2060794 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3248 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14926 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 795522 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17238980 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 391927 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17225652 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 391932 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1572389 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14646185 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 228906 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48337037 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 102627 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9755366 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6540913 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 729665 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50173 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3845 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14938 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 169845 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 132330 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 302175 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 60177661 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 26008514 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1045975 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1576672 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14666749 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48476685 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98660 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9803560 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6552959 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 716609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 50437 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 9701 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14926 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 170356 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133051 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 303407 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 60276255 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 26034557 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1047592 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 99212 # number of nop insts executed -system.cpu1.iew.exec_refs 31985233 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5705434 # Number of branches executed -system.cpu1.iew.exec_stores 5976719 # Number of stores executed -system.cpu1.iew.exec_rate 0.252085 # Inst execution rate -system.cpu1.iew.wb_sent 59667880 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 42283458 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23216135 # num instructions producing a value -system.cpu1.iew.wb_consumers 42895102 # num instructions consuming a value +system.cpu1.iew.exec_nop 104499 # number of nop insts executed +system.cpu1.iew.exec_refs 32021114 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5717498 # Number of branches executed +system.cpu1.iew.exec_stores 5986557 # Number of stores executed +system.cpu1.iew.exec_rate 0.252464 # Inst execution rate +system.cpu1.iew.wb_sent 59765334 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 42391160 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23307297 # num instructions producing a value +system.cpu1.iew.wb_consumers 43055480 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.177126 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.541230 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177553 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.541332 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 9567940 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763919 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 261423 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 74825615 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.512228 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.487191 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 9596314 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 764035 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 262671 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 74883149 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.513666 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.490214 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 61056295 81.60% 81.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6800068 9.09% 90.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1929591 2.58% 93.26% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1057405 1.41% 94.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1013455 1.35% 96.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 520209 0.70% 96.73% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 685711 0.92% 97.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 375889 0.50% 98.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1386992 1.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61098286 81.59% 81.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6805438 9.09% 90.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1903916 2.54% 93.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1064936 1.42% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1018174 1.36% 96.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 531111 0.71% 96.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 691593 0.92% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 378534 0.51% 98.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1391161 1.86% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 74825615 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29838157 # Number of instructions committed -system.cpu1.commit.committedOps 38327755 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 74883149 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29982419 # Number of instructions committed +system.cpu1.commit.committedOps 38464913 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13458430 # Number of memory references committed -system.cpu1.commit.loads 7709539 # Number of loads committed -system.cpu1.commit.membars 201879 # Number of memory barriers committed -system.cpu1.commit.branches 4970440 # Number of branches committed -system.cpu1.commit.fp_insts 4743 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33879408 # Number of committed integer instructions. -system.cpu1.commit.function_calls 500692 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1386992 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13500203 # Number of memory references committed +system.cpu1.commit.loads 7742766 # Number of loads committed +system.cpu1.commit.membars 202217 # Number of memory barriers committed +system.cpu1.commit.branches 4992962 # Number of branches committed +system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33994528 # Number of committed integer instructions. +system.cpu1.commit.function_calls 502375 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1391161 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 120414089 # The number of ROB reads -system.cpu1.rob.rob_writes 97409741 # The number of ROB writes -system.cpu1.timesIdled 885352 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 162321777 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2286481516 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29771274 # Number of Instructions Simulated -system.cpu1.committedOps 38260872 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29771274 # Number of Instructions Simulated -system.cpu1.cpi 8.018460 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.018460 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124712 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124712 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 271859015 # number of integer regfile reads -system.cpu1.int_regfile_writes 43450852 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22226 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19958 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14811721 # number of misc regfile reads -system.cpu1.misc_regfile_writes 428358 # number of misc regfile writes -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.rob.rob_reads 120638730 # The number of ROB reads +system.cpu1.rob.rob_writes 97745041 # The number of ROB writes +system.cpu1.timesIdled 886317 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 162292323 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2286407630 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29911740 # Number of Instructions Simulated +system.cpu1.committedOps 38394234 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29911740 # Number of Instructions Simulated +system.cpu1.cpi 7.981888 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.981888 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.125284 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.125284 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 272364887 # number of integer regfile reads +system.cpu1.int_regfile_writes 43577017 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22187 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19914 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14848508 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429527 # number of misc regfile writes +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2077,17 +2068,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1456504103755 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1456504103755 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1456504103755 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1453044953007 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1453044953007 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1453044953007 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83064 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83067 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index fb76d8786..96aff7e7e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,142 +1,142 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.627154 # Number of seconds simulated -sim_ticks 2627154206500 # Number of ticks simulated -final_tick 2627154206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.630645 # Number of seconds simulated +sim_ticks 2630645085500 # Number of ticks simulated +final_tick 2630645085500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 361221 # Simulator instruction rate (inst/s) -host_op_rate 459651 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15759970234 # Simulator tick rate (ticks/s) -host_mem_usage 398468 # Number of bytes of host memory used -host_seconds 166.70 # Real time elapsed on the host -sim_insts 60214798 # Number of instructions simulated -sim_ops 76622863 # Number of ops (including micro ops) simulated +host_inst_rate 281405 # Simulator instruction rate (inst/s) +host_op_rate 358084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12294669184 # Simulator tick rate (ticks/s) +host_mem_usage 398476 # Number of bytes of host memory used +host_seconds 213.97 # Real time elapsed on the host +sim_insts 60211229 # Number of instructions simulated +sim_ops 76617937 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 292384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4914704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 305952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4748752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 411968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4151472 # Number of bytes read from this memory -system.physmem.bytes_read::total 134026976 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 292384 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 411968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704352 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3695296 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1534856 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1481296 # Number of bytes written to this memory -system.physmem.bytes_written::total 6711448 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 398080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4312560 # Number of bytes read from this memory +system.physmem.bytes_read::total 134021792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 305952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 398080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3690176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1535008 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1481144 # Number of bytes written to this memory +system.physmem.bytes_written::total 6706328 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 76826 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10983 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74233 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6437 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 64893 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690962 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57739 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 383714 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 370324 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811777 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47296902 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 67410 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57659 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 383752 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 370286 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811697 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47234139 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 111293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1870733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 116303 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1805166 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 156812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1580216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51016029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 111293 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 156812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268105 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1406578 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 584228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2554646 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1406578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47296902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 151324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1639355 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50946360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 116303 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 151324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267627 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1402765 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 583510 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563035 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2549309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1402765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47234139 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 111293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2454961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 116303 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2388676 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 156812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2144057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53570675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690962 # Total number of read requests seen -system.physmem.writeReqs 811777 # Total number of write requests seen -system.physmem.cpureqs 214505 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 1004221568 # Total number of bytes read from memory -system.physmem.bytesWritten 51953728 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 134026976 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6711448 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 151324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2202389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53495669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690881 # Total number of read requests seen +system.physmem.writeReqs 811697 # Total number of write requests seen +system.physmem.cpureqs 214350 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 1004216384 # Total number of bytes read from memory +system.physmem.bytesWritten 51948608 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 134021792 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6706328 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 26 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 980549 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 980310 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 980142 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 980447 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 986846 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 980559 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 980589 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 980289 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 980613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 980424 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 979732 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 979654 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 980193 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 980214 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 980246 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 980129 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49310 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49129 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51113 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51073 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51327 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51427 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51168 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51208 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51034 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50441 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 50412 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 50841 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50704 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50889 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 50829 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 4522 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 980391 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 980205 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 980221 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 980428 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 986950 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 980709 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 980611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 980417 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 980615 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 980431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 979815 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 979554 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 980154 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 980076 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 980169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 980109 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 49158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 49026 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50948 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51094 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51158 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51463 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51449 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51194 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51021 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50517 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 50336 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 50808 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50591 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50830 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 50810 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2627149788000 # Total gap between requests +system.physmem.totGap 2630640666000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6680 # Categorize read packet sizes system.physmem.readPktSize::3 15532032 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152250 # Categorize read packet sizes +system.physmem.readPktSize::6 152169 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754038 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 57739 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1134037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 977508 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1022657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3835405 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2876027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2874808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2829459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 16845 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 28680 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 2442 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 2410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 32 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57659 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1131442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 973737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1003950 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3836084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2879069 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2878494 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2847936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 16166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 29952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 44268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 29895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1064 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -152,30 +152,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35397 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35250 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35428 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -184,224 +184,196 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38107 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 27715.971974 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 2557.155392 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 33302.761922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-127 5424 14.23% 14.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-191 3316 8.70% 22.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-255 2198 5.77% 28.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-319 1686 4.42% 33.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-383 1157 3.04% 36.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-447 1029 2.70% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-511 812 2.13% 41.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-575 726 1.91% 42.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-639 578 1.52% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-703 463 1.21% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-767 465 1.22% 46.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-831 413 1.08% 47.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-895 261 0.68% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-959 269 0.71% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-1023 229 0.60% 49.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1087 239 0.63% 50.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1215 136 0.36% 51.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1279 99 0.26% 51.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1343 99 0.26% 51.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1407 86 0.23% 52.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1535 761 2.00% 54.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1599 211 0.55% 54.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1663 139 0.36% 55.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1727 123 0.32% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1791 64 0.17% 55.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1855 78 0.20% 56.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1919 56 0.15% 56.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1983 58 0.15% 56.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2047 48 0.13% 56.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2111 69 0.18% 56.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2175 34 0.09% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2239 27 0.07% 56.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2303 25 0.07% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2367 25 0.07% 56.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2431 9 0.02% 56.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2495 23 0.06% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2559 23 0.06% 57.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2623 14 0.04% 57.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2687 10 0.03% 57.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2879 8 0.02% 57.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2943 10 0.03% 57.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-3007 9 0.02% 57.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3199 5 0.01% 57.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3263 6 0.02% 57.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3455 4 0.01% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3519 8 0.02% 57.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3583 4 0.01% 57.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3647 7 0.02% 57.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3775 11 0.03% 57.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3839 9 0.02% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3903 3 0.01% 57.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-4031 10 0.03% 57.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4095 5 0.01% 57.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4159 35 0.09% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4287 2 0.01% 57.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4351 6 0.02% 57.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4415 4 0.01% 57.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4543 4 0.01% 57.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4735 2 0.01% 57.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4863 5 0.01% 57.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4927 3 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4991 1 0.00% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5119 3 0.01% 57.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5311 5 0.01% 57.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5375 2 0.01% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5439 4 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5503 2 0.01% 57.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5567 4 0.01% 57.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5631 2 0.01% 57.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5695 3 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5759 2 0.01% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5887 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6079 1 0.00% 57.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6207 23 0.06% 57.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6271 4 0.01% 58.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6335 3 0.01% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6591 2 0.01% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6847 18 0.05% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7231 5 0.01% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7295 1 0.00% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7423 3 0.01% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7487 4 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7807 6 0.02% 58.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7999 2 0.01% 58.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8063 3 0.01% 58.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8191 5 0.01% 58.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8255 310 0.81% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9408-9471 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9855 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10303 17 0.04% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11327 2 0.01% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12095 2 0.01% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12351 1 0.00% 59.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13375 2 0.01% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14143 1 0.00% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14911 1 0.00% 59.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17471 2 0.01% 59.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18751 2 0.01% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19775 1 0.00% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-20031 1 0.00% 59.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20799 1 0.00% 59.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21567 3 0.01% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22847 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24639 3 0.01% 59.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24895 1 0.00% 59.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25663 1 0.00% 59.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25920-25983 1 0.00% 59.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26687 1 0.00% 59.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27455 2 0.01% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28479 1 0.00% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28735 3 0.01% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28991 1 0.00% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29952-30015 1 0.00% 59.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30271 1 0.00% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31103 2 0.01% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32063 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32575 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33087 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33472-33535 2 0.01% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33599 19 0.05% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35391 1 0.00% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36927 2 0.01% 59.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38207 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-41023 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-42047 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43071 1 0.00% 59.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44095 2 0.01% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48191 1 0.00% 59.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48447 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49215 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::50688-50751 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51456-51519 1 0.00% 59.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52480-52543 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54272-54335 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56128-56191 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58687 1 0.00% 59.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60032-60095 1 0.00% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60672-60735 1 0.00% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63551 1 0.00% 59.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65599 15122 39.68% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::71808-71871 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::82176-82239 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::88064-88127 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::99712-99775 1 0.00% 99.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129856-129919 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131135 356 0.93% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 37996 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 27796.675861 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 2568.021256 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 33333.179984 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-127 5396 14.20% 14.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-191 3321 8.74% 22.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-255 2191 5.77% 28.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-319 1656 4.36% 33.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-383 1158 3.05% 36.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-447 1048 2.76% 38.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-511 789 2.08% 40.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-575 726 1.91% 42.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-639 577 1.52% 44.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-703 474 1.25% 45.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-767 440 1.16% 46.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-831 388 1.02% 47.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-895 251 0.66% 48.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-959 273 0.72% 49.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-1023 221 0.58% 49.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1087 258 0.68% 50.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1151 159 0.42% 50.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1215 126 0.33% 51.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1279 108 0.28% 51.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1343 95 0.25% 51.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1407 80 0.21% 51.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1471 156 0.41% 52.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1535 779 2.05% 54.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1599 205 0.54% 54.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1663 146 0.38% 55.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1727 108 0.28% 55.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1791 84 0.22% 55.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1855 80 0.21% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1919 53 0.14% 56.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1983 48 0.13% 56.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-2047 45 0.12% 56.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2111 58 0.15% 56.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2175 47 0.12% 56.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2239 19 0.05% 56.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2303 26 0.07% 56.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2367 22 0.06% 56.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2431 18 0.05% 56.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2495 19 0.05% 56.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2559 19 0.05% 57.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2687 11 0.03% 57.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2751 13 0.03% 57.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2815 9 0.02% 57.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2879 7 0.02% 57.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-3007 10 0.03% 57.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3135 16 0.04% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3199 3 0.01% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3263 9 0.02% 57.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3327 9 0.02% 57.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3391 4 0.01% 57.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3519 5 0.01% 57.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3583 5 0.01% 57.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3647 15 0.04% 57.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3711 11 0.03% 57.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3775 13 0.03% 57.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3839 8 0.02% 57.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4159 34 0.09% 57.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4223 3 0.01% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4287 1 0.00% 57.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4351 1 0.00% 57.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4415 7 0.02% 57.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4479 6 0.02% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4543 5 0.01% 57.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4607 3 0.01% 57.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4671 6 0.02% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4735 1 0.00% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4799 1 0.00% 57.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4863 4 0.01% 57.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4927 2 0.01% 57.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4991 3 0.01% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5055 2 0.01% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5183 7 0.02% 57.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5311 6 0.02% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5375 3 0.01% 57.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5439 2 0.01% 57.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5503 4 0.01% 57.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5567 2 0.01% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5631 1 0.00% 57.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5695 5 0.01% 57.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5951 2 0.01% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6143 1 0.00% 57.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6207 18 0.05% 57.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6271 4 0.01% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6335 4 0.01% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6399 1 0.00% 57.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6527 3 0.01% 57.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6591 3 0.01% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6655 1 0.00% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6719 1 0.00% 57.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6783 2 0.01% 57.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6847 17 0.04% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6911 1 0.00% 58.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-7039 1 0.00% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7488-7551 5 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7743 7 0.02% 58.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7807 3 0.01% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7999 6 0.02% 58.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8063 2 0.01% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8127 9 0.02% 58.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8191 4 0.01% 58.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8255 308 0.81% 58.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8767 1 0.00% 58.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9279 1 0.00% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11071 2 0.01% 59.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13375 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14655 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17727 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18944-19007 1 0.00% 59.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19519 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21248-21311 2 0.01% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21823 1 0.00% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22079 1 0.00% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23615 1 0.00% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25151 1 0.00% 59.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26175 1 0.00% 59.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27711 2 0.01% 59.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28735 2 0.01% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30527 1 0.00% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30783 1 0.00% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-31039 1 0.00% 59.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31807 2 0.01% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32831 2 0.01% 59.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33087 3 0.01% 59.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33343 15 0.04% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41152-41215 1 0.00% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46143 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47423 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52224-52287 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::55872-55935 1 0.00% 59.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::56320-56383 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::57984-58047 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58240-58303 1 0.00% 59.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65599 15141 39.85% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72832-72895 1 0.00% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::80704-80767 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::86848-86911 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::101184-101247 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::129728-129791 1 0.00% 99.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::130112-130175 1 0.00% 99.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::131072-131135 356 0.94% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.99% # Bytes accessed per row activation system.physmem.bytesPerActivate::136576-136639 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38107 # Bytes accessed per row activation -system.physmem.totQLat 304254816750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 398977768000 # Sum of mem lat for all requests -system.physmem.totBusLat 78454680000 # Total cycles spent in databus access -system.physmem.totBankLat 16268271250 # Total cycles spent in bank access -system.physmem.avgQLat 19390.48 # Average queueing delay per request -system.physmem.avgBankLat 1036.79 # Average bank access latency per request +system.physmem.bytesPerActivate::total 37996 # Bytes accessed per row activation +system.physmem.totQLat 300645538000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 395312713000 # Sum of mem lat for all requests +system.physmem.totBusLat 78454275000 # Total cycles spent in databus access +system.physmem.totBankLat 16212900000 # Total cycles spent in bank access +system.physmem.avgQLat 19160.56 # Average queueing delay per request +system.physmem.avgBankLat 1033.27 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25427.28 # Average memory access latency -system.physmem.avgRdBW 382.25 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 19.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.02 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 25193.83 # Average memory access latency +system.physmem.avgRdBW 381.74 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 19.75 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.95 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.55 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 1.26 # Average write queue length over time -system.physmem.readRowHits 15666209 # Number of row buffer hits during reads -system.physmem.writeRowHits 798397 # Number of row buffer hits during writes +system.physmem.readRowHits 15666172 # Number of row buffer hits during reads +system.physmem.writeRowHits 798379 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 98.35 # Row buffer hit rate for writes -system.physmem.avgGap 159194.77 # Average gap between requests +system.physmem.writeRowHitRate 98.36 # Row buffer hit rate for writes +system.physmem.avgGap 159407.86 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -414,259 +386,259 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54483503 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743616 # Transaction distribution -system.membus.trans_dist::ReadResp 16743616 # Transaction distribution +system.membus.throughput 54407285 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16743607 # Transaction distribution +system.membus.trans_dist::ReadResp 16743607 # Transaction distribution system.membus.trans_dist::WriteReq 763392 # Transaction distribution system.membus.trans_dist::WriteResp 763392 # Transaction distribution -system.membus.trans_dist::Writeback 57739 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution -system.membus.trans_dist::ReadExReq 131423 # Transaction distribution -system.membus.trans_dist::ReadExResp 131423 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57659 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution +system.membus.trans_dist::ReadExReq 131350 # Transaction distribution +system.membus.trans_dist::ReadExResp 131350 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892707 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1892477 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4279569 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4279337 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 32956771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::system.physmem.port 32956541 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35343633 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35343401 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16482168 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16471864 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18880309 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 18870001 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2390397 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 140738424 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::system.physmem.port 140728120 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143136565 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143136565 # Total data (bytes) +system.membus.tot_pkt_size::total 143126257 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 143126257 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225633000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1209137000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 18165198500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 18109692000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) -system.membus.reqLayer3.occupancy 3755000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 3744500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4987617364 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4946454076 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 35065696500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 35060518750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.replacements 62136 # number of replacements -system.l2c.tagsinuse 51567.664706 # Cycle average of tags in use -system.l2c.total_refs 1698783 # Total number of references to valid blocks. -system.l2c.sampled_refs 127519 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.321803 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2572304327500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 38171.110682 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000688 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 2904.028598 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3024.624697 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4116.712903 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3351.186952 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.582445 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.044312 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.046152 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.062816 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.051135 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786860 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9922 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 419412 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 179877 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9880 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3503 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 425184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 190638 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242011 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596576 # number of Writeback hits -system.l2c.Writeback_hits::total 596576 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits +system.l2c.tags.replacements 62055 # number of replacements +system.l2c.tags.tagsinuse 51615.482729 # Cycle average of tags in use +system.l2c.tags.total_refs 1699189 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127440 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.333247 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2575816655500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38219.751550 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000690 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2839.791296 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3005.850612 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000186 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4181.982232 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3368.106163 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.583187 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.043332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045866 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.063812 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.051393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.787590 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 10006 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3588 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 435821 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 185768 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 9923 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3635 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 408641 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 184604 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1241986 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596408 # number of Writeback hits +system.l2c.Writeback_hits::total 596408 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 9 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56638 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 57846 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114484 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9922 # 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mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537517 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.246971 # mshr miss rate for demand accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.537822 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.536759 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537316 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009921 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.234025 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.209163 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.101885 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009810 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.246971 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221749 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.101840 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000557 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009921 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.234025 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000101 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014914 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.209163 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.101885 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221749 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.101840 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 56466.938661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 56750.373622 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59423.740053 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 57644.968070 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59647.405660 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 57613.045775 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001.669792 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.347102 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51707.260344 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51272.568687 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 51508.568707 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10003.791347 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.388407 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 51513.275389 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51551.540309 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 51531.484394 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 52034.369344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 51886.775707 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 52130.681758 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 52354.656011 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56218.652226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 52034.369344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 57139.226013 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 51886.775707 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58186.810626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51880.433734 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 52339.077136 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57093.207395 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 52130.681758 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 52354.656011 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -814,45 +786,45 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52848676 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471696 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471696 # Transaction distribution +system.toL2Bus.throughput 52767546 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2471907 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471907 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763392 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763392 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596576 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 596408 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2907 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2907 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247542 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247542 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1725238 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5754024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 19969 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50318 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 7549549 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54758516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83805889 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79212 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 138672017 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138672017 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 169604 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4809056500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadExReq 247510 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247510 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 1724962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 5753498 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 20327 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 50707 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count 7549494 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 54749620 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 83783741 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 28900 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 79720 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size 138641981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 138641981 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 170704 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4808390000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3862257000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3865864500 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4394586000 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4428402674 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12869000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13102500 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30515000 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30777250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48206783 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715360 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715360 # Transaction distribution +system.iobus.throughput 48142811 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 16715359 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715359 # Transaction distribution system.iobus.trans_dist::WriteReq 8167 # Transaction distribution system.iobus.trans_dist::WriteResp 8167 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -874,11 +846,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382990 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -901,9 +873,9 @@ system.iobus.pkt_count::system.realview.aaci_fake.pio 16 system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33447052 # Packet count per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -925,11 +897,11 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -952,11 +924,11 @@ system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646653 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646653 # Total data (bytes) +system.iobus.tot_pkt_size::total 126646649 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 126646649 # Total data (bytes) system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1002,141 +974,141 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374823000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374821000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 31064064000 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.2 # Layer utilization (%) +system.iobus.respLayer1.occupancy 42579543250 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7331530 # DTB read hits -system.cpu0.dtb.read_misses 6749 # DTB read misses -system.cpu0.dtb.write_hits 5629181 # DTB write hits -system.cpu0.dtb.write_misses 1838 # DTB write misses -system.cpu0.dtb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 7541054 # DTB read hits +system.cpu0.dtb.read_misses 7077 # DTB read misses +system.cpu0.dtb.write_hits 5712165 # DTB write hits +system.cpu0.dtb.write_misses 1789 # DTB write misses +system.cpu0.dtb.flush_tlb 1248 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6355 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 735 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 146 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 224 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7338279 # DTB read accesses -system.cpu0.dtb.write_accesses 5631019 # DTB write accesses +system.cpu0.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7548131 # DTB read accesses +system.cpu0.dtb.write_accesses 5713954 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12960711 # DTB hits -system.cpu0.dtb.misses 8587 # DTB misses -system.cpu0.dtb.accesses 12969298 # DTB accesses -system.cpu0.itb.inst_hits 29905877 # ITB inst hits -system.cpu0.itb.inst_misses 3541 # ITB inst misses +system.cpu0.dtb.hits 13253219 # DTB hits +system.cpu0.dtb.misses 8866 # DTB misses +system.cpu0.dtb.accesses 13262085 # DTB accesses +system.cpu0.itb.inst_hits 30586267 # ITB inst hits +system.cpu0.itb.inst_misses 3713 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1248 # 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number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3901744 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33819709 # number of integer instructions -system.cpu0.num_fp_insts 4399 # number of float instructions -system.cpu0.num_int_register_reads 193860060 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36222671 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 2980 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1422 # number of times the floating registers were written -system.cpu0.num_mem_refs 13528220 # number of memory refs -system.cpu0.num_load_insts 7652095 # Number of load instructions -system.cpu0.num_store_insts 5876125 # Number of store instructions -system.cpu0.num_idle_cycles 3959269974.685009 # Number of idle cycles -system.cpu0.num_busy_cycles -1333655320.685009 # Number of busy cycles -system.cpu0.not_idle_fraction -0.507940 # Percentage of non-idle cycles -system.cpu0.idle_fraction 1.507940 # Percentage of idle cycles +system.cpu0.committedInsts 29984771 # Number of instructions committed +system.cpu0.committedOps 38337194 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34488518 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5157 # Number of float alu accesses +system.cpu0.num_func_calls 1080132 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3980914 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34488518 # number of integer instructions +system.cpu0.num_fp_insts 5157 # number of float instructions +system.cpu0.num_int_register_reads 197896297 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36953400 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3554 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1606 # number of times the floating registers were written +system.cpu0.num_mem_refs 13834370 # number of memory refs +system.cpu0.num_load_insts 7870253 # Number of load instructions +system.cpu0.num_store_insts 5964117 # Number of store instructions +system.cpu0.num_idle_cycles -1415422.936618 # Number of idle cycles +system.cpu0.num_busy_cycles 2630849391.936618 # Number of busy cycles +system.cpu0.not_idle_fraction 1.000538 # Percentage of non-idle cycles +system.cpu0.idle_fraction -0.000538 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83030 # number of quiesce instructions executed -system.cpu0.icache.replacements 856296 # number of replacements -system.cpu0.icache.tagsinuse 510.881527 # Cycle average of tags in use -system.cpu0.icache.total_refs 60652091 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 856808 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 70.788428 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13926.334992 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13764.720918 # average overall miss latency +system.cpu0.kern.inst.quiesce 83028 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 856159 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.881074 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60648644 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856671 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.795724 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19966906250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 210.109344 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 300.771730 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.410370 # 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number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1145,158 +1117,158 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 424296 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 432512 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 856808 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 424296 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 432512 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 856808 # 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average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11599.977374 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11926.334992 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11764.720918 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 440996 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 415675 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 856671 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 440996 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 415675 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 856671 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 440996 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 415675 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 856671 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5122351500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 4953145250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10075496750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5122351500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 4953145250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10075496750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5122351500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 4953145250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10075496750 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 430705250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 430705250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014418 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013444 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013928 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014418 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.013444 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013928 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014418 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.013444 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013928 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11615.414879 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.908462 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11761.220760 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11615.414879 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.908462 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11761.220760 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11615.414879 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.908462 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11761.220760 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 627777 # number of replacements -system.cpu0.dcache.tagsinuse 511.879644 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23662359 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 628289 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.661584 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 650252000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 250.372579 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 261.507065 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.489009 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.510756 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.999765 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6433193 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6766702 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13199895 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4991648 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 4983805 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9975453 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117595 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 118707 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123506 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 124296 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247802 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11424841 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 11750507 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 23175348 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11424841 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 11750507 # number of overall hits -system.cpu0.dcache.overall_hits::total 23175348 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 179297 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 189949 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 369246 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 130279 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 120170 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 250449 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 5911 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 5590 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11501 # number of LoadLockedReq misses -system.cpu0.dcache.demand_misses::cpu0.data 309576 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 310119 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 619695 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 309576 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 310119 # number of overall misses -system.cpu0.dcache.overall_misses::total 619695 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2654380500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2776699500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5431080000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5632662000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 4856154500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10488816500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 79686500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 80814000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 160500500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8287042500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 7632854000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 15919896500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8287042500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 7632854000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 15919896500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6612490 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6956651 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13569141 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5121927 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5103975 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10225902 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123506 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124297 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 247803 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123506 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 124296 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247802 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11734417 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12060626 # 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miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044973 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046412 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026382 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025713 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026043 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026382 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025713 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026043 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14804.377653 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14618.131709 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14708.568272 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43235.379455 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40410.705667 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41880.049431 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13481.052275 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14456.887299 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13955.351709 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25689.890188 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26769.008256 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24612.661591 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 25689.890188 # average overall miss latency +system.cpu0.dcache.tags.replacements 627599 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.878483 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 23660456 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 628111 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 37.669227 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 657290250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 182.795545 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 329.082938 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.357023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.642740 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999763 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6630954 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6567853 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13198807 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5069666 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 4905119 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9974785 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 121275 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 114924 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 236199 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127469 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 120289 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247758 # 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number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15987337522 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6815882 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 6751966 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13567848 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5200737 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 5024465 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225202 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 127468 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 120291 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 247759 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127469 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 120289 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247758 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12016619 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 11776431 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 23793050 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12016619 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 11776431 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 23793050 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027132 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.027268 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027200 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025202 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.023753 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.024490 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048585 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044617 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.046658 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026297 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025768 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026297 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.025768 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14791.301209 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14686.291843 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14738.912479 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42146.342890 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42095.346413 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42122.038528 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13350.314872 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14396.031302 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13835.813149 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26137.706319 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25465.873357 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25808.589964 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26137.706319 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 25465.873357 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 25808.589964 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1305,77 +1277,77 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 596576 # number of writebacks -system.cpu0.dcache.writebacks::total 596576 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 179297 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 189949 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369246 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130279 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 120170 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 250449 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 5911 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5590 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11501 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 309576 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 310119 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 619695 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 309576 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 310119 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 619695 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2295786500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2396801500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4692588000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5372104000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4615814500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9987918500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67864500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69634000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 137498500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7667890500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7012616000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 14680506500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7667890500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7012616000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14680506500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91527278500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90544684500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182071963000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13203337000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13032051000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235388000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104730615500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103576735500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208307351000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027115 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027305 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027212 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023544 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.047860 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044973 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046412 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.026043 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026382 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025713 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026043 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12804.377653 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12618.131709 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12708.568272 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41235.379455 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38410.705667 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39880.049431 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11481.052275 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12456.887299 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11955.351709 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.008256 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.661591 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23689.890188 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 596408 # number of writebacks +system.cpu0.dcache.writebacks::total 596408 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184928 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 184113 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 369041 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131071 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 119346 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 250417 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5367 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 11560 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 315999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 303459 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 619458 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 315999 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 303459 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619458 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2362872250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2333419750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4696292000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5228333691 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4754653787 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9982987478 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70279500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 66466500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136746000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7591205941 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7088073537 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14679279478 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7591205941 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7088073537 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14679279478 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91858515750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90196579000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182055094750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13241304408 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 12994136940 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26235441348 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 105099820158 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103190715940 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208290536098 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.027132 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.027268 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.027200 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025202 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.023753 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048585 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044617 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046658 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026297 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025768 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12777.255202 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12673.845682 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.664628 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39889.324801 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39839.238743 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39865.454334 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11348.215727 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12384.292901 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11829.238754 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24022.879633 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23357.598677 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23696.972963 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1388,76 +1360,76 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7669515 # DTB read hits -system.cpu1.dtb.read_misses 7262 # DTB read misses -system.cpu1.dtb.write_hits 5604176 # DTB write hits -system.cpu1.dtb.write_misses 1826 # DTB write misses -system.cpu1.dtb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 7458653 # DTB read hits +system.cpu1.dtb.read_misses 7094 # DTB read misses +system.cpu1.dtb.write_hits 5520448 # DTB write hits +system.cpu1.dtb.write_misses 1859 # DTB write misses +system.cpu1.dtb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6595 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6666 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 144 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 134 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 228 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7676777 # DTB read accesses -system.cpu1.dtb.write_accesses 5606002 # DTB write accesses +system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7465747 # DTB read accesses +system.cpu1.dtb.write_accesses 5522307 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13273691 # DTB hits -system.cpu1.dtb.misses 9088 # DTB misses -system.cpu1.dtb.accesses 13282779 # DTB accesses -system.cpu1.itb.inst_hits 31603022 # ITB inst hits -system.cpu1.itb.inst_misses 3724 # ITB inst misses +system.cpu1.dtb.hits 12979101 # DTB hits +system.cpu1.dtb.misses 8953 # DTB misses +system.cpu1.dtb.accesses 12988054 # DTB accesses +system.cpu1.itb.inst_hits 30919048 # ITB inst hits +system.cpu1.itb.inst_misses 3673 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1246 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1247 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 704 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 2817 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 31606746 # ITB inst accesses -system.cpu1.itb.hits 31603022 # DTB hits -system.cpu1.itb.misses 3724 # DTB misses -system.cpu1.itb.accesses 31606746 # DTB accesses -system.cpu1.numCycles 2628693759 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 30922721 # ITB inst accesses +system.cpu1.itb.hits 30919048 # DTB hits +system.cpu1.itb.misses 3673 # DTB misses +system.cpu1.itb.accesses 30922721 # DTB accesses +system.cpu1.numCycles 2631856202 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30860361 # Number of instructions committed -system.cpu1.committedOps 39028594 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 35068610 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5870 # Number of float alu accesses -system.cpu1.num_func_calls 1089512 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4048013 # number of instructions that are conditional controls -system.cpu1.num_int_insts 35068610 # number of integer instructions -system.cpu1.num_fp_insts 5870 # number of float instructions -system.cpu1.num_int_register_reads 201015882 # number of times the integer registers were read -system.cpu1.num_int_register_writes 37978161 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4513 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1358 # number of times the floating registers were written -system.cpu1.num_mem_refs 13873832 # number of memory refs -system.cpu1.num_load_insts 8013211 # Number of load instructions -system.cpu1.num_store_insts 5860621 # Number of store instructions -system.cpu1.num_idle_cycles 952679619.816103 # Number of idle cycles -system.cpu1.num_busy_cycles 1676014139.183897 # Number of busy cycles -system.cpu1.not_idle_fraction 0.637584 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.362416 # Percentage of idle cycles +system.cpu1.committedInsts 30226458 # Number of instructions committed +system.cpu1.committedOps 38280743 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 34395206 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5112 # Number of float alu accesses +system.cpu1.num_func_calls 1060216 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3968456 # number of instructions that are conditional controls +system.cpu1.num_int_insts 34395206 # number of integer instructions +system.cpu1.num_fp_insts 5112 # number of float instructions +system.cpu1.num_int_register_reads 196952140 # number of times the integer registers were read +system.cpu1.num_int_register_writes 37242776 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3939 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1174 # number of times the floating registers were written +system.cpu1.num_mem_refs 13565505 # number of memory refs +system.cpu1.num_load_insts 7793640 # Number of load instructions +system.cpu1.num_store_insts 5771865 # Number of store instructions +system.cpu1.num_idle_cycles 4920851591.451757 # Number of idle cycles +system.cpu1.num_busy_cycles -2288995389.451757 # Number of busy cycles +system.cpu1.not_idle_fraction -0.869727 # Percentage of non-idle cycles +system.cpu1.idle_fraction 1.869727 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1466,10 +1438,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1482619780500 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1482619780500 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1482619780500 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1478947388250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1478947388250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1478947388250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |