diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-27 16:08:05 -0400 |
| commit | b1a58933e07d7af0eb5f43942f8ad9bc93f28039 (patch) | |
| tree | 21f36b849ba0aed06ec18ed45aef46feeacd7532 /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | 630068be6f7b6dc5c612867c764c37e41fd90a4a (diff) | |
| download | gem5-b1a58933e07d7af0eb5f43942f8ad9bc93f28039.tar.xz | |
stats: update stats for icache change not allowing dirty data
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
11 files changed, 2154 insertions, 3164 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 7eac6f043..35fda0d55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -168,7 +168,7 @@ type=O3Checker children=dtb itb tracer checker=Null clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false do_checkpoint_insts=true do_quiesce=true @@ -640,7 +640,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 3620c0fb4..8990e0cd7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -4,31 +4,8 @@ warn: Sockets disabled, not accepting gdb connections warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -warn: The ccsidr register isn't implemented and always reads as 0. -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 -warn: LCD dual screen mode not supported -warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 -hack: be nice to actually delete the event here +panic: Not supported on checker! + @ cycle 197694500 +[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130] +Memory Usage: 355632 KBytes +Program aborted at cycle 197694500 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index f106f905a..8772dfecb 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:05:39 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 02:25:32 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2502549875500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 4976e4992..e69de29bb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,978 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 2.502550 # Number of seconds simulated -sim_ticks 2502549875500 # Number of ticks simulated -final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75474 # Simulator instruction rate (inst/s) -host_op_rate 97450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3170228022 # Simulator tick rate (ticks/s) -host_mem_usage 386888 # Number of bytes of host memory used -host_seconds 789.39 # Real time elapsed on the host -sim_insts 59578267 # Number of instructions simulated -sim_ops 76925839 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64431 # number of replacements -system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use -system.l2c.total_refs 2028510 # Total number of references to valid blocks. -system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits -system.l2c.Writeback_hits::total 675442 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits -system.l2c.overall_hits::cpu.inst 977935 # number of overall hits -system.l2c.overall_hits::cpu.data 496445 # number of overall hits -system.l2c.overall_hits::total 1608169 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses -system.l2c.demand_misses::total 156364 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12384 # number of overall misses -system.l2c.overall_misses::cpu.data 143920 # number of overall misses -system.l2c.overall_misses::total 156364 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59159 # number of writebacks -system.l2c.writebacks::total 59159 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048164 # DTB read hits -system.cpu.checker.dtb.read_misses 7309 # DTB read misses -system.cpu.checker.dtb.write_hits 11293826 # DTB write hits -system.cpu.checker.dtb.write_misses 2190 # DTB write misses -system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055473 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296016 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26341990 # DTB hits -system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26351489 # DTB accesses -system.cpu.checker.itb.inst_hits 60744881 # ITB inst hits -system.cpu.checker.itb.inst_misses 4471 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60749352 # ITB inst accesses -system.cpu.checker.itb.hits 60744881 # DTB hits -system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60749352 # DTB accesses -system.cpu.checker.numCycles 77204260 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51771660 # DTB read hits -system.cpu.dtb.read_misses 81258 # DTB read misses -system.cpu.dtb.write_hits 11880398 # DTB write hits -system.cpu.dtb.write_misses 17961 # DTB write misses -system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8043 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51852918 # DTB read accesses -system.cpu.dtb.write_accesses 11898359 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63652058 # DTB hits -system.cpu.dtb.misses 99219 # DTB misses -system.cpu.dtb.accesses 63751277 # DTB accesses -system.cpu.itb.inst_hits 13142261 # ITB inst hits -system.cpu.itb.inst_misses 12247 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5262 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154508 # ITB inst accesses -system.cpu.itb.hits 13142261 # DTB hits -system.cpu.itb.misses 12247 # DTB misses -system.cpu.itb.accesses 13154508 # DTB accesses -system.cpu.numCycles 413642740 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued -system.cpu.iq.rate 0.301258 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 256054 # number of nop insts executed -system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed -system.cpu.iew.exec_branches 11412736 # Number of branches executed -system.cpu.iew.exec_stores 12391364 # Number of stores executed -system.cpu.iew.exec_rate 0.293583 # Inst execution rate -system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46459932 # num instructions producing a value -system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value -system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back -system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59728648 # Number of instructions committed -system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513345 # Number of memory references committed -system.cpu.commit.loads 15715170 # Number of loads committed -system.cpu.commit.membars 413057 # Number of memory barriers committed -system.cpu.commit.branches 9904308 # Number of branches committed -system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. -system.cpu.commit.function_calls 995953 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached -system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 246021016 # The number of ROB reads -system.cpu.rob.rob_writes 206855771 # The number of ROB writes -system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59578267 # Number of Instructions Simulated -system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated -system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551124725 # number of integer regfile reads -system.cpu.int_regfile_writes 87730819 # number of integer regfile writes -system.cpu.fp_regfile_reads 8186 # number of floating regfile reads -system.cpu.fp_regfile_writes 2858 # number of floating regfile writes -system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads -system.cpu.misc_regfile_writes 912697 # number of misc regfile writes -system.cpu.icache.replacements 991190 # number of replacements -system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use -system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits -system.cpu.icache.overall_hits::total 12061455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses -system.cpu.icache.overall_misses::total 1076423 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67899 # number of writebacks -system.cpu.icache.writebacks::total 67899 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643139 # number of replacements -system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use -system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits -system.cpu.dcache.overall_hits::total 21161261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses -system.cpu.dcache.overall_misses::total 3758563 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks -system.cpu.dcache.writebacks::total 607543 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 0 # number of replacements -system.iocache.tagsinuse 0 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.avg_refs nan # Average number of references to valid blocks. -system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 8ee00f929..7a79f323f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -1023,7 +1023,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 6f1b9eba3..523f8a126 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -10,10 +10,10 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index fe27005da..904402304 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:16:08 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 02:25:35 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2581527583500 because m5_exit instruction encountered +Exiting @ tick 2582310281500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index ba015b214..977ccc85a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.581528 # Number of seconds simulated -sim_ticks 2581527583500 # Number of ticks simulated -final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.582310 # Number of seconds simulated +sim_ticks 2582310281500 # Number of ticks simulated +final_tick 2582310281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89313 # Simulator instruction rate (inst/s) -host_op_rate 115365 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3717496726 # Simulator tick rate (ticks/s) -host_mem_usage 390980 # Number of bytes of host memory used -host_seconds 694.43 # Real time elapsed on the host -sim_insts 62021206 # Number of instructions simulated -sim_ops 80112751 # Number of ops (including micro ops) simulated +host_inst_rate 62666 # Simulator instruction rate (inst/s) +host_op_rate 80652 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2566586582 # Simulator tick rate (ticks/s) +host_mem_usage 395816 # Number of bytes of host memory used +host_seconds 1006.13 # Real time elapsed on the host +sim_insts 63050246 # Number of instructions simulated +sim_ops 81146063 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4372212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5220016 # Number of bytes read from this memory +system.physmem.bytes_read::total 129953444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4241024 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7270160 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6196 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6650 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81589 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105053 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66266 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823550 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46290976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1693140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 273 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2021452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50324488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318375 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1642337 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6583 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1166450 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815370 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1642337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46290976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1699723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3187902 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53139859 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -29,292 +84,237 @@ system.realview.nvmem.bw_inst_read::total 149 # I system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory -system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72536 # number of replacements -system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use -system.l2c.total_refs 2019266 # Total number of references to valid blocks. -system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.660834 # Average number of references to valid blocks. +system.l2c.replacements 72453 # number of replacements +system.l2c.tagsinuse 52989.750711 # Cycle average of tags in use +system.l2c.total_refs 1967154 # Total number of references to valid blocks. +system.l2c.sampled_refs 137652 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.290777 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37689.434458 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.667894 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004429 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4220.453796 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2953.326384 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 6.708393 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4009.126872 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4107.028485 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575095 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits -system.l2c.Writeback_hits::total 645710 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40402.220460 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40740.913730 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40028.692132 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40049.083314 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.487487 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.794872 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40019.031142 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40020.618557 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41111.835957 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40931.189956 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41013.105098 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41131.535379 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41050.012880 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41007.797123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40890.905956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40971.489573 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -509,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9084255 # DTB read hits -system.cpu0.dtb.read_misses 36769 # DTB read misses -system.cpu0.dtb.write_hits 5284576 # DTB write hits -system.cpu0.dtb.write_misses 6773 # DTB write misses +system.cpu0.dtb.read_hits 9083896 # DTB read hits +system.cpu0.dtb.read_misses 37543 # DTB read misses +system.cpu0.dtb.write_hits 5286239 # DTB write hits +system.cpu0.dtb.write_misses 6882 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2244 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1393 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 382 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9121024 # DTB read accesses -system.cpu0.dtb.write_accesses 5291349 # DTB write accesses +system.cpu0.dtb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9121439 # DTB read accesses +system.cpu0.dtb.write_accesses 5293121 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14368831 # DTB hits -system.cpu0.dtb.misses 43542 # DTB misses -system.cpu0.dtb.accesses 14412373 # DTB accesses -system.cpu0.itb.inst_hits 4421795 # ITB inst hits -system.cpu0.itb.inst_misses 5958 # ITB inst misses +system.cpu0.dtb.hits 14370135 # DTB hits +system.cpu0.dtb.misses 44425 # DTB misses +system.cpu0.dtb.accesses 14414560 # DTB accesses +system.cpu0.itb.inst_hits 4418601 # ITB inst hits +system.cpu0.itb.inst_misses 6114 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -538,542 +536,544 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1409 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1633 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses -system.cpu0.itb.hits 4421795 # DTB hits -system.cpu0.itb.misses 5958 # DTB misses -system.cpu0.itb.accesses 4427753 # DTB accesses -system.cpu0.numCycles 66112093 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4424715 # ITB inst accesses +system.cpu0.itb.hits 4418601 # DTB hits +system.cpu0.itb.misses 6114 # DTB misses +system.cpu0.itb.accesses 4424715 # DTB accesses +system.cpu0.numCycles 66354055 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6346252 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4857071 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316053 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 4075974 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3037671 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700378 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 30829 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12963003 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33274045 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6346252 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3738049 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7812188 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1602844 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 89446 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 22023764 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5932 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 73578 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90886 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 179 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4416774 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175280 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3223 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 44209960 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.971808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.352806 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36406101 82.35% 82.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 622907 1.41% 83.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 820090 1.85% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 691511 1.56% 87.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 794774 1.80% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578673 1.31% 90.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 721468 1.63% 91.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 370773 0.84% 92.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3203663 7.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 44209960 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.095642 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.501462 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13460475 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 22052761 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7004876 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 606078 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1085770 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 992839 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66349 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41502146 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 217622 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1085770 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14072541 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6178049 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13569314 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6948288 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2355998 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40249124 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2572 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 473537 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1335703 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 188 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40597200 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 181819083 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 181783808 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 35275 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31678350 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8918849 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 463403 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 418800 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5692374 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7927385 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5883720 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132627 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1230816 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 38008933 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 947103 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38247071 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 93468 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6756686 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14324325 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258267 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 44209960 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.865123 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.479533 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 28324155 64.07% 64.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6346765 14.36% 78.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3236431 7.32% 85.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2507997 5.67% 91.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2107881 4.77% 96.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 937016 2.12% 98.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 515116 1.17% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 180639 0.41% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53960 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 44209960 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27715 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 460 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 839091 78.45% 81.09% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202283 18.91% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22968400 60.05% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50115 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 14 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 11 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9563149 25.00% 85.33% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5612341 14.67% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued -system.cpu0.iq.rate 0.570847 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38247071 # Type of FU issued +system.cpu0.iq.rate 0.576409 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069549 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.027964 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 121902835 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45721169 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35306324 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8427 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4840 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3930 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39259896 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4380 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 325721 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1504145 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3982 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13879 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 608088 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149487 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5263 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1085770 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4069341 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 129560 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39094255 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 87678 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7927385 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5883720 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 614122 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49261 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17662 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13879 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 160370 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144551 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 304921 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37828601 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9401576 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 418470 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 138361 # number of nop insts executed -system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4921687 # Number of branches executed -system.cpu0.iew.exec_stores 5556491 # Number of stores executed -system.cpu0.iew.exec_rate 0.564758 # Inst execution rate -system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18360594 # num instructions producing a value -system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value +system.cpu0.iew.exec_nop 138219 # number of nop insts executed +system.cpu0.iew.exec_refs 14960222 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5069889 # Number of branches executed +system.cpu0.iew.exec_stores 5558646 # Number of stores executed +system.cpu0.iew.exec_rate 0.570102 # Inst execution rate +system.cpu0.iew.wb_sent 37608832 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35310254 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18670977 # num instructions producing a value +system.cpu0.iew.wb_consumers 35573590 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.532149 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524855 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 24262280 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31997725 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6679991 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688836 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 267429 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 43160582 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.741365 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.695624 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 31020137 71.87% 71.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6071618 14.07% 85.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1950463 4.52% 90.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1036843 2.40% 92.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 799662 1.85% 94.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 507487 1.18% 95.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 407135 0.94% 96.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 202137 0.47% 97.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1165100 2.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24134633 # Number of instructions committed -system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 43160582 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24262280 # Number of instructions committed +system.cpu0.commit.committedOps 31997725 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11694422 # Number of memory references committed -system.cpu0.commit.loads 6420941 # Number of loads committed -system.cpu0.commit.membars 234529 # Number of memory barriers committed -system.cpu0.commit.branches 4382702 # Number of branches committed +system.cpu0.commit.refs 11698872 # Number of memory references committed +system.cpu0.commit.loads 6423240 # Number of loads committed +system.cpu0.commit.membars 234547 # Number of memory barriers committed +system.cpu0.commit.branches 4415502 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499856 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28265931 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499946 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1165100 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 79207972 # The number of ROB reads -system.cpu0.rob.rob_writes 77724528 # The number of ROB writes -system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24053891 # Number of Instructions Simulated -system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated -system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads -system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads -system.cpu0.fp_regfile_writes 898 # number of floating regfile writes -system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes -system.cpu0.icache.replacements 406974 # number of replacements -system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use -system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor +system.cpu0.rob.rob_reads 79788976 # The number of ROB reads +system.cpu0.rob.rob_writes 78443760 # The number of ROB writes +system.cpu0.timesIdled 426851 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22144095 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5098222727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24181538 # Number of Instructions Simulated +system.cpu0.committedOps 31916983 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24181538 # Number of Instructions Simulated +system.cpu0.cpi 2.743996 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.743996 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.364432 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.364432 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176533858 # number of integer regfile reads +system.cpu0.int_regfile_writes 35079827 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3404 # number of floating regfile reads +system.cpu0.fp_regfile_writes 942 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47584444 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527516 # number of misc regfile writes +system.cpu0.icache.replacements 406873 # number of replacements +system.cpu0.icache.tagsinuse 511.614484 # Cycle average of tags in use +system.cpu0.icache.total_refs 3975135 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 407385 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.757686 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6470209000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.614484 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3978434 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3978434 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3978434 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3978434 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3978434 # number of overall hits -system.cpu0.icache.overall_hits::total 3978434 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 441298 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 441298 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 441298 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 441298 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 441298 # number of overall misses -system.cpu0.icache.overall_misses::total 441298 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7186656997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7186656997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7186656997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7186656997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3975135 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3975135 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3975135 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3975135 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3975135 # number of overall hits +system.cpu0.icache.overall_hits::total 3975135 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441500 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 441500 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441500 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 441500 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441500 # number of overall misses +system.cpu0.icache.overall_misses::total 441500 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7129067996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7129067996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7129067996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7129067996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7129067996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7129067996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4416635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4416635 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4416635 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4416635 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4416635 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4416635 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099963 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099963 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099963 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099963 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099963 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099963 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16147.379379 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16147.379379 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16147.379379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16147.379379 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16147.379379 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1348496 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8074.826347 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks -system.cpu0.icache.writebacks::total 29234 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 34106 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 34106 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 34106 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 34106 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 34106 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 34106 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407394 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 407394 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 407394 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 407394 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 407394 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 407394 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5468654996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5468654996 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5468654996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5468654996 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5468654996 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5468654996 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092241 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092241 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092241 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092241 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13423.504018 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13423.504018 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13423.504018 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275761 # number of replacements -system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275592 # number of replacements +system.cpu0.dcache.tagsinuse 476.837382 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9554493 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276104 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.604689 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174478 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171499 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171499 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9159400 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9159400 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9159400 # number of overall hits -system.cpu0.dcache.overall_hits::total 9159400 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401255 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401255 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1594245 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1594245 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9007 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9007 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7794 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7794 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1995500 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1995500 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1995500 # number of overall misses -system.cpu0.dcache.overall_misses::total 1995500 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7289566500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7289566500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71816395371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71816395371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114642500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 114642500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93715000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 93715000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 79105961871 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 79105961871 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 79105961871 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 79105961871 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6335948 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6335948 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818952 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4818952 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183485 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 476.837382 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.931323 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.931323 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5935954 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5935954 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3226635 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3226635 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174405 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174405 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171548 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171548 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9162589 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9162589 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9162589 # number of overall hits +system.cpu0.dcache.overall_hits::total 9162589 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 400527 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 400527 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1594104 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1594104 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8985 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8985 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7776 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7776 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1994631 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1994631 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1994631 # number of overall misses +system.cpu0.dcache.overall_misses::total 1994631 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7261400500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7261400500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71837415855 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71837415855 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113971500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 113971500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93410500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 93410500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 79098816355 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 79098816355 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 79098816355 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 79098816355 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6336481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6336481 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820739 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4820739 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183390 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183390 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179324 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179324 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11157220 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11157220 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11157220 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11157220 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063210 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063210 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330676 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330676 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048994 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048994 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043363 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043363 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178775 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178775 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178775 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178775 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18129.615482 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18129.615482 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45064.447398 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45064.447398 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12684.641068 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12684.641068 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12012.667181 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12012.667181 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39655.864345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39655.864345 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39655.864345 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7527492 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1548500 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1462 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5148.763338 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17798.850575 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks -system.cpu0.dcache.writebacks::total 255942 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255542 # number of writebacks +system.cpu0.dcache.writebacks::total 255542 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211236 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 211236 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463026 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1463026 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 516 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674262 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1674262 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674262 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1674262 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189291 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189291 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131078 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131078 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7773 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320369 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320369 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320369 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2800937917 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2800937917 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685815512 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685815512 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79569505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79569505 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 68924555 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7486753429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7486753429 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7486753429 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7486753429 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315126500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315126500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849486399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849486399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164612899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164612899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029873 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046180 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046180 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043346 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043346 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028714 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028714 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028714 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14796.994664 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14796.994664 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.298814 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.298814 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9395.383753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9395.383753 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8867.175479 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23369.156907 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23369.156907 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1083,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43446349 # DTB read hits -system.cpu1.dtb.read_misses 46684 # DTB read misses -system.cpu1.dtb.write_hits 7088138 # DTB write hits -system.cpu1.dtb.write_misses 12274 # DTB write misses +system.cpu1.dtb.read_hits 43445270 # DTB read hits +system.cpu1.dtb.read_misses 46285 # DTB read misses +system.cpu1.dtb.write_hits 7088572 # DTB write hits +system.cpu1.dtb.write_misses 12217 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2504 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3688 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 371 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43493033 # DTB read accesses -system.cpu1.dtb.write_accesses 7100412 # DTB write accesses +system.cpu1.dtb.perms_faults 674 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43491555 # DTB read accesses +system.cpu1.dtb.write_accesses 7100789 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50534487 # DTB hits -system.cpu1.dtb.misses 58958 # DTB misses -system.cpu1.dtb.accesses 50593445 # DTB accesses -system.cpu1.itb.inst_hits 9221438 # ITB inst hits -system.cpu1.itb.inst_misses 6034 # ITB inst misses +system.cpu1.dtb.hits 50533842 # DTB hits +system.cpu1.dtb.misses 58502 # DTB misses +system.cpu1.dtb.accesses 50592344 # DTB accesses +system.cpu1.itb.inst_hits 9223213 # ITB inst hits +system.cpu1.itb.inst_misses 6180 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1112,121 +1112,121 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1615 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1780 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses -system.cpu1.itb.hits 9221438 # DTB hits -system.cpu1.itb.misses 6034 # DTB misses -system.cpu1.itb.accesses 9227472 # DTB accesses -system.cpu1.numCycles 353824423 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9229393 # ITB inst accesses +system.cpu1.itb.hits 9223213 # DTB hits +system.cpu1.itb.misses 6180 # DTB misses +system.cpu1.itb.accesses 9229393 # DTB accesses +system.cpu1.numCycles 355232424 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9848764 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 8083275 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 447123 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6868345 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5662939 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 832004 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49676 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22148379 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71952458 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9848764 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6494943 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15333431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4632908 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88364 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 74838070 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 63991 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 141562 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 138 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9221022 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 859641 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3677 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 115781579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.750934 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.109459 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100456410 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 829573 0.72% 87.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1015846 0.88% 88.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2061622 1.78% 90.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1645380 1.42% 91.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 616095 0.53% 92.09% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2274849 1.96% 94.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 467300 0.40% 94.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6414504 5.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 115781579 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.027725 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.202550 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23776389 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 74601447 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13781615 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 561009 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3061119 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1241407 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102665 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 81190791 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 341149 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3061119 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25333003 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33967991 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 36116187 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12703540 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4599739 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74711209 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 20422 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 719883 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3284162 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33659 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79078972 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 344223554 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 344164086 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59468 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50180386 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28898586 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 486916 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 421354 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8389500 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14026564 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8607423 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1068694 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1518812 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67421543 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1209489 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91958955 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 109721 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18898752 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53543776 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 290002 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 115781579 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.794245 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521941 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83973534 72.53% 72.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9124499 7.88% 80.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4576997 3.95% 84.36% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4009566 3.46% 87.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10699106 9.24% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1974757 1.71% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1060771 0.92% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 281863 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 80486 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 115781579 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29310 0.37% 0.37% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available @@ -1255,403 +1255,397 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7573445 95.84% 96.23% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298199 3.77% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.34% 0.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39470238 42.92% 43.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61477 0.07% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1690 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44643108 48.55% 91.88% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7468676 8.12% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued -system.cpu1.iq.rate 0.256048 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91958955 # Type of FU issued +system.cpu1.iq.rate 0.258870 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7901947 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.085929 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 307754751 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 87542996 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55769663 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14772 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8137 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6817 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99539441 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7724 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 371642 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4037130 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6814 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21954 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1589436 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965709 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1043610 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3061119 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25601852 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 406330 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68756671 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 131432 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14026564 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8607423 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 899609 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 81519 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 7124 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21954 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 226065 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 196785 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 422850 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 89098857 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43830249 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2860098 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 125146 # number of nop insts executed -system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7024509 # Number of branches executed -system.cpu1.iew.exec_stores 7393409 # Number of stores executed -system.cpu1.iew.exec_rate 0.248048 # Inst execution rate -system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30044182 # num instructions producing a value -system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value +system.cpu1.iew.exec_nop 125639 # number of nop insts executed +system.cpu1.iew.exec_refs 51224079 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7396455 # Number of branches executed +system.cpu1.iew.exec_stores 7393830 # Number of stores executed +system.cpu1.iew.exec_rate 0.250818 # Inst execution rate +system.cpu1.iew.wb_sent 87931251 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55776480 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30792122 # num instructions producing a value +system.cpu1.iew.wb_consumers 54566321 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.157014 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.564306 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38938347 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 49298719 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 19014978 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919487 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 376070 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112768879 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.437166 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.403258 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95484340 84.67% 84.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8537208 7.57% 92.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2210726 1.96% 94.20% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1312266 1.16% 95.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1283048 1.14% 96.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 588048 0.52% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1003635 0.89% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 487845 0.43% 98.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1861763 1.65% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38036954 # Number of instructions committed -system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112768879 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38938347 # Number of instructions committed +system.cpu1.commit.committedOps 49298719 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17007249 # Number of memory references committed -system.cpu1.commit.loads 9989241 # Number of loads committed -system.cpu1.commit.membars 202226 # Number of memory barriers committed -system.cpu1.commit.branches 5993368 # Number of branches committed +system.cpu1.commit.refs 17007421 # Number of memory references committed +system.cpu1.commit.loads 9989434 # Number of loads committed +system.cpu1.commit.membars 202281 # Number of memory barriers committed +system.cpu1.commit.branches 6220621 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556157 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43690243 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556165 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1861763 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 175585773 # The number of ROB reads -system.cpu1.rob.rob_writes 137553768 # The number of ROB writes -system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37967315 # Number of Instructions Simulated -system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated -system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads -system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes -system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes -system.cpu1.icache.replacements 622931 # number of replacements -system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use -system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits -system.cpu1.icache.overall_hits::total 8545880 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses -system.cpu1.icache.overall_misses::total 673372 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked +system.cpu1.rob.rob_reads 178106600 # The number of ROB reads +system.cpu1.rob.rob_writes 139781050 # The number of ROB writes +system.cpu1.timesIdled 1519184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 239450845 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4808685831 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38868708 # Number of Instructions Simulated +system.cpu1.committedOps 49229080 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38868708 # Number of Instructions Simulated +system.cpu1.cpi 9.139291 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.139291 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.109418 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.109418 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 398713179 # number of integer regfile reads +system.cpu1.int_regfile_writes 58485097 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4918 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2338 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91819776 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429481 # number of misc regfile writes +system.cpu1.icache.replacements 621812 # number of replacements +system.cpu1.icache.tagsinuse 498.762593 # Cycle average of tags in use +system.cpu1.icache.total_refs 8548797 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 622324 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.736891 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74633258000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.762593 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974146 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974146 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8548797 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8548797 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8548797 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8548797 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8548797 # number of overall hits +system.cpu1.icache.overall_hits::total 8548797 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 672174 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 672174 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 672174 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 672174 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 672174 # number of overall misses +system.cpu1.icache.overall_misses::total 672174 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10613540997 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10613540997 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10613540997 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10613540997 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10613540997 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10613540997 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9220971 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9220971 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9220971 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9220971 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9220971 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9220971 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072896 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072896 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072896 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072896 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072896 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072896 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15789.871368 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15789.871368 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15789.871368 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15789.871368 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15789.871368 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1180997 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 198 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 5964.631313 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks -system.cpu1.icache.writebacks::total 33068 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49820 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49820 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49820 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49820 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49820 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49820 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622354 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 622354 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 622354 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 622354 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 622354 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 622354 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8128418498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8128418498 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8128418498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8128418498 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8128418498 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8128418498 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067493 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067493 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067493 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067493 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13060.763646 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13060.763646 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13060.763646 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # 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Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits -system.cpu1.dcache.overall_hits::total 12866610 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 410185 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 410185 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1595357 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1595357 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10900 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10900 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2005542 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2005542 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2005542 # number of overall misses -system.cpu1.dcache.overall_misses::total 2005542 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # 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number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14872152 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14872152 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045454 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272801 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.272801 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119597 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119597 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097662 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097662 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134852 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.134852 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134852 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.134852 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8698.990826 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8698.990826 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29196505 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5606000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6645 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4393.755455 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 362958 # 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number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 106100 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100714 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100714 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12860686 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12860686 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12860686 # number of overall hits +system.cpu1.dcache.overall_hits::total 12860686 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 410615 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 410615 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1595619 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1595619 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14222 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14222 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10905 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10905 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2006234 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2006234 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2006234 # number of overall misses +system.cpu1.dcache.overall_misses::total 2006234 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8133768000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8133768000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66485489237 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 66485489237 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 165213500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 165213500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94467000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94467000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74619257237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74619257237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74619257237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74619257237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9018883 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9018883 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848037 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5848037 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 120322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111619 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111619 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14866920 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14866920 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14866920 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14866920 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045528 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045528 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272847 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272847 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118199 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118199 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097698 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134946 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134946 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134946 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134946 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19808.745418 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19808.745418 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41667.521656 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41667.521656 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11616.755731 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11616.755731 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8662.723521 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8662.723521 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37193.695868 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 37193.695868 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37193.695868 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 37193.695868 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29476015 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5620000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6671 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 172 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4418.530205 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32674.418605 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks -system.cpu1.dcache.writebacks::total 327467 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1432552 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1457 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1611743 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1611743 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1611743 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1611743 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 230994 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 230994 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162805 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162805 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12821 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327729 # number of writebacks +system.cpu1.dcache.writebacks::total 327729 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179332 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 179332 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432824 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1432824 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1612156 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1612156 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1612156 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1612156 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231283 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231283 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162795 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162795 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10900 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394078 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394078 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394078 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394078 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3556387454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3556387454 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5557887685 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5557887685 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 103446504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 103446504 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60421505 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60421505 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9114275139 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9114275139 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9114275139 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9114275139 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004022500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004022500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40580989302 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40580989302 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177585011802 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177585011802 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025644 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025644 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027838 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027838 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.106173 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.106173 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097654 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097654 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026507 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026507 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15376.778466 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15376.778466 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34140.407783 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34140.407783 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8097.573699 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8097.573699 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5543.257339 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5543.257339 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23128.099359 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23128.099359 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1673,18 +1667,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305599683923 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305599683923 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305599683923 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43782 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53899 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 71f536288..9e6ff3218 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -581,7 +581,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 34717b2ec..c9f3d2864 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:04:56 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 02:23:14 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2502549875500 because m5_exit instruction encountered +Exiting @ tick 2503329223500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 6df4de0df..b903804f3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.502550 # Number of seconds simulated -sim_ticks 2502549875500 # Number of ticks simulated -final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.503329 # Number of seconds simulated +sim_ticks 2503329223500 # Number of ticks simulated +final_tick 2503329223500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90191 # Simulator instruction rate (inst/s) -host_op_rate 116452 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3788406278 # Simulator tick rate (ticks/s) -host_mem_usage 386884 # Number of bytes of host memory used -host_seconds 660.58 # Real time elapsed on the host -sim_insts 59578267 # Number of instructions simulated -sim_ops 76925839 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +host_inst_rate 62297 # Simulator instruction rate (inst/s) +host_op_rate 80132 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2573650165 # Simulator tick rate (ticks/s) +host_mem_usage 394796 # Number of bytes of host memory used +host_seconds 972.68 # Real time elapsed on the host +sim_insts 60594713 # Number of instructions simulated +sim_ops 77942287 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3712 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory -system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 799552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory +system.physmem.bytes_read::total 129435024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 799552 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3785216 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 6801288 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 58 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12493 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096888 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59144 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813162 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47751475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1483 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319395 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3632775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51705154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319395 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1512073 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1204824 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2716897 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1512073 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47751475 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1483 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4837599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54422052 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64431 # number of replacements -system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use -system.l2c.total_refs 2028510 # Total number of references to valid blocks. -system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor +system.l2c.replacements 64407 # number of replacements +system.l2c.tagsinuse 51237.721374 # Cycle average of tags in use +system.l2c.total_refs 1963815 # Total number of references to valid blocks. +system.l2c.sampled_refs 129804 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.129079 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2492699118000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36773.515896 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 46.128401 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 8177.854263 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6240.222629 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.561119 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000704 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits -system.l2c.Writeback_hits::total 675442 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.occ_percent::cpu.inst 0.124784 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095218 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781826 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 123734 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 976636 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 387128 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1499425 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 607519 # number of Writeback hits +system.l2c.Writeback_hits::total 607519 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 41 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits -system.l2c.overall_hits::cpu.inst 977935 # number of overall hits -system.l2c.overall_hits::cpu.data 496445 # number of overall hits -system.l2c.overall_hits::total 1608169 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses +system.l2c.ReadExReq_hits::cpu.data 112732 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112732 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 123734 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11927 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 976636 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 499860 # number of demand (read+write) hits +system.l2c.demand_hits::total 1612157 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 123734 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11927 # number of overall hits +system.l2c.overall_hits::cpu.inst 976636 # number of overall hits +system.l2c.overall_hits::cpu.data 499860 # number of overall hits +system.l2c.overall_hits::total 1612157 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 58 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.inst 12374 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23124 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133219 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133219 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 58 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses -system.l2c.demand_misses::total 156364 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 59 # 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number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 994500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7086596499 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7086596499 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3035000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu.inst 659327498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7648967497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8311389995 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3035000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1764533 # 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average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162829894011 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162835217011 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026721 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015142 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541649 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541649 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.223448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088365 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000469 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000084 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012503 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.223448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088365 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41080.219877 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40479.256820 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40800.975884 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.758336 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.758336 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40966.138456 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40966.138456 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40103.448276 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41080.219877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40930.159396 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40941.772131 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51771660 # DTB read hits -system.cpu.dtb.read_misses 81258 # DTB read misses -system.cpu.dtb.write_hits 11880398 # DTB write hits -system.cpu.dtb.write_misses 17961 # DTB write misses +system.cpu.dtb.read_hits 51771178 # DTB read hits +system.cpu.dtb.read_misses 82022 # DTB read misses +system.cpu.dtb.write_hits 11879780 # DTB write hits +system.cpu.dtb.write_misses 18404 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4471 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4476 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2874 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 631 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51852918 # DTB read accesses -system.cpu.dtb.write_accesses 11898359 # DTB write accesses +system.cpu.dtb.perms_faults 1260 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51853200 # DTB read accesses +system.cpu.dtb.write_accesses 11898184 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63652058 # DTB hits -system.cpu.dtb.misses 99219 # DTB misses -system.cpu.dtb.accesses 63751277 # DTB accesses -system.cpu.itb.inst_hits 13142261 # ITB inst hits -system.cpu.itb.inst_misses 12247 # ITB inst misses +system.cpu.dtb.hits 63650958 # DTB hits +system.cpu.dtb.misses 100426 # DTB misses +system.cpu.dtb.accesses 63751384 # DTB accesses +system.cpu.itb.inst_hits 13147400 # ITB inst hits +system.cpu.itb.inst_misses 12275 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,122 +361,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2634 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2641 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3416 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154508 # ITB inst accesses -system.cpu.itb.hits 13142261 # DTB hits -system.cpu.itb.misses 12247 # DTB misses -system.cpu.itb.accesses 13154508 # DTB accesses -system.cpu.numCycles 413642740 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13159675 # ITB inst accesses +system.cpu.itb.hits 13147400 # DTB hits +system.cpu.itb.misses 12275 # DTB misses +system.cpu.itb.accesses 13159675 # DTB accesses +system.cpu.numCycles 415310668 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits +system.cpu.BPredUnit.lookups 15527738 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12466555 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753811 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10646284 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8367014 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1449693 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80905 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33357472 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101736318 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15527738 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9816707 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22310929 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6078281 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 161634 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 94635812 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2484 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 132549 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208778 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 375 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13143214 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1025665 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6564 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 154991090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.809239 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.178893 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 132697054 85.62% 85.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1371702 0.89% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1758298 1.13% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2653739 1.71% 89.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2357523 1.52% 90.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1143564 0.74% 91.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2918516 1.88% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 809258 0.52% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9281436 5.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 154991090 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.037388 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.244964 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35540110 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94304374 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20024957 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1112327 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4009322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100739 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174603 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118268322 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 570412 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4009322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37657945 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39869078 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47822984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18880557 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6751204 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110681454 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22988 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1160036 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4497834 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31020 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115504222 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506609726 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506516210 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93516 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78727449 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36776772 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 900485 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 799637 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13564830 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21065339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13879000 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1961867 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2663971 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101316574 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2057711 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126458108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199553 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24657438 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65563204 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 513311 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 154991090 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.815906 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.514046 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108868078 70.24% 70.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14887887 9.61% 79.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7383585 4.76% 84.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6313472 4.07% 88.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12622401 8.14% 96.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2812506 1.81% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1537255 0.99% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 440277 0.28% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125629 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 154991090 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54148 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available @@ -504,399 +504,397 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8364176 94.75% 95.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 409089 4.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60068751 47.50% 47.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95236 0.08% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.87% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53417106 42.24% 90.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12511205 9.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued -system.cpu.iq.rate 0.301258 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126458108 # Type of FU issued +system.cpu.iq.rate 0.304490 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8827417 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069805 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 417011386 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128052835 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87416470 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22950 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12920 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10331 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134909754 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12105 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 645788 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5350138 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35101 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2080838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107263 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1048290 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4009322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29478613 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 536036 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103628902 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217385 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21065339 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13879000 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1466402 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 126510 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 31155 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35101 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 376939 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332400 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 709339 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123236608 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52461044 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3221500 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 256054 # number of nop insts executed -system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed -system.cpu.iew.exec_branches 11412736 # Number of branches executed -system.cpu.iew.exec_stores 12391364 # Number of stores executed -system.cpu.iew.exec_rate 0.293583 # Inst execution rate -system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46459932 # num instructions producing a value -system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value +system.cpu.iew.exec_nop 254617 # number of nop insts executed +system.cpu.iew.exec_refs 64851969 # number of memory reference insts executed +system.cpu.iew.exec_branches 11926568 # Number of branches executed +system.cpu.iew.exec_stores 12390925 # Number of stores executed +system.cpu.iew.exec_rate 0.296734 # Inst execution rate +system.cpu.iew.wb_sent 121860265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87426801 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47494075 # num instructions producing a value +system.cpu.iew.wb_consumers 86379183 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back +system.cpu.iew.wb_rate 0.210509 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549832 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 60745094 # The number of committed instructions +system.cpu.commit.commitCommittedOps 78092668 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24728606 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1544400 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625654 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 151064180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.516950 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.491641 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 122872114 81.34% 81.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13991345 9.26% 90.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3943128 2.61% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2231050 1.48% 94.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2009345 1.33% 96.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1063949 0.70% 96.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402638 0.93% 97.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 655924 0.43% 98.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2894687 1.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59728648 # Number of instructions committed -system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 151064180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60745094 # Number of instructions committed +system.cpu.commit.committedOps 78092668 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513345 # Number of memory references committed -system.cpu.commit.loads 15715170 # Number of loads committed -system.cpu.commit.membars 413057 # Number of memory barriers committed -system.cpu.commit.branches 9904308 # Number of branches committed +system.cpu.commit.refs 27513363 # Number of memory references committed +system.cpu.commit.loads 15715201 # Number of loads committed +system.cpu.commit.membars 413054 # Number of memory barriers committed +system.cpu.commit.branches 10161447 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. -system.cpu.commit.function_calls 995953 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69131310 # Number of committed integer instructions. +system.cpu.commit.function_calls 995952 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2894687 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 246021016 # The number of ROB reads -system.cpu.rob.rob_writes 206855771 # The number of ROB writes -system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59578267 # Number of Instructions Simulated -system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated -system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads -system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 551124722 # number of integer regfile reads -system.cpu.int_regfile_writes 87730818 # number of integer regfile writes -system.cpu.fp_regfile_reads 8186 # number of floating regfile reads -system.cpu.fp_regfile_writes 2858 # number of floating regfile writes -system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads -system.cpu.misc_regfile_writes 912697 # number of misc regfile writes -system.cpu.icache.replacements 991190 # number of replacements -system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use -system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits -system.cpu.icache.overall_hits::total 12061455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses -system.cpu.icache.overall_misses::total 1076423 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked +system.cpu.rob.rob_reads 249075594 # The number of ROB reads +system.cpu.rob.rob_writes 209750294 # The number of ROB writes +system.cpu.timesIdled 1905944 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260319578 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591259733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60594713 # Number of Instructions Simulated +system.cpu.committedOps 77942287 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60594713 # Number of Instructions Simulated +system.cpu.cpi 6.853909 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.853909 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145902 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.145902 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557815348 # number of integer regfile reads +system.cpu.int_regfile_writes 90098492 # number of integer regfile writes +system.cpu.fp_regfile_reads 8218 # number of floating regfile reads +system.cpu.fp_regfile_writes 2870 # number of floating regfile writes +system.cpu.misc_regfile_reads 134021846 # number of misc regfile reads +system.cpu.misc_regfile_writes 912706 # number of misc regfile writes +system.cpu.icache.replacements 989908 # number of replacements +system.cpu.icache.tagsinuse 511.610984 # Cycle average of tags in use +system.cpu.icache.total_refs 12068184 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 990420 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.184915 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426400000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.610984 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999240 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999240 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12068184 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12068184 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12068184 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12068184 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12068184 # number of overall hits +system.cpu.icache.overall_hits::total 12068184 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1074896 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1074896 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1074896 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1074896 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1074896 # number of overall misses +system.cpu.icache.overall_misses::total 1074896 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16638687991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16638687991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16638687991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16638687991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16638687991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16638687991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13143080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13143080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13143080 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13143080 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13143080 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13143080 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081784 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081784 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081784 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081784 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081784 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081784 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15479.346831 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15479.346831 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15479.346831 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15479.346831 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15479.346831 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15479.346831 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2960492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 448 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6608.241071 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67899 # number of writebacks -system.cpu.icache.writebacks::total 67899 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84437 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84437 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84437 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84437 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84437 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84437 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 990459 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 990459 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 990459 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 990459 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 990459 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 990459 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12623481992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12623481992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12623481992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12623481992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12623481992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12623481992 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075360 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075360 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075360 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075360 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.082827 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.082827 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.082827 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.082827 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643139 # number of replacements -system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use -system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. +system.cpu.dcache.replacements 643258 # number of replacements +system.cpu.dcache.tagsinuse 511.991338 # Cycle average of tags in use +system.cpu.dcache.total_refs 21734239 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643770 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.760876 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.991338 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits -system.cpu.dcache.overall_hits::total 21161261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765252 # 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number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634410 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634410 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634410 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6262166095 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6262166095 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9286622435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9286622435 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 163471000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 163471000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 289000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 289000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15548788530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15548788530 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15548788530 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15548788530 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147078103000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147078103000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41268229410 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41268229410 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188346332410 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 188346332410 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026291 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026291 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024270 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041163 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041163 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000063 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025460 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025460 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025460 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025460 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.709690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.709690 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37328.953666 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37328.953666 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13279.528838 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13279.528838 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16055.555556 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16055.555556 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24509.053341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24509.053341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24509.053341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24509.053341 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -918,16 +916,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305424568773 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305424568773 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305424568773 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88047 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |