diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
9 files changed, 470 insertions, 104 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index b11582c4e..5d60c7bc8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -570,9 +571,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -631,10 +631,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1046,9 +1045,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 1bca46ae4..086d512f2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:58:44 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2501685689500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 2501dfd76..e9f646cad 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu sim_ticks 2501685689500 # Number of ticks simulated final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54158 # Simulator instruction rate (inst/s) -host_op_rate 69928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2274069684 # Simulator tick rate (ticks/s) -host_mem_usage 384504 # Number of bytes of host memory used -host_seconds 1100.09 # Real time elapsed on the host +host_inst_rate 49441 # Simulator instruction rate (inst/s) +host_op_rate 63837 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2075989543 # Simulator tick rate (ticks/s) +host_mem_usage 387400 # Number of bytes of host memory used +host_seconds 1205.06 # Real time elapsed on the host sim_insts 59579009 # Number of instructions simulated sim_ops 76926775 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585736 # Number of bytes written to this memory -system.physmem.num_reads 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes 856669 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory +system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 119797 # number of replacements system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use system.l2c.total_refs 1834134 # Total number of references to valid blocks. @@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -676,11 +734,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked @@ -714,13 +778,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 645895 # number of replacements system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use @@ -780,17 +852,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked @@ -842,20 +926,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -876,7 +975,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 632f13a19..aff8253f7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -953,9 +954,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -1014,10 +1014,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -1429,9 +1428,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 3d3cfe606..c0177ee1d 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:58:50 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2570833934500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a45391ada..6e759f59e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,32 +4,90 @@ sim_seconds 2.570834 # Nu sim_ticks 2570833934500 # Number of ticks simulated final_tick 2570833934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63716 # Simulator instruction rate (inst/s) -host_op_rate 82290 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2641493756 # Simulator tick rate (ticks/s) -host_mem_usage 388068 # Number of bytes of host memory used -host_seconds 973.25 # Real time elapsed on the host +host_inst_rate 53678 # Simulator instruction rate (inst/s) +host_op_rate 69325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2225327298 # Simulator tick rate (ticks/s) +host_mem_usage 390932 # Number of bytes of host memory used +host_seconds 1155.26 # Real time elapsed on the host sim_insts 62012062 # Number of instructions simulated sim_ops 80088895 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 131429540 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1199424 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10175696 # Number of bytes written to this memory -system.physmem.num_reads 15128117 # Number of read requests responded to by this memory -system.physmem.num_writes 868949 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51123310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 466551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3958130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55081440 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 149 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 149 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 5376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 544832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4740532 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 654592 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5942256 # Number of bytes read from this memory +system.physmem.bytes_read::total 131429540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 544832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 654592 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1199424 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7146560 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 10175696 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 84 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 8513 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 74143 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10228 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 92874 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15128117 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 111665 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 868949 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46497622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 2091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 211928 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1843967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 254622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2311412 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51123310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 211928 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 254622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 466551 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2779861 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1171657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3958130 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2779861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46497622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 211928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1850579 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 254622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3483069 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55081440 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 320 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 130926 # number of replacements system.l2c.tagsinuse 27576.629960 # Cycle average of tags in use system.l2c.total_refs 1855308 # Total number of references to valid blocks. @@ -211,12 +269,16 @@ system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000137 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.014302 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.052466 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.024905 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.849004 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836304 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.842250 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784080 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607287 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.696438 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 0.650892 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.552698 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.592636 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000869 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.024345 # miss rate for demand accesses @@ -225,6 +287,7 @@ system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.demand_miss_rate::cpu1.itb.walker 0.000137 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.014302 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.240884 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.100520 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001635 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000869 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.024345 # miss rate for overall accesses @@ -233,6 +296,7 @@ system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.overall_miss_rate::cpu1.itb.walker 0.000137 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.014302 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.240884 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.100520 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52200 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.338109 # average ReadReq miss latency @@ -241,12 +305,16 @@ system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52316.416593 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 52243.878665 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52259.373529 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3478.081138 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6680.529301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5169.101633 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2849.619289 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8968.333333 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5494.596542 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52435.364432 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52479.021964 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52459.519720 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency @@ -255,6 +323,7 @@ system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52416.535382 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52184.523810 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52200 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52293.338109 # average overall miss latency @@ -263,6 +332,7 @@ system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52188.524590 system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.inst 52316.416593 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.data 52447.097621 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52416.535382 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,12 +451,16 @@ system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.052326 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.024846 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.849004 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836304 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.842250 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784080 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607287 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.696438 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.650892 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.552698 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.592636 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for demand accesses @@ -395,6 +469,7 @@ system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.100469 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001635 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000869 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.024336 # mshr miss rate for overall accesses @@ -403,6 +478,7 @@ system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000544 system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000137 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014285 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.240798 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.100469 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average ReadReq mshr miss latency @@ -411,12 +487,16 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40062.314308 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40079.973669 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40062.103442 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40030.245747 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40045.281307 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40043.147208 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40061.666667 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40051.152738 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40033.493643 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40096.958338 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40068.608041 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency @@ -425,6 +505,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40047.619048 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40200 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40079.003941 # average overall mshr miss latency @@ -433,16 +514,20 @@ system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40065.573770 system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40122.729504 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40092.265656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40071.044415 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -802,11 +887,17 @@ system.cpu0.icache.demand_accesses::total 3831829 # n system.cpu0.icache.overall_accesses::cpu0.inst 3831829 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::total 3831829 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.097921 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.097921 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.097921 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.097921 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.097921 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.097921 # miss rate for overall accesses system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15191.937401 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15191.937401 # average ReadReq miss latency system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15191.937401 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15191.937401 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15191.937401 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 1854487 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 217 # number of cycles access was blocked @@ -840,13 +931,21 @@ system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7615500 system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7615500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7615500 # number of overall MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090196 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090196 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090196 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090196 # mshr miss rate for overall accesses system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12350.278885 # average ReadReq mshr miss latency system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12350.278885 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12350.278885 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 232498 # number of replacements system.cpu0.dcache.tagsinuse 430.308093 # Cycle average of tags in use @@ -906,17 +1005,29 @@ system.cpu0.dcache.demand_accesses::total 9184667 # n system.cpu0.dcache.overall_accesses::cpu0.data 9184667 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 9184667 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.064743 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.064743 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.357635 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.357635 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054115 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054115 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049505 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049505 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.193767 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.193767 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.193767 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.193767 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14069.822629 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14069.822629 # average ReadReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41208.753589 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41208.753589 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11264.994917 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11264.994917 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10776.392038 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10776.392038 # average StoreCondReq miss latency system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36135.430423 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36135.430423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36135.430423 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 3548990 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 1931000 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 344 # number of cycles access was blocked @@ -968,20 +1079,35 @@ system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 843217391 system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10065198391 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10065198391 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030818 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030818 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029328 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029328 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.050038 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.050038 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049461 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049461 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030161 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030161 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.030161 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12858.383693 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12858.383693 # average ReadReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35977.924229 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35977.924229 # average WriteReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8140.422673 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8140.422673 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7779.977304 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7779.977304 # average StoreCondReq mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22761.476527 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22761.476527 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses @@ -1335,11 +1461,17 @@ system.cpu1.icache.demand_accesses::total 10441732 # n system.cpu1.icache.overall_accesses::cpu1.inst 10441732 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::total 10441732 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074367 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.074367 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074367 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.074367 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074367 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.074367 # miss rate for overall accesses system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14668.026995 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14668.026995 # average ReadReq miss latency system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14668.026995 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14668.026995 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14668.026995 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 1572992 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 238 # number of cycles access was blocked @@ -1373,13 +1505,21 @@ system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2572500 system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 2572500 # number of overall MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068483 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.068483 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068483 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.068483 # mshr miss rate for overall accesses system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11895.853716 # average ReadReq mshr miss latency system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.853716 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11895.853716 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 417022 # number of replacements system.cpu1.dcache.tagsinuse 464.475329 # Cycle average of tags in use @@ -1439,17 +1579,29 @@ system.cpu1.dcache.demand_accesses::total 17145866 # n system.cpu1.dcache.overall_accesses::cpu1.data 17145866 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 17145866 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044917 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044917 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.260965 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.260965 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.104573 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.104573 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.081010 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.081010 # miss rate for StoreCondReq accesses system.cpu1.dcache.demand_miss_rate::cpu1.data 0.128275 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.128275 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.128275 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.128275 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15102.598715 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15102.598715 # average ReadReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 33117.439237 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 33117.439237 # average WriteReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12016.421751 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 12016.421751 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8688.894140 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8688.894140 # average StoreCondReq miss latency system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 29243.132109 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29243.132109 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29243.132109 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 15169067 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 5303000 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3226 # number of cycles access was blocked @@ -1503,21 +1655,37 @@ system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41662340533 system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 179841843533 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 179841843533 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025683 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025683 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026828 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026828 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.095692 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.095692 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.080972 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.080972 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026125 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026125 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026125 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12607.262630 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12607.262630 # average ReadReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31279.549610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31279.549610 # average WriteReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8987.345519 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8987.345519 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5687.612293 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5687.612293 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20005.469779 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20005.469779 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -1538,7 +1706,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1308180699879 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308180699879 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1308180699879 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 36058 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index e70ebd6c7..911c40f55 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,6 +12,7 @@ children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview termi atags_addr=256 boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 @@ -19,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 num_work_ids=16 readfile=tests/halt.sh @@ -511,9 +512,8 @@ type=IntrControl sys=system [system.iobus] -type=Bus +type=NoncoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -572,10 +572,9 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] -type=Bus +type=CoherentBus children=badaddr_responder block_size=64 -bus_id=1 clock=1000 header_cycles=1 use_default_range=false @@ -987,9 +986,8 @@ output=true port=3456 [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c9bc70145..c37c93eb0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 10 2012 12:36:36 -gem5 started May 10 2012 12:41:59 -gem5 executing on u200540-lin +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 18:55:16 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 2501685689500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 097a484ee..93f3afbea 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,32 +4,63 @@ sim_seconds 2.501686 # Nu sim_ticks 2501685689500 # Number of ticks simulated final_tick 2501685689500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62639 # Simulator instruction rate (inst/s) -host_op_rate 80877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2630163340 # Simulator tick rate (ticks/s) -host_mem_usage 384244 # Number of bytes of host memory used -host_seconds 951.15 # Real time elapsed on the host +host_inst_rate 57858 # Simulator instruction rate (inst/s) +host_op_rate 74704 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2429415836 # Simulator tick rate (ticks/s) +host_mem_usage 387132 # Number of bytes of host memory used +host_seconds 1029.75 # Real time elapsed on the host sim_insts 59579009 # Number of instructions simulated sim_ops 76926775 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 129658608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1119872 # Number of instructions bytes read from this memory -system.physmem.bytes_written 9585736 # Number of bytes written to this memory -system.physmem.num_reads 14980335 # Number of read requests responded to by this memory -system.physmem.num_writes 856669 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 51828496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 447647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 3831711 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 55660207 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bytes_read 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_written 0 # Number of bytes written to this memory -system.realview.nvmem.num_reads 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_writes 0 # Number of write requests responded to by this memory -system.realview.nvmem.num_other 0 # Number of other requests responded to by this memory -system.realview.nvmem.bw_read 26 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read 26 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 26 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::realview.clcd 118440096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1119872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10085712 # Number of bytes read from this memory +system.physmem.bytes_read::total 129658608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1119872 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6569664 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 9585736 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14805012 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 17498 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 157623 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14980335 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 102651 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 856669 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47344115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 4810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 358 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 447647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 4031566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51828496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 447647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2626095 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205616 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3831711 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2626095 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47344115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 4810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 358 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 447647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5237182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 55660207 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 119797 # number of replacements system.l2c.tagsinuse 26022.811009 # Cycle average of tags in use system.l2c.total_refs 1834134 # Total number of references to valid blocks. @@ -139,32 +170,44 @@ system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001309 system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001119 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.017061 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.data 0.048254 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.023372 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu.data 0.986547 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.986547 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.384615 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.384615 # miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu.data 0.569906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569906 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.dtb.walker 0.001309 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.001119 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.inst 0.017061 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.data 0.247765 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.097332 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.dtb.walker 0.001309 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.001119 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.inst 0.017061 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.data 0.247765 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.097332 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52119.047619 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53714.285714 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.inst 52369.634020 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52246.923879 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52304.833927 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu.data 301.818182 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 301.818182 # average UpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 20800 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 20800 # average SCUpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu.data 52501.618054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52501.618054 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52119.047619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.itb.walker 53714.285714 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52369.634020 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.data 52470.985502 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52460.760337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -241,37 +284,52 @@ system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001302 system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.048038 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.023307 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.986547 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.986547 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.384615 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.384615 # mshr miss rate for SCUpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569906 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.097277 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001302 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001119 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.017048 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.data 0.247631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.097277 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40163.902327 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40096.522468 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40128.887070 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40266.666667 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40266.666667 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40074.434038 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40074.434038 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40063.829787 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41714.285714 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40163.902327 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.data 40077.080170 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40085.715335 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -631,11 +689,17 @@ system.cpu.icache.demand_accesses::total 13709800 # nu system.cpu.icache.overall_accesses::cpu.inst 13709800 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 13709800 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081089 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081089 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.081089 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081089 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.081089 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081089 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14724.903310 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14724.903310 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 14724.903310 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14724.903310 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 2973484 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 393 # number of cycles access was blocked @@ -669,13 +733,21 @@ system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7292000 system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7292000 # number of overall MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.074386 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.074386 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.074386 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.074386 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11950.707952 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11950.707952 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11950.707952 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11950.707952 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 645895 # number of replacements system.cpu.dcache.tagsinuse 511.991565 # Cycle average of tags in use @@ -735,17 +807,29 @@ system.cpu.dcache.demand_accesses::total 25214634 # nu system.cpu.dcache.overall_accesses::cpu.data 25214634 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 25214634 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.049963 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.049963 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289436 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289436 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045848 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045848 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000046 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.147316 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.147316 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.147316 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.147316 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15030.145589 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15030.145589 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37128.139717 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37128.139717 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16297.519459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16297.519459 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 30307.692308 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 30307.692308 # average StoreCondReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 32680.276789 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32680.276789 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 17091437 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 7607500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3024 # number of cycles access was blocked @@ -797,20 +881,35 @@ system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42255772015 system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 189407649515 # number of overall MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025927 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025927 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024333 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024333 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041225 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041225 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000046 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025279 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025279 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025279 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13629.886666 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13629.886666 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35717.776634 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35717.776634 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13402.839576 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13402.839576 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 27038.461538 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 27038.461538 # average StoreCondReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22273.319073 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22273.319073 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use @@ -831,7 +930,9 @@ system.iocache.ReadReq_mshr_uncacheable_latency::total 1296131413558 system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.overall_mshr_uncacheable_latency::total 1296131413558 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 88053 # number of quiesce instructions executed |