diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
11 files changed, 3084 insertions, 3117 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index ea1e9a4d7..7eac6f043 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -577,7 +577,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -638,7 +638,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -1051,7 +1051,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 570320fa8..3620c0fb4 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -10,25 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 5596738500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 -warn: 5604531500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 5613988500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 5652343500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 5668456500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6102531000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 5800930000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 5810491000: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 5849158000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 5865375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6307702500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 53268640500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 53639390500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2455592103500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2467697849500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2487360820500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2487895818500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2493686984500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2494805379500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2494806652500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2456135822500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2468351819500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488200522500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2488780405500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2494975875500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2496192426500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2496193716500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2496816594500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 494cdd6ff..f106f905a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:32:52 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:05:39 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2500827052500 because m5_exit instruction encountered +Exiting @ tick 2502549875500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 655a3d26b..4976e4992 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.500827 # Number of seconds simulated -sim_ticks 2500827052500 # Number of ticks simulated -final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.502550 # Number of seconds simulated +sim_ticks 2502549875500 # Number of ticks simulated +final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76093 # Simulator instruction rate (inst/s) -host_op_rate 98249 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3194009596 # Simulator tick rate (ticks/s) -host_mem_usage 386968 # Number of bytes of host memory used -host_seconds 782.97 # Real time elapsed on the host -sim_insts 59579144 # Number of instructions simulated -sim_ops 76926734 # Number of ops (including micro ops) simulated +host_inst_rate 75474 # Simulator instruction rate (inst/s) +host_op_rate 97450 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3170228022 # Simulator tick rate (ticks/s) +host_mem_usage 386888 # Number of bytes of host memory used +host_seconds 789.39 # Real time elapsed on the host +sim_insts 59578267 # Number of instructions simulated +sim_ops 76925839 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory -system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64425 # number of replacements -system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use -system.l2c.total_refs 2029411 # Total number of references to valid blocks. -system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.replacements 64431 # number of replacements +system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use +system.l2c.total_refs 2028510 # Total number of references to valid blocks. +system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits -system.l2c.Writeback_hits::total 675876 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits -system.l2c.overall_hits::cpu.inst 977061 # number of overall hits -system.l2c.overall_hits::cpu.data 497363 # number of overall hits -system.l2c.overall_hits::total 1608896 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits +system.l2c.Writeback_hits::total 675442 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits +system.l2c.overall_hits::cpu.inst 977935 # number of overall hits +system.l2c.overall_hits::cpu.data 496445 # number of overall hits +system.l2c.overall_hits::total 1608169 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses -system.l2c.demand_misses::total 156375 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses +system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses +system.l2c.demand_misses::total 156364 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12370 # number of overall misses -system.l2c.overall_misses::cpu.data 143952 # number of overall misses -system.l2c.overall_misses::total 156375 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses +system.l2c.overall_misses::cpu.inst 12384 # number of overall misses +system.l2c.overall_misses::cpu.data 143920 # number of overall misses +system.l2c.overall_misses::total 156364 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency +system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59134 # number of writebacks -system.l2c.writebacks::total 59134 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 59159 # number of writebacks +system.l2c.writebacks::total 59159 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -336,26 +332,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15048239 # DTB read hits -system.cpu.checker.dtb.read_misses 7308 # DTB read misses -system.cpu.checker.dtb.write_hits 11293838 # DTB write hits -system.cpu.checker.dtb.write_misses 2191 # DTB write misses +system.cpu.checker.dtb.read_hits 15048164 # DTB read hits +system.cpu.checker.dtb.read_misses 7309 # DTB read misses +system.cpu.checker.dtb.write_hits 11293826 # DTB write hits +system.cpu.checker.dtb.write_misses 2190 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 6416 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 6410 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 179 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 177 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15055547 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11296029 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15055473 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11296016 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26342077 # DTB hits +system.cpu.checker.dtb.hits 26341990 # DTB hits system.cpu.checker.dtb.misses 9499 # DTB misses -system.cpu.checker.dtb.accesses 26351576 # DTB accesses -system.cpu.checker.itb.inst_hits 60745761 # ITB inst hits +system.cpu.checker.dtb.accesses 26351489 # DTB accesses +system.cpu.checker.itb.inst_hits 60744881 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -372,36 +368,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 60750232 # ITB inst accesses -system.cpu.checker.itb.hits 60745761 # DTB hits +system.cpu.checker.itb.inst_accesses 60749352 # ITB inst accesses +system.cpu.checker.itb.hits 60744881 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 60750232 # DTB accesses -system.cpu.checker.numCycles 77205158 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 60749352 # DTB accesses +system.cpu.checker.numCycles 77204260 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51785537 # DTB read hits -system.cpu.dtb.read_misses 81591 # DTB read misses -system.cpu.dtb.write_hits 11872923 # DTB write hits -system.cpu.dtb.write_misses 18231 # DTB write misses +system.cpu.dtb.read_hits 51771660 # DTB read hits +system.cpu.dtb.read_misses 81258 # DTB read misses +system.cpu.dtb.write_hits 11880398 # DTB write hits +system.cpu.dtb.write_misses 17961 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8065 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 8043 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51867128 # DTB read accesses -system.cpu.dtb.write_accesses 11891154 # DTB write accesses +system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51852918 # DTB read accesses +system.cpu.dtb.write_accesses 11898359 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63658460 # DTB hits -system.cpu.dtb.misses 99822 # DTB misses -system.cpu.dtb.accesses 63758282 # DTB accesses -system.cpu.itb.inst_hits 13022422 # ITB inst hits -system.cpu.itb.inst_misses 12153 # ITB inst misses +system.cpu.dtb.hits 63652058 # DTB hits +system.cpu.dtb.misses 99219 # DTB misses +system.cpu.dtb.accesses 63751277 # DTB accesses +system.cpu.itb.inst_hits 13142261 # ITB inst hits +system.cpu.itb.inst_misses 12247 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -410,542 +406,542 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5249 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5262 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13034575 # ITB inst accesses -system.cpu.itb.hits 13022422 # DTB hits -system.cpu.itb.misses 12153 # DTB misses -system.cpu.itb.accesses 13034575 # DTB accesses -system.cpu.numCycles 408047924 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154508 # ITB inst accesses +system.cpu.itb.hits 13142261 # DTB hits +system.cpu.itb.misses 12247 # DTB misses +system.cpu.itb.accesses 13154508 # DTB accesses +system.cpu.numCycles 413642740 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits +system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued -system.cpu.iq.rate 0.305615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued +system.cpu.iq.rate 0.301258 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 254480 # number of nop insts executed -system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed -system.cpu.iew.exec_branches 11392260 # Number of branches executed -system.cpu.iew.exec_stores 12383469 # Number of stores executed -system.cpu.iew.exec_rate 0.298278 # Inst execution rate -system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46962413 # num instructions producing a value -system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value +system.cpu.iew.exec_nop 256054 # number of nop insts executed +system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed +system.cpu.iew.exec_branches 11412736 # Number of branches executed +system.cpu.iew.exec_stores 12391364 # Number of stores executed +system.cpu.iew.exec_rate 0.293583 # Inst execution rate +system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46459932 # num instructions producing a value +system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back +system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729525 # Number of instructions committed -system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59728648 # Number of instructions committed +system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513492 # Number of memory references committed -system.cpu.commit.loads 15715290 # Number of loads committed -system.cpu.commit.membars 413064 # Number of memory barriers committed -system.cpu.commit.branches 9904425 # Number of branches committed +system.cpu.commit.refs 27513345 # Number of memory references committed +system.cpu.commit.loads 15715170 # Number of loads committed +system.cpu.commit.membars 413057 # Number of memory barriers committed +system.cpu.commit.branches 9904308 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. -system.cpu.commit.function_calls 995959 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. +system.cpu.commit.function_calls 995953 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240802540 # The number of ROB reads -system.cpu.rob.rob_writes 206662154 # The number of ROB writes -system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579144 # Number of Instructions Simulated -system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated -system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 552215112 # number of integer regfile reads -system.cpu.int_regfile_writes 88113132 # number of integer regfile writes -system.cpu.fp_regfile_reads 8314 # number of floating regfile reads -system.cpu.fp_regfile_writes 2878 # number of floating regfile writes -system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads -system.cpu.misc_regfile_writes 912736 # number of misc regfile writes -system.cpu.icache.replacements 990445 # number of replacements -system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use -system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits -system.cpu.icache.overall_hits::total 11943122 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses -system.cpu.icache.overall_misses::total 1075156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked +system.cpu.rob.rob_reads 246021016 # The number of ROB reads +system.cpu.rob.rob_writes 206855771 # The number of ROB writes +system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59578267 # Number of Instructions Simulated +system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated +system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 551124725 # number of integer regfile reads +system.cpu.int_regfile_writes 87730819 # number of integer regfile writes +system.cpu.fp_regfile_reads 8186 # number of floating regfile reads +system.cpu.fp_regfile_writes 2858 # number of floating regfile writes +system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads +system.cpu.misc_regfile_writes 912697 # number of misc regfile writes +system.cpu.icache.replacements 991190 # number of replacements +system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use +system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits +system.cpu.icache.overall_hits::total 12061455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses +system.cpu.icache.overall_misses::total 1076423 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67776 # number of writebacks -system.cpu.icache.writebacks::total 67776 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67899 # number of writebacks +system.cpu.icache.writebacks::total 67899 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644124 # number of replacements -system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use -system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits -system.cpu.dcache.overall_hits::total 21203803 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses -system.cpu.dcache.overall_misses::total 3698116 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 643139 # number of replacements +system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use +system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits +system.cpu.dcache.overall_hits::total 21161261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses +system.cpu.dcache.overall_misses::total 3758563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks -system.cpu.dcache.writebacks::total 608100 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks +system.cpu.dcache.writebacks::total 607543 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -967,16 +963,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 8259e7988..8ee00f929 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -960,7 +960,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -1021,7 +1021,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -1434,7 +1434,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index c3484784a..6f1b9eba3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -14,7 +14,6 @@ warn: Returning thumbEE disabled for now since we don't support CP14config regis warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 02c5cc88a..fe27005da 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:33:16 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:16:08 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2569716290500 because m5_exit instruction encountered +Exiting @ tick 2581527583500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 038e4aa5b..ba015b214 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,75 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.569716 # Number of seconds simulated -sim_ticks 2569716290500 # Number of ticks simulated -final_tick 2569716290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.581528 # Number of seconds simulated +sim_ticks 2581527583500 # Number of ticks simulated +final_tick 2581527583500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91215 # Simulator instruction rate (inst/s) -host_op_rate 117813 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3779331614 # Simulator tick rate (ticks/s) -host_mem_usage 391064 # Number of bytes of host memory used -host_seconds 679.94 # Real time elapsed on the host -sim_insts 62020337 # Number of instructions simulated -sim_ops 80105642 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 383040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4310004 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 438272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5311600 # Number of bytes read from this memory -system.physmem.bytes_read::total 129982372 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 383040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 438272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 821312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4277376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7306512 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 5985 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67416 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 83020 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15105505 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66834 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824118 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46517845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 149059 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1677230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 170553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2066999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50582382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 149059 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 170553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319612 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1664532 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6616 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1172167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2843315 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1664532 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46517845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 149059 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1683845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 170553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3239165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53425697 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 89313 # Simulator instruction rate (inst/s) +host_op_rate 115365 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3717496726 # Simulator tick rate (ticks/s) +host_mem_usage 390980 # Number of bytes of host memory used +host_seconds 694.43 # Real time elapsed on the host +sim_insts 62021206 # Number of instructions simulated +sim_ops 80112751 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 320 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 384 # Number of bytes read from this memory @@ -80,259 +21,300 @@ system.realview.nvmem.num_reads::cpu0.inst 1 # system.realview.nvmem.num_reads::cpu1.inst 5 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 125 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 124 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::total 149 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 125 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 124 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::total 149 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 125 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 124 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 149 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72902 # number of replacements -system.l2c.tagsinuse 52914.655952 # Cycle average of tags in use -system.l2c.total_refs 2024041 # Total number of references to valid blocks. -system.l2c.sampled_refs 138037 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.663032 # Average number of references to valid blocks. +system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 395008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4372084 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5226480 # Number of bytes read from this memory +system.physmem.bytes_read::total 129958756 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 395008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 820544 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244480 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7273616 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6172 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68386 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81690 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15105136 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66320 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46305011 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 223 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 153013 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1693603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 164839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2024569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50341804 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 153013 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 164839 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1644174 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6585 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1166804 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2817563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1644174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46305011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 223 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 153013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1700189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 164839 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3191372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53159367 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72536 # number of replacements +system.l2c.tagsinuse 53024.626088 # Cycle average of tags in use +system.l2c.total_refs 2019266 # Total number of references to valid blocks. +system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.660834 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37560.940783 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.394478 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000176 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4213.394018 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2969.636370 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.170115 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.970249 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4028.311406 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4125.838357 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.573134 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000052 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37701.415204 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.259804 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000179 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4215.968317 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2959.624437 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 13.637835 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4028.150256 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4102.570055 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.575278 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000050 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064291 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045313 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000186 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061467 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062955 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.807414 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 50859 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5940 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 395141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 161674 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 79156 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 619717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202375 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1521452 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 646021 # number of Writeback hits -system.l2c.Writeback_hits::total 646021 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 861 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1085 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1946 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 209 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 373 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 50919 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 55813 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106732 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 50859 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5940 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 395141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 212593 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 79156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 619717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 258188 # number of demand (read+write) hits -system.l2c.demand_hits::total 1628184 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 50859 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5940 # number of overall hits -system.l2c.overall_hits::cpu0.inst 395141 # number of overall hits -system.l2c.overall_hits::cpu0.data 212593 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 79156 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6590 # number of overall hits -system.l2c.overall_hits::cpu1.inst 619717 # number of overall hits -system.l2c.overall_hits::cpu1.data 258188 # number of overall hits -system.l2c.overall_hits::total 1628184 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.064331 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.045160 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000208 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.061465 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.062600 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.809092 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 53338 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 6106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 398719 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 164464 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 78886 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6452 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 615129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 199702 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1522796 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 645710 # number of Writeback hits +system.l2c.Writeback_hits::total 645710 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1043 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 806 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1849 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 213 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 356 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48030 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 59189 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107219 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 53338 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 6106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 398719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 212494 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 78886 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 6452 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 615129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 258891 # number of demand (read+write) hits +system.l2c.demand_hits::total 1630015 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 53338 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 6106 # number of overall hits +system.l2c.overall_hits::cpu0.inst 398719 # number of overall hits +system.l2c.overall_hits::cpu0.data 212494 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 78886 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 6452 # number of overall hits +system.l2c.overall_hits::cpu1.inst 615129 # number of overall hits +system.l2c.overall_hits::cpu1.data 258891 # number of overall hits +system.l2c.overall_hits::total 1630015 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 5853 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6139 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6809 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6537 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25366 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5294 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4767 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10061 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 775 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 577 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1352 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62637 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77700 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140337 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 6044 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6302 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6609 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6328 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25314 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5683 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 4287 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 9970 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 777 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1366 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76572 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140023 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 5853 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 68776 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6809 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 84237 # number of demand (read+write) misses -system.l2c.demand_misses::total 165703 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses +system.l2c.demand_misses::cpu0.inst 6044 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69753 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6609 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 82900 # number of demand (read+write) misses +system.l2c.demand_misses::total 165337 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 5853 # number of overall misses -system.l2c.overall_misses::cpu0.data 68776 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6809 # number of overall misses -system.l2c.overall_misses::cpu1.data 84237 # number of overall misses -system.l2c.overall_misses::total 165703 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 521500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 53000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 306091000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 320158000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 783000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 356464000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 341134500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1325309000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 18664500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 31259000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 49923500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1307000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6272500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 7579500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3285106999 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4081053500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7366160499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 521500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 53000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 306091000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3605264999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 783000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 104000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 356464000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4422188000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8691469499 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 521500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 53000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 306091000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3605264999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 783000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 104000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 356464000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4422188000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8691469499 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 50869 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5941 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 400994 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 167813 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 79171 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6592 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 626526 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 208912 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1546818 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 646021 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 646021 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6155 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5852 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 12007 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 984 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 741 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1725 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 113556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 133513 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247069 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 50869 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5941 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 400994 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 281369 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 79171 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6592 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 626526 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 342425 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1793887 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 50869 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5941 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 400994 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 281369 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 79171 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6592 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 626526 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 342425 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1793887 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000168 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014596 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036582 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000303 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010868 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.031291 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016399 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.860114 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.814593 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.837928 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.787602 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.778677 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.783768 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.551596 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.581966 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.568007 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000168 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014596 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244433 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010868 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.246001 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.092371 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000197 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000168 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014596 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244433 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000189 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010868 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.246001 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.092371 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 53000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52296.429182 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52151.490471 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52200 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52351.887208 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52185.176687 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52247.457226 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3525.595013 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6557.373610 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4962.081304 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1686.451613 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10870.883882 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 5606.139053 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52446.748711 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52523.211068 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52489.083413 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52452.095007 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52296.429182 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52420.393727 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52200 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52351.887208 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52496.978762 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52452.095007 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 6044 # number of overall misses +system.l2c.overall_misses::cpu0.data 69753 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6609 # number of overall misses +system.l2c.overall_misses::cpu1.data 82900 # number of overall misses +system.l2c.overall_misses::total 165337 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 471000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 60000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 322261499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 330895497 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1101000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 351559997 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 332583499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1338932492 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 20202500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27410499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47612999 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1721500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7138500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 8860000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3379920986 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4071556980 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7451477966 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 471000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 60000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 322261499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3710816483 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1101000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 351559997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4404140479 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8790410458 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 471000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 60000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 322261499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3710816483 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1101000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 351559997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4404140479 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8790410458 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 53347 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6107 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 404763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 170766 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 78907 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6452 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 621738 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 206030 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1548110 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 645710 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 645710 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6726 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 5093 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 11819 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 990 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 732 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1722 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111481 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135761 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247242 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 53347 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 404763 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 282247 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 78907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6452 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 621738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 341791 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1795352 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 53347 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 404763 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 282247 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 78907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6452 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 621738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 341791 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1795352 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000164 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014932 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036904 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016352 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.844930 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.841744 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.843557 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.784848 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.804645 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.793264 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569164 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.564021 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566340 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000164 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014932 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.247135 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.242546 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.092092 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000169 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000164 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014932 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.247135 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000266 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.242546 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.092092 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 60000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53319.242058 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52506.426055 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53194.128764 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52557.442952 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52892.964052 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3554.900581 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6393.864941 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 4775.626780 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2215.572716 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 12119.694397 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 6486.090776 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53268.206742 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53172.921956 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53216.099969 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53166.626091 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52333.333333 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 60000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53319.242058 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53199.381862 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52428.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53194.128764 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53125.940639 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53166.626091 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -341,180 +323,170 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66834 # number of writebacks -system.l2c.writebacks::total 66834 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 25 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 25 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 66320 # number of writebacks +system.l2c.writebacks::total 66320 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 39 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 40 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 23 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 25 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 40 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 23 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 5849 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6101 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6803 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6512 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25293 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5294 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4767 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10061 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 775 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 577 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1352 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 62637 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77700 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140337 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6039 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6263 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6604 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6305 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25242 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5683 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 4287 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 9970 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 777 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1366 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63450 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76572 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140022 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 5849 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 68738 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6803 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 84212 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165630 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6039 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69713 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6604 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 82877 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165264 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 5849 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 68738 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6803 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 84212 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165630 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 41000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 234434500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 244221500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 601000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 273121500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 260689500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1013589000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 211949500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190864500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 402814000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31033000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23118500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 54151500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2507451999 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3115007000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5622458999 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 41000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 234434500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2751673499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 601000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 273121500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3375696500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6636047999 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 41000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 234434500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2751673499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 601000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 273121500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3375696500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6636047999 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5501500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 21616744000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2009500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 110336260000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131960515000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 713445484 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31812115712 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32525561196 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5501500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 22330189484 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2009500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 142148375712 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164486076196 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036356 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031171 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016352 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.860114 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814593 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.837928 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.787602 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.778677 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.783768 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.551596 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581966 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.568007 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.092330 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000197 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000168 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014586 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244298 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000189 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000303 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010858 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.245928 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.092330 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses::cpu0.inst 6039 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69713 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6604 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82877 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165264 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 48000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 248302999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253032000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 846000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270719997 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 254713500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1028022496 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 227576000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 171718000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 399294000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31112500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23586500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 54699000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2608560498 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3134816489 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5743376987 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 48000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 248302999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2861592498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 846000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 270719997 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3389529989 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6771399483 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 48000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 248302999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2861592498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 846000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 270719997 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3389529989 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6771399483 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5579000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 9186859000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2133500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 122397706500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131592278000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 704572999 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 30781654107 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31486227106 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5579000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9891431999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2133500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 153179360607 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163078505106 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036676 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030602 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016305 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.844930 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.841744 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.843557 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.784848 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.804645 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.793264 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569155 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.564021 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566336 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.092051 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000169 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014920 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000266 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010622 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242479 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.092051 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40029.749221 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40032.171376 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40073.893963 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40035.795240 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.703587 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40037.173243 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40042.580645 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.724437 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40052.884615 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40031.482973 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40090.180180 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40063.981694 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40401.085742 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40398.651864 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40726.665716 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40045.046630 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40055.516678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40049.548646 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40041.827542 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40044.991511 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40043.191801 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41112.064586 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40939.462062 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41017.675701 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 41000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40081.124979 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40031.329090 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40066.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.214464 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40085.694438 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40065.495375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41116.575426 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41048.190409 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40285.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40993.336917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40898.319063 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40973.227581 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +509,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12222008 # DTB read hits -system.cpu0.dtb.read_misses 34799 # DTB read misses -system.cpu0.dtb.write_hits 5155654 # DTB write hits -system.cpu0.dtb.write_misses 4970 # DTB write misses +system.cpu0.dtb.read_hits 9084255 # DTB read hits +system.cpu0.dtb.read_misses 36769 # DTB read misses +system.cpu0.dtb.write_hits 5284576 # DTB write hits +system.cpu0.dtb.write_misses 6773 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2546 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1270 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 369 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2261 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1412 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 383 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 661 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12256807 # DTB read accesses -system.cpu0.dtb.write_accesses 5160624 # DTB write accesses +system.cpu0.dtb.perms_faults 588 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9121024 # DTB read accesses +system.cpu0.dtb.write_accesses 5291349 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 17377662 # DTB hits -system.cpu0.dtb.misses 39769 # DTB misses -system.cpu0.dtb.accesses 17417431 # DTB accesses -system.cpu0.itb.inst_hits 4312814 # ITB inst hits -system.cpu0.itb.inst_misses 5659 # ITB inst misses +system.cpu0.dtb.hits 14368831 # DTB hits +system.cpu0.dtb.misses 43542 # DTB misses +system.cpu0.dtb.accesses 14412373 # DTB accesses +system.cpu0.itb.inst_hits 4421795 # ITB inst hits +system.cpu0.itb.inst_misses 5958 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,542 +538,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1615 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1415 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1550 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1713 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4318473 # ITB inst accesses -system.cpu0.itb.hits 4312814 # DTB hits -system.cpu0.itb.misses 5659 # DTB misses -system.cpu0.itb.accesses 4318473 # DTB accesses -system.cpu0.numCycles 91755333 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4427753 # ITB inst accesses +system.cpu0.itb.hits 4421795 # DTB hits +system.cpu0.itb.misses 5958 # DTB misses +system.cpu0.itb.accesses 4427753 # DTB accesses +system.cpu0.numCycles 66112093 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5952266 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4505075 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 304047 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3800923 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2764349 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6172143 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4680207 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 316413 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3902841 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2861272 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 686219 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 29965 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12225669 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31634782 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5952266 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3450568 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7438203 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1498517 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 86111 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 25429329 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 56004 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 89121 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 253 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4310960 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 168036 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2895 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 46396814 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.887686 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.274992 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 700420 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 30889 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12972431 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32579396 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6172143 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3561692 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7636967 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1568394 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 92289 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21876805 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5742 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 73340 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 91549 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 175 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4419869 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 175391 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2999 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 43870869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.963501 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.353712 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 38966492 83.99% 83.99% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 608768 1.31% 85.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 793531 1.71% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 678621 1.46% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 615872 1.33% 89.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 550838 1.19% 90.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680018 1.47% 92.45% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 365085 0.79% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3137589 6.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 36242473 82.61% 82.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 623814 1.42% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 820212 1.87% 85.90% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 686089 1.56% 87.47% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 622737 1.42% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 578948 1.32% 90.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 720296 1.64% 91.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 370745 0.85% 92.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3205555 7.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 46396814 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.064871 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.344773 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12690058 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 25456221 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6703467 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 545759 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1001309 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 958631 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 66338 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39766150 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 219028 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1001309 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13289637 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7972865 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15343248 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6631332 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2158423 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38589176 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 848 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 416461 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1242307 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 38596643 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175113710 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175069465 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 44245 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30775876 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 7820767 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 452714 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 409285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5195885 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7781233 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5757511 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1120127 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1192401 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36577178 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 791583 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 40176979 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 83237 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5967561 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13599049 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 145097 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 46396814 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.865943 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.513269 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 43870869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.093359 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.492790 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13461534 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21912526 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6836712 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 603785 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1056312 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 995110 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 66550 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40827533 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 217718 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1056312 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14066817 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6153021 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13456769 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6788701 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2349249 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39593607 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1040 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 472233 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1335984 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 103 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39791095 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179675714 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179640853 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34861 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31537071 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8254023 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 463697 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 419128 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5673165 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7928571 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5881726 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1132931 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1238845 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37538443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 794373 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37739879 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 92690 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6264606 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14354053 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 137507 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 43870869 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.860249 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.478315 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 30520128 65.78% 65.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5937185 12.80% 78.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3046653 6.57% 85.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2264959 4.88% 90.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2893477 6.24% 96.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 928258 2.00% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 563400 1.21% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 186019 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 56735 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 28164784 64.20% 64.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6326126 14.42% 78.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3234526 7.37% 85.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2361316 5.38% 91.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2098246 4.78% 96.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 936106 2.13% 98.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 514694 1.17% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 181493 0.41% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53578 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 46396814 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 43870869 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 26385 1.46% 1.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.03% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 1567613 86.92% 88.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 209022 11.59% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27565 2.58% 2.58% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 466 0.04% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.62% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 837939 78.44% 81.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202337 18.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 25309 0.06% 0.06% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 21935197 54.60% 54.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48039 0.12% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 8 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 725 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 12687286 31.58% 86.36% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5480393 13.64% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 20407 0.05% 0.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22494595 59.60% 59.66% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50051 0.13% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9563453 25.34% 85.13% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5610668 14.87% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 40176979 # Type of FU issued -system.cpu0.iq.rate 0.437871 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1803473 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.044888 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 128665759 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43343315 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34031138 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11205 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6096 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4927 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 41949154 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5989 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 311358 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37739879 # Type of FU issued +system.cpu0.iq.rate 0.570847 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1068307 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028307 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 120546534 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44606042 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34820056 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8333 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4740 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3893 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38783456 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4323 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 326383 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1414489 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4027 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13694 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 607908 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1507630 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4080 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13930 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 608245 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 5397304 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5188 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149509 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5404 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1001309 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 6077720 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 124694 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37485087 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 95046 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7781233 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5757511 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 467034 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 52649 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 4313 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13694 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 153875 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 138964 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 292839 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 39778235 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 12530314 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 398744 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1056312 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4064319 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 129740 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38471177 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 88757 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7928571 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5881726 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 461616 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49674 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17745 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13930 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 159357 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 144737 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 304094 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37337331 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9402148 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 402548 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 116326 # number of nop insts executed -system.cpu0.iew.exec_refs 17957262 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4780864 # Number of branches executed -system.cpu0.iew.exec_stores 5426948 # Number of stores executed -system.cpu0.iew.exec_rate 0.433525 # Inst execution rate -system.cpu0.iew.wb_sent 39572300 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34036065 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18213937 # num instructions producing a value -system.cpu0.iew.wb_consumers 35297892 # num instructions consuming a value +system.cpu0.iew.exec_nop 138361 # number of nop insts executed +system.cpu0.iew.exec_refs 14958639 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4921687 # Number of branches executed +system.cpu0.iew.exec_stores 5556491 # Number of stores executed +system.cpu0.iew.exec_rate 0.564758 # Inst execution rate +system.cpu0.iew.wb_sent 37117116 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34823949 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18360594 # num instructions producing a value +system.cpu0.iew.wb_consumers 34980725 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.370944 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.516006 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.526741 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524877 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 23601687 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 31186721 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 6143896 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 646486 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 256571 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 45430638 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686469 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.654503 # Number of insts commited each cycle +system.cpu0.commit.commitCommittedInsts 24134633 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 31866160 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 6466683 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 656866 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 267750 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 42850944 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.743651 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.697776 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33717084 74.22% 74.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5850006 12.88% 87.09% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1884843 4.15% 91.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 960822 2.11% 93.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 731888 1.61% 94.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 454898 1.00% 95.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 476885 1.05% 97.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 212485 0.47% 97.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1141727 2.51% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 30739496 71.74% 71.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6075340 14.18% 85.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1944692 4.54% 90.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1041937 2.43% 92.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 773699 1.81% 94.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 503770 1.18% 95.86% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 405337 0.95% 96.81% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 203427 0.47% 97.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1163246 2.71% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 45430638 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23601687 # Number of instructions committed -system.cpu0.commit.committedOps 31186721 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 42850944 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24134633 # Number of instructions committed +system.cpu0.commit.committedOps 31866160 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11516347 # Number of memory references committed -system.cpu0.commit.loads 6366744 # Number of loads committed -system.cpu0.commit.membars 228774 # Number of memory barriers committed -system.cpu0.commit.branches 4268909 # Number of branches committed -system.cpu0.commit.fp_insts 4838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27636133 # Number of committed integer instructions. -system.cpu0.commit.function_calls 492618 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1141727 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11694422 # Number of memory references committed +system.cpu0.commit.loads 6420941 # Number of loads committed +system.cpu0.commit.membars 234529 # Number of memory barriers committed +system.cpu0.commit.branches 4382702 # Number of branches committed +system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 28193395 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499856 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1163246 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 80832744 # The number of ROB reads -system.cpu0.rob.rob_writes 75665562 # The number of ROB writes -system.cpu0.timesIdled 511317 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 45358519 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5047039822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23536584 # Number of Instructions Simulated -system.cpu0.committedOps 31121618 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23536584 # Number of Instructions Simulated -system.cpu0.cpi 3.898413 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.898413 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.256515 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.256515 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 183926116 # number of integer regfile reads -system.cpu0.int_regfile_writes 33429350 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4511 # number of floating regfile reads -system.cpu0.fp_regfile_writes 934 # number of floating regfile writes -system.cpu0.misc_regfile_reads 45525801 # number of misc regfile reads -system.cpu0.misc_regfile_writes 515221 # number of misc regfile writes -system.cpu0.icache.replacements 402234 # number of replacements -system.cpu0.icache.tagsinuse 511.630403 # Cycle average of tags in use -system.cpu0.icache.total_refs 3875529 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 402746 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.622762 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6260006000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.630403 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999278 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999278 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3875529 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3875529 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3875529 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3875529 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3875529 # number of overall hits -system.cpu0.icache.overall_hits::total 3875529 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 435289 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 435289 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 435289 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 435289 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 435289 # number of overall misses -system.cpu0.icache.overall_misses::total 435289 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6419795491 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6419795491 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6419795491 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6419795491 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6419795491 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6419795491 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4310818 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4310818 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4310818 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4310818 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4310818 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4310818 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100976 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100976 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100976 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100976 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100976 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100976 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14748.352223 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14748.352223 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14748.352223 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14748.352223 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14748.352223 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1456992 # number of cycles access was blocked +system.cpu0.rob.rob_reads 79207972 # The number of ROB reads +system.cpu0.rob.rob_writes 77724528 # The number of ROB writes +system.cpu0.timesIdled 427936 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22241224 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5096899290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24053891 # Number of Instructions Simulated +system.cpu0.committedOps 31785418 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24053891 # Number of Instructions Simulated +system.cpu0.cpi 2.748499 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.748499 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.363835 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.363835 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 174526329 # number of integer regfile reads +system.cpu0.int_regfile_writes 34331240 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3280 # number of floating regfile reads +system.cpu0.fp_regfile_writes 898 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46875879 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527497 # number of misc regfile writes +system.cpu0.icache.replacements 406974 # number of replacements +system.cpu0.icache.tagsinuse 511.614338 # Cycle average of tags in use +system.cpu0.icache.total_refs 3978434 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 407486 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.763364 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6469268000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.614338 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999247 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999247 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3978434 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3978434 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3978434 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3978434 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3978434 # number of overall hits +system.cpu0.icache.overall_hits::total 3978434 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 441298 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 441298 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 441298 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 441298 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 441298 # number of overall misses +system.cpu0.icache.overall_misses::total 441298 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7186656997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7186656997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7186656997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7186656997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7186656997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7186656997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4419732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4419732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4419732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4419732 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4419732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4419732 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099847 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099847 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099847 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099847 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099847 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099847 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16285.269811 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16285.269811 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16285.269811 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16285.269811 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16285.269811 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1454497 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 171 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8938.601227 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8505.830409 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 31582 # number of writebacks -system.cpu0.icache.writebacks::total 31582 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 32527 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 32527 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 32527 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 32527 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 32527 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 32527 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 402762 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 402762 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 402762 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 402762 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 402762 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 402762 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4809385492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4809385492 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4809385492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4809385492 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4809385492 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4809385492 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7376000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7376000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7376000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7376000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093431 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093431 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093431 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093431 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11941.011049 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11941.011049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11941.011049 # average overall mshr miss latency +system.cpu0.icache.writebacks::writebacks 29234 # number of writebacks +system.cpu0.icache.writebacks::total 29234 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33802 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33802 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33802 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33802 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33802 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33802 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 407496 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 407496 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 407496 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 407496 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 407496 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 407496 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5527499503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5527499503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5527499503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5527499503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5527499503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8379000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8379000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8379000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092199 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092199 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092199 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092199 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13564.549107 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13564.549107 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13564.549107 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 272390 # number of replacements -system.cpu0.dcache.tagsinuse 477.646995 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9259935 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 272772 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.947528 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 49645000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 477.646995 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.932904 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.932904 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5751664 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5751664 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3128629 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3128629 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172667 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 172667 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 169954 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 169954 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8880293 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8880293 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8880293 # number of overall hits -system.cpu0.dcache.overall_hits::total 8880293 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 380393 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 380393 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1568163 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1568163 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9112 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9112 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7881 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7881 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1948556 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1948556 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1948556 # number of overall misses -system.cpu0.dcache.overall_misses::total 1948556 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5112833000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5112833000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 57745298395 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 57745298395 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100839000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 100839000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 84292000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 84292000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 62858131395 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 62858131395 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 62858131395 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 62858131395 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6132057 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6132057 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4696792 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4696792 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 181779 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 181779 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 177835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 177835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10828849 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10828849 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10828849 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10828849 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062034 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062034 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333880 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333880 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.050127 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.050127 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.044316 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.044316 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179941 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.179941 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179941 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.179941 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13440.922940 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13440.922940 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 36823.530714 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 36823.530714 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11066.615452 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11066.615452 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 10695.597005 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10695.597005 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32258.827252 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32258.827252 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32258.827252 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3762493 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1470000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 438 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 79 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8590.166667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18607.594937 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275761 # number of replacements +system.cpu0.dcache.tagsinuse 476.305820 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9551525 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276273 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.572778 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 51448000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 476.305820 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.930285 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.930285 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5934693 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5934693 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3224707 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3224707 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174478 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174478 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171499 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171499 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9159400 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9159400 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9159400 # number of overall hits +system.cpu0.dcache.overall_hits::total 9159400 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 401255 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 401255 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1594245 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1594245 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9007 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9007 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7794 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7794 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1995500 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1995500 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1995500 # number of overall misses +system.cpu0.dcache.overall_misses::total 1995500 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7289566500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7289566500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71816395371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71816395371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114642500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 114642500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 93715000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 93715000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 79105961871 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 79105961871 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 79105961871 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 79105961871 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6335948 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6335948 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818952 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4818952 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183485 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183485 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179293 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179293 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11154900 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11154900 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11154900 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11154900 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063330 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063330 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330828 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330828 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.049088 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043471 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043471 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178890 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178890 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178890 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178890 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18166.917546 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18166.917546 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45047.276530 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45047.276530 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12728.155879 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12728.155879 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 12023.992815 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12023.992815 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39642.175831 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39642.175831 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 39642.175831 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7140493 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1629000 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1441 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 89 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4955.234559 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18303.370787 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 253456 # number of writebacks -system.cpu0.dcache.writebacks::total 253456 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195063 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 195063 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1436472 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1436472 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 621 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 621 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1631535 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1631535 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1631535 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1631535 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 185330 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 185330 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131691 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131691 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8491 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8491 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7877 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7877 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 317021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 317021 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 317021 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 317021 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2232196000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2232196000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4281157492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4281157492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67651500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67651500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 60619000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 60619000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6513353492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6513353492 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6513353492 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6513353492 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 24166586500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 24166586500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 850308391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 850308391 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 25016894891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 25016894891 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030223 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030223 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028038 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028038 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046711 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046711 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.044294 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029276 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029276 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029276 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12044.439648 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12044.439648 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32509.112179 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32509.112179 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7967.436109 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7967.436109 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7695.696331 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7695.696331 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20545.495384 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20545.495384 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255942 # number of writebacks +system.cpu0.dcache.writebacks::total 255942 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211815 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 211815 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1463184 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1463184 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 509 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 509 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1674999 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1674999 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1674999 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1674999 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189440 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189440 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131061 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131061 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8498 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7791 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7791 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320501 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320501 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320501 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2806583905 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2806583905 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4685193022 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4685193022 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 80265007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 80265007 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 69214057 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 69214057 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7491776927 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7491776927 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7491776927 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7491776927 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10315161000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10315161000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 849550399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 849550399 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11164711399 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11164711399 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029899 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029899 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046314 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046314 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043454 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043454 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028732 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028732 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028732 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14815.159971 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14815.159971 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35748.186127 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35748.186127 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9445.164392 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9445.164392 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8883.847645 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8883.847645 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23375.206090 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23375.206090 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1111,27 +1083,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 40314372 # DTB read hits -system.cpu1.dtb.read_misses 47835 # DTB read misses -system.cpu1.dtb.write_hits 7207214 # DTB write hits -system.cpu1.dtb.write_misses 14308 # DTB write misses +system.cpu1.dtb.read_hits 43446349 # DTB read hits +system.cpu1.dtb.read_misses 46684 # DTB read misses +system.cpu1.dtb.write_hits 7088138 # DTB write hits +system.cpu1.dtb.write_misses 12274 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2204 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3789 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 426 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2545 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3731 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 361 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 618 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 40362207 # DTB read accesses -system.cpu1.dtb.write_accesses 7221522 # DTB write accesses +system.cpu1.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43493033 # DTB read accesses +system.cpu1.dtb.write_accesses 7100412 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 47521586 # DTB hits -system.cpu1.dtb.misses 62143 # DTB misses -system.cpu1.dtb.accesses 47583729 # DTB accesses -system.cpu1.itb.inst_hits 9199147 # ITB inst hits -system.cpu1.itb.inst_misses 6537 # ITB inst misses +system.cpu1.dtb.hits 50534487 # DTB hits +system.cpu1.dtb.misses 58958 # DTB misses +system.cpu1.dtb.accesses 50593445 # DTB accesses +system.cpu1.itb.inst_hits 9221438 # ITB inst hits +system.cpu1.itb.inst_misses 6034 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1140,542 +1112,546 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1398 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1610 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1778 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1730 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9205684 # ITB inst accesses -system.cpu1.itb.hits 9199147 # DTB hits -system.cpu1.itb.misses 6537 # DTB misses -system.cpu1.itb.accesses 9205684 # DTB accesses -system.cpu1.numCycles 321589455 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9227472 # ITB inst accesses +system.cpu1.itb.hits 9221438 # DTB hits +system.cpu1.itb.misses 6034 # DTB misses +system.cpu1.itb.accesses 9227472 # DTB accesses +system.cpu1.numCycles 353824423 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9609219 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7804241 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 456907 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6466725 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5325877 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9470897 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7703385 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 447489 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6420671 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5281203 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 844527 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 50619 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 21504333 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71435147 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9609219 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6170404 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15136389 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4734420 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 89053 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 66067639 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5715 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 64771 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 143196 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 87 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9197098 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 766779 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3914 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 106241109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.815152 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.196213 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 834152 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 50449 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22167103 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 70445168 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9470897 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6115355 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14956565 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4597208 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88094 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 73687570 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 6011 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 61739 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 141755 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9219303 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 857673 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3541 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114241434 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.747913 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.114106 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 91113370 85.76% 85.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 835957 0.79% 86.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1038807 0.98% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2054123 1.93% 89.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1283354 1.21% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 639035 0.60% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2277082 2.14% 93.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 459375 0.43% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6540006 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99293168 86.92% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 828706 0.73% 87.64% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1015866 0.89% 88.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2054648 1.80% 90.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1280264 1.12% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 613123 0.54% 91.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2273093 1.99% 93.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 467514 0.41% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6415052 5.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 106241109 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029880 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.222131 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23013271 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 65947642 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13617278 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 534194 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3128724 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1272359 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 103085 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80569967 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 342001 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3128724 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 24438096 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 29197230 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 32706540 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12706787 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4063732 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74758294 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2356 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 627503 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2908939 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 45012 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79187879 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 346602336 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 346555262 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 47074 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50022423 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 29165455 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 496148 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 429704 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7532124 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14054260 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8745175 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1095062 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1520090 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67170682 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 857343 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 88258087 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 108704 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18559774 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53338169 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 154632 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 106241109 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.830734 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.556038 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114241434 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.026767 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.199096 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23740446 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 73499308 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13432186 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 537783 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3031711 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1242419 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102480 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 79700896 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 342426 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3031711 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25267828 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33699109 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 35312301 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12394168 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4536317 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 73261010 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3244 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 714923 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3281779 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33706 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 77426546 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 339504965 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 339445449 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59516 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49265102 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28161444 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 486276 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 420659 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8155263 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14019935 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8605996 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1069297 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1521896 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 66318588 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 855610 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90596015 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 108958 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18341957 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53651445 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 163223 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114241434 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.793022 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.525613 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 76008182 71.54% 71.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8446540 7.95% 79.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4482838 4.22% 83.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3826420 3.60% 87.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 9985833 9.40% 96.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1963466 1.85% 98.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1174590 1.11% 99.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 267511 0.25% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 85729 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83094748 72.74% 72.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8828314 7.73% 80.46% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4518450 3.96% 84.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3737052 3.27% 87.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10664138 9.33% 97.02% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1972512 1.73% 98.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1063413 0.93% 99.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282401 0.25% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 80406 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 106241109 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114241434 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 34820 0.48% 0.48% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 995 0.01% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 6868408 95.11% 95.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 317335 4.39% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29108 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 993 0.01% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7574349 95.84% 96.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 298565 3.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 81809 0.09% 0.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39074007 44.27% 44.37% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 63191 0.07% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 5 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1634 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 41444924 46.96% 91.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7592491 8.60% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 86745 0.10% 0.10% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38337785 42.32% 42.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61539 0.07% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 4 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1698 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44639306 49.27% 91.76% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7468915 8.24% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 88258087 # Type of FU issued -system.cpu1.iq.rate 0.274443 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7221558 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.081823 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 290137702 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 86602000 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55480726 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11865 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6384 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5360 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95391603 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6233 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 377691 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90596015 # Type of FU issued +system.cpu1.iq.rate 0.256048 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7903015 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.087234 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 303489486 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 85529327 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54443530 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14763 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8091 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6830 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 98404572 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7713 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 368848 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4014151 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 6631 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 21303 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1605227 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4030694 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6909 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 21919 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1587988 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 28717238 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1149940 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965710 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1045299 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3128724 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 22478642 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 328290 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68173106 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 141945 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14054260 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8745175 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 539434 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 62530 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3755 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 21303 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 237741 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 202628 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 440369 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85609132 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 40707747 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2648955 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3031711 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25598263 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 405605 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 67299344 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 135063 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14019935 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8605996 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 545729 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 81019 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 7196 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 21919 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 232087 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 197105 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 429192 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87765278 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43831578 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2830737 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 145081 # number of nop insts executed -system.cpu1.iew.exec_refs 48220727 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7143156 # Number of branches executed -system.cpu1.iew.exec_stores 7512980 # Number of stores executed -system.cpu1.iew.exec_rate 0.266206 # Inst execution rate -system.cpu1.iew.wb_sent 84396881 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55486086 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30755357 # num instructions producing a value -system.cpu1.iew.wb_consumers 55849815 # num instructions consuming a value +system.cpu1.iew.exec_nop 125146 # number of nop insts executed +system.cpu1.iew.exec_refs 51224987 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7024509 # Number of branches executed +system.cpu1.iew.exec_stores 7393409 # Number of stores executed +system.cpu1.iew.exec_rate 0.248048 # Inst execution rate +system.cpu1.iew.wb_sent 86598496 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54450360 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30044182 # num instructions producing a value +system.cpu1.iew.wb_consumers 53342809 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.172537 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.550680 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.153891 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.563228 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 38569031 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 49069302 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 19027054 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 702711 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 384240 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103162057 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.475653 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.464816 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 38036954 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 48396972 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 18817114 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 692387 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 376510 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111258144 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.434997 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.402953 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 86125230 83.49% 83.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8314170 8.06% 91.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2284328 2.21% 93.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1318858 1.28% 95.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1066734 1.03% 96.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 616185 0.60% 96.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1058049 1.03% 97.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 494277 0.48% 98.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1884226 1.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94210177 84.68% 84.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8524716 7.66% 92.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2208233 1.98% 94.32% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1307974 1.18% 95.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1064973 0.96% 96.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 589982 0.53% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1003368 0.90% 97.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 487910 0.44% 98.33% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1860811 1.67% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103162057 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38569031 # Number of instructions committed -system.cpu1.commit.committedOps 49069302 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111258144 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38036954 # Number of instructions committed +system.cpu1.commit.committedOps 48396972 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17180057 # Number of memory references committed -system.cpu1.commit.loads 10040109 # Number of loads committed -system.cpu1.commit.membars 207982 # Number of memory barriers committed -system.cpu1.commit.branches 6108113 # Number of branches committed -system.cpu1.commit.fp_insts 5310 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43785233 # Number of committed integer instructions. -system.cpu1.commit.function_calls 563417 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1884226 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17007249 # Number of memory references committed +system.cpu1.commit.loads 9989241 # Number of loads committed +system.cpu1.commit.membars 202226 # Number of memory barriers committed +system.cpu1.commit.branches 5993368 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43235909 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556157 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1860811 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 168322862 # The number of ROB reads -system.cpu1.rob.rob_writes 139443210 # The number of ROB writes -system.cpu1.timesIdled 1396987 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 215348346 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4817788385 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38483753 # Number of Instructions Simulated -system.cpu1.committedOps 48984024 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38483753 # Number of Instructions Simulated -system.cpu1.cpi 8.356499 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.356499 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.119667 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.119667 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 385614321 # number of integer regfile reads -system.cpu1.int_regfile_writes 58138574 # number of integer regfile writes -system.cpu1.fp_regfile_reads 3969 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1880 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91635789 # number of misc regfile reads -system.cpu1.misc_regfile_writes 441645 # number of misc regfile writes -system.cpu1.icache.replacements 628575 # number of replacements -system.cpu1.icache.tagsinuse 498.649539 # Cycle average of tags in use -system.cpu1.icache.total_refs 8518604 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 629087 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.541218 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 73946666000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.649539 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.973925 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.973925 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8518604 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8518604 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8518604 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8518604 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8518604 # number of overall hits -system.cpu1.icache.overall_hits::total 8518604 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 678443 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 678443 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 678443 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 678443 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 678443 # number of overall misses -system.cpu1.icache.overall_misses::total 678443 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9864551499 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9864551499 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9864551499 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9864551499 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9864551499 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9864551499 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9197047 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9197047 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9197047 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9197047 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9197047 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9197047 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073767 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073767 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073767 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073767 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073767 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073767 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14539.985672 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14539.985672 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14539.985672 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14539.985672 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14539.985672 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 932999 # number of cycles access was blocked +system.cpu1.rob.rob_reads 175585773 # The number of ROB reads +system.cpu1.rob.rob_writes 137553768 # The number of ROB writes +system.cpu1.timesIdled 1520299 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 239582989 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4808538839 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37967315 # Number of Instructions Simulated +system.cpu1.committedOps 48327333 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37967315 # Number of Instructions Simulated +system.cpu1.cpi 9.319185 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 9.319185 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.107306 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.107306 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 393921761 # number of integer regfile reads +system.cpu1.int_regfile_writes 56840694 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4925 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2334 # number of floating regfile writes +system.cpu1.misc_regfile_reads 90313719 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429414 # number of misc regfile writes +system.cpu1.icache.replacements 622931 # number of replacements +system.cpu1.icache.tagsinuse 498.760560 # Cycle average of tags in use +system.cpu1.icache.total_refs 8545880 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 623443 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.707556 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74633827000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.760560 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974142 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974142 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8545880 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8545880 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8545880 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8545880 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8545880 # number of overall hits +system.cpu1.icache.overall_hits::total 8545880 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 673372 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 673372 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 673372 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 673372 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 673372 # number of overall misses +system.cpu1.icache.overall_misses::total 673372 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10716931993 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10716931993 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10716931993 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10716931993 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10716931993 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10716931993 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 9219252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 9219252 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 9219252 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 9219252 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 9219252 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 9219252 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073040 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073040 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073040 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073040 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073040 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073040 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15915.321684 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15915.321684 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15915.321684 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15915.321684 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15915.321684 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1332494 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 205 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6098.032680 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6499.970732 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 30976 # number of writebacks -system.cpu1.icache.writebacks::total 30976 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49327 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 49327 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 49327 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 49327 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 49327 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 49327 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 629116 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 629116 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 629116 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 629116 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 629116 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 629116 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7390302499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7390302499 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7390302499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7390302499 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7390302499 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7390302499 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2676000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2676000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2676000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2676000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.068404 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.068404 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.068404 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.068404 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11747.122151 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11747.122151 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11747.122151 # average overall mshr miss latency +system.cpu1.icache.writebacks::writebacks 33068 # number of writebacks +system.cpu1.icache.writebacks::total 33068 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 49906 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 49906 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 49906 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 49906 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 49906 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 49906 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 623466 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 623466 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 623466 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 623466 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 623466 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 623466 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8227032008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8227032008 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8227032008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8227032008 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8227032008 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3154000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3154000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3154000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3154000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067627 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067627 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067627 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067627 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13195.638588 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13195.638588 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13195.638588 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 365990 # number of replacements -system.cpu1.dcache.tagsinuse 486.374853 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13437990 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 366502 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.665530 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70078369000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 486.374853 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.949951 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.949951 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8795505 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8795505 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4385128 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4385128 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 106581 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 106581 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 102282 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 102282 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 13180633 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 13180633 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 13180633 # number of overall hits -system.cpu1.dcache.overall_hits::total 13180633 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 408153 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 408153 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1582783 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1582783 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13916 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13916 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10800 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10800 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1990936 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1990936 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1990936 # number of overall misses -system.cpu1.dcache.overall_misses::total 1990936 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5766799000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5766799000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 55285236443 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 55285236443 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 141367500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 141367500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 89573500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 89573500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 61052035443 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 61052035443 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 61052035443 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 61052035443 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9203658 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9203658 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5967911 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5967911 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 120497 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 120497 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 113082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 113082 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 15171569 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 15171569 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 15171569 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 15171569 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044347 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044347 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.265216 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.265216 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.115488 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.115488 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095506 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095506 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.131228 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.131228 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.131228 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.131228 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14129.012895 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14129.012895 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34929.132069 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34929.132069 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10158.630354 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10158.630354 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8293.842593 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8293.842593 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30664.991463 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30664.991463 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 30664.991463 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 12254574 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5966500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3013 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 167 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4067.233322 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 35727.544910 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 362729 # number of replacements +system.cpu1.dcache.tagsinuse 487.126779 # Cycle average of tags in use +system.cpu1.dcache.total_refs 13112337 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 363073 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 36.114878 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70483759000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 487.126779 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.951419 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.951419 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8613908 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8613908 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4252702 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4252702 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105106 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 105106 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100709 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100709 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12866610 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12866610 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12866610 # number of overall hits +system.cpu1.dcache.overall_hits::total 12866610 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 410185 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 410185 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1595357 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1595357 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14278 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14278 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10900 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10900 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 2005542 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 2005542 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 2005542 # number of overall misses +system.cpu1.dcache.overall_misses::total 2005542 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8114216000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8114216000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66620735237 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 66620735237 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166584000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 166584000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 94819000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 94819000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74734951237 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74734951237 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74734951237 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74734951237 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9024093 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9024093 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5848059 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5848059 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119384 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 119384 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111609 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14872152 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14872152 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14872152 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14872152 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045454 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045454 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272801 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272801 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119597 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119597 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097662 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097662 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134852 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134852 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134852 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134852 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19781.844777 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19781.844777 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41759.139326 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41759.139326 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11667.180277 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11667.180277 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8698.990826 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8698.990826 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 37264.216475 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 37264.216475 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 37264.216475 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29196505 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 5606000 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 6645 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 174 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4393.755455 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32218.390805 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 330007 # number of writebacks -system.cpu1.dcache.writebacks::total 330007 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172901 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172901 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1420692 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1420692 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1265 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1265 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1593593 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1593593 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1593593 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1593593 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 235252 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 235252 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162091 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162091 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12651 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12651 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10796 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10796 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 397343 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 397343 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 397343 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 397343 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2772800000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2772800000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5167139074 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5167139074 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88580000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 57154000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 57154000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7939939074 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7939939074 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7939939074 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7939939074 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 123239389500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 123239389500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 41654166350 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 41654166350 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 164893555850 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 164893555850 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025561 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025561 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027160 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027160 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.104990 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.104990 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095471 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095471 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026190 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026190 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11786.509785 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11786.509785 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31878.013425 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31878.013425 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7001.818038 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7001.818038 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5293.997777 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5293.997777 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19982.581986 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19982.581986 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327467 # number of writebacks +system.cpu1.dcache.writebacks::total 327467 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 179191 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 179191 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1432552 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1432552 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1457 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1457 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1611743 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1611743 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1611743 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1611743 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 230994 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 230994 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162805 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162805 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12821 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12821 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10892 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 393799 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 393799 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 393799 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 393799 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3545762451 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3545762451 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5565749199 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5565749199 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104395505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104395505 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 60832506 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 60832506 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9111511650 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9111511650 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9111511650 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9111511650 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137004750500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137004750500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40571899654 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40571899654 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 177576650154 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 177576650154 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025597 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027839 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027839 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107393 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107393 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097591 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097591 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026479 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026479 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026479 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15350.019702 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15350.019702 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34186.598686 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34186.598686 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8142.539973 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8142.539973 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5585.062982 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5585.062982 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23137.467718 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23137.467718 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1697,18 +1673,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1308136748055 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308136748055 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1308136748055 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1305278151135 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1305278151135 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1305278151135 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 42935 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43785 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 54742 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53912 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 027fdffc2..71f536288 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -518,7 +518,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -579,7 +579,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side @@ -992,7 +992,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 9c5baf3db..34717b2ec 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:31:55 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 17:04:56 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2500827052500 because m5_exit instruction encountered +Exiting @ tick 2502549875500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 2b0eb45e9..6df4de0df 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,16 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.500827 # Number of seconds simulated -sim_ticks 2500827052500 # Number of ticks simulated -final_tick 2500827052500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.502550 # Number of seconds simulated +sim_ticks 2502549875500 # Number of ticks simulated +final_tick 2502549875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90125 # Simulator instruction rate (inst/s) -host_op_rate 116367 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3783000939 # Simulator tick rate (ticks/s) -host_mem_usage 386964 # Number of bytes of host memory used -host_seconds 661.07 # Real time elapsed on the host -sim_insts 59579144 # Number of instructions simulated -sim_ops 76926734 # Number of ops (including micro ops) simulated +host_inst_rate 90191 # Simulator instruction rate (inst/s) +host_op_rate 116452 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3788406278 # Simulator tick rate (ticks/s) +host_mem_usage 386884 # Number of bytes of host memory used +host_seconds 660.58 # Real time elapsed on the host +sim_insts 59578267 # Number of instructions simulated +sim_ops 76925839 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 118994504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 800128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094928 # Number of bytes read from this memory +system.physmem.bytes_read::total 128893400 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800128 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802248 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14874313 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12502 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142142 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15029017 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813177 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47549304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 319725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3634264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51504828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 319725 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1512927 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1205200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2718127 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1512927 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47549304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 319725 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4839464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54222954 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -23,191 +61,149 @@ system.realview.nvmem.bw_inst_read::cpu.inst 26 system.realview.nvmem.bw_inst_read::total 26 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 26 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 117964800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9095824 # Number of bytes read from this memory -system.physmem.bytes_read::total 127863440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799424 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784576 # Number of bytes written to this memory -system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800648 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 14745600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142156 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14900300 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59134 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813152 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47170315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 26 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 319664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3637126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51128462 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 319664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1513330 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1206030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2719360 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1513330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47170315 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 26 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 319664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4843156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53847821 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64425 # number of replacements -system.l2c.tagsinuse 51220.169448 # Cycle average of tags in use -system.l2c.total_refs 2029411 # Total number of references to valid blocks. -system.l2c.sampled_refs 129819 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.632619 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2490891834000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36757.661469 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 42.093314 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000181 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8185.117102 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6235.297383 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.560877 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000642 # Average percentage of cache occupancy +system.l2c.replacements 64431 # number of replacements +system.l2c.tagsinuse 51237.782352 # Cycle average of tags in use +system.l2c.total_refs 2028510 # Total number of references to valid blocks. +system.l2c.sampled_refs 129827 # Sample count of references to valid blocks. +system.l2c.avg_refs 15.624716 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2492014554000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36760.884600 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 47.476285 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000184 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 8187.042847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6242.378435 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.560927 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.dtb.walker 0.000724 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.124895 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.095143 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 122696 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 11776 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 977061 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 384470 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1496003 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 675876 # number of Writeback hits -system.l2c.Writeback_hits::total 675876 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 50 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 50 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112893 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112893 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 122696 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 977061 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 497363 # number of demand (read+write) hits -system.l2c.demand_hits::total 1608896 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 122696 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11776 # number of overall hits -system.l2c.overall_hits::cpu.inst 977061 # number of overall hits -system.l2c.overall_hits::cpu.data 497363 # number of overall hits -system.l2c.overall_hits::total 1608896 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 52 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124924 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095251 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781827 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 121963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 11826 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977935 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 383708 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1495432 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 675442 # number of Writeback hits +system.l2c.Writeback_hits::total 675442 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 16 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 16 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 112737 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 112737 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 121963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 11826 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977935 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 496445 # number of demand (read+write) hits +system.l2c.demand_hits::total 1608169 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 121963 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 11826 # number of overall hits +system.l2c.overall_hits::cpu.inst 977935 # number of overall hits +system.l2c.overall_hits::cpu.data 496445 # number of overall hits +system.l2c.overall_hits::total 1608169 # number of overall hits +system.l2c.ReadReq_misses::cpu.dtb.walker 59 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 12370 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 10695 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23118 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2910 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2910 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133257 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133257 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 52 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu.inst 12384 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 10691 # number of ReadReq misses +system.l2c.ReadReq_misses::total 23135 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2909 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2909 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133229 # number of ReadExReq misses +system.l2c.demand_misses::cpu.dtb.walker 59 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 12370 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 143952 # number of demand (read+write) misses -system.l2c.demand_misses::total 156375 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 52 # number of overall misses +system.l2c.demand_misses::cpu.inst 12384 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 143920 # number of demand (read+write) misses +system.l2c.demand_misses::total 156364 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 59 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu.inst 12370 # number of overall misses -system.l2c.overall_misses::cpu.data 143952 # number of overall misses -system.l2c.overall_misses::total 156375 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2714000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 53000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 647826500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 558032000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1208625500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 993500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 993500 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 52000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6991862500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6991862500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2714000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 53000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 647826500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 7549894500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8200488000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2714000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 53000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 647826500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 7549894500 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8200488000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 122748 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 11777 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 989431 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 395165 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1519121 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 675876 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 675876 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2960 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu.data 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246150 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 122748 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 11777 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 989431 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 641315 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1765271 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 122748 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 11777 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 989431 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 641315 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1765271 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000424 # miss rate for ReadReq accesses +system.l2c.overall_misses::cpu.inst 12384 # number of overall misses +system.l2c.overall_misses::cpu.data 143920 # number of overall misses +system.l2c.overall_misses::total 156364 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3091500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.inst 659591498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu.data 562236498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1224979496 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu.data 944500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 944500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 7069904999 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7069904999 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu.dtb.walker 3091500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.itb.walker 60000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.inst 659591498 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 7632141497 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8294884495 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu.dtb.walker 3091500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.itb.walker 60000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.inst 659591498 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu.data 7632141497 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8294884495 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.dtb.walker 122022 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 11827 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 990319 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 394399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1518567 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 675442 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 675442 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2951 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu.data 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 245966 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 122022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 11827 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 990319 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 640365 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1764533 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 122022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 11827 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 990319 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 640365 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1764533 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000484 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000085 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012502 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.027065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.015218 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.983108 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.983108 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.294118 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541365 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541365 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000424 # miss rate for demand accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012505 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.027107 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.015235 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.985768 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.985768 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.157895 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.541656 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.541656 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000484 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012502 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.224464 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088584 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000424 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu.inst 0.012505 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.224747 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.088615 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000484 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu.itb.walker 0.000085 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012502 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.224464 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.088584 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 53000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.inst 52370.776071 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu.data 52176.905096 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52280.711999 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 341.408935 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 341.408935 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 10400 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 10400 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52469.007257 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52469.007257 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52441.170264 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.itb.walker 53000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.inst 52370.776071 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52447.305352 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52441.170264 # average overall miss latency +system.l2c.overall_miss_rate::cpu.inst 0.012505 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.224747 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.088615 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52398.305085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 60000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.inst 53261.587371 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu.data 52589.701431 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52949.189367 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 324.682021 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 324.682021 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 53065.811490 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53065.811490 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53048.556541 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52398.305085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.itb.walker 60000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.inst 53261.587371 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 53030.443976 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53048.556541 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -216,109 +212,109 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 59134 # number of writebacks -system.l2c.writebacks::total 59134 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 59159 # number of writebacks +system.l2c.writebacks::total 59159 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu.inst 9 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu.inst 9 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu.inst 9 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 52 # number of ReadReq MSHR misses +system.l2c.overall_mshr_hits::total 71 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 59 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.inst 12362 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu.data 10633 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23048 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 2910 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2910 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 133257 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 133257 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu.dtb.walker 52 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.inst 12375 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu.data 10629 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 2909 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2909 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 133229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 133229 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu.dtb.walker 59 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.inst 12362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 143890 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 156305 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu.dtb.walker 52 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu.inst 12375 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 143858 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 156293 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu.dtb.walker 59 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.inst 12362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 143890 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 156305 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2081000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 41000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.inst 496452000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu.data 425891000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 924465000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116622000 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 200000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5338935000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2081000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.itb.walker 41000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.inst 496452000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 5764826000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6263400000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2081000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.itb.walker 41000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.inst 496452000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 5764826000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6263400000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5219000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131764564500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 131769783500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32353763131 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5219000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu.data 164118327631 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 164123546631 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::cpu.inst 12375 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 143858 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 156293 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 2372000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 48000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.inst 508160500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu.data 430170499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 940750999 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 116825000 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5436034999 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2372000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 48000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 508160500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 5866205498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6376785998 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2372000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 48000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 508160500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 5866205498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6376785998 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 5323000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131417115000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 131422438000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 31373446015 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.inst 5323000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 162790561015 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 162795884015 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026908 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.015172 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.983108 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.294118 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.541365 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for demand accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015188 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.985768 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.157895 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541656 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.088544 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000424 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.088575 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000484 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000085 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012494 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.224367 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.088544 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 41000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40159.521113 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40053.700743 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40110.421729 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40076.288660 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40076.288660 # average UpgradeReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012496 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.224650 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.088575 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41063.474747 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40471.398909 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40788.718306 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40159.848745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40159.848745 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.949684 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40064.949684 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40019.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 41000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40159.521113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40064.118424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40071.654778 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40802.190206 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40802.190206 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40203.389831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41063.474747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40777.749572 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40800.202172 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -336,27 +332,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51785537 # DTB read hits -system.cpu.dtb.read_misses 81591 # DTB read misses -system.cpu.dtb.write_hits 11872923 # DTB write hits -system.cpu.dtb.write_misses 18231 # DTB write misses +system.cpu.dtb.read_hits 51771660 # DTB read hits +system.cpu.dtb.read_misses 81258 # DTB read misses +system.cpu.dtb.write_hits 11880398 # DTB write hits +system.cpu.dtb.write_misses 17961 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4506 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2988 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 690 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4471 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3044 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 609 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1351 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51867128 # DTB read accesses -system.cpu.dtb.write_accesses 11891154 # DTB write accesses +system.cpu.dtb.perms_faults 1282 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51852918 # DTB read accesses +system.cpu.dtb.write_accesses 11898359 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63658460 # DTB hits -system.cpu.dtb.misses 99822 # DTB misses -system.cpu.dtb.accesses 63758282 # DTB accesses -system.cpu.itb.inst_hits 13022422 # ITB inst hits -system.cpu.itb.inst_misses 12153 # ITB inst misses +system.cpu.dtb.hits 63652058 # DTB hits +system.cpu.dtb.misses 99219 # DTB misses +system.cpu.dtb.accesses 63751277 # DTB accesses +system.cpu.itb.inst_hits 13142261 # ITB inst hits +system.cpu.itb.inst_misses 12247 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -365,542 +361,542 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2627 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2634 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3259 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3496 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13034575 # ITB inst accesses -system.cpu.itb.hits 13022422 # DTB hits -system.cpu.itb.misses 12153 # DTB misses -system.cpu.itb.accesses 13034575 # DTB accesses -system.cpu.numCycles 408047924 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13154508 # ITB inst accesses +system.cpu.itb.hits 13142261 # DTB hits +system.cpu.itb.misses 12247 # DTB misses +system.cpu.itb.accesses 13154508 # DTB accesses +system.cpu.numCycles 413642740 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14895929 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11838635 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 749498 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9774236 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7761608 # Number of BTB hits +system.cpu.BPredUnit.lookups 14974990 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11915620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 753400 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10068197 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7820088 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1450585 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80646 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 32131999 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 99541579 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14895929 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9212193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21738174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6062724 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 161664 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 89532236 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 119247 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208172 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13018415 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 931788 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6733 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.832729 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.216336 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1448775 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 80927 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33422471 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 99542070 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14974990 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9268863 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21759182 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6002262 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 163536 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 93319816 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2533 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 133610 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 208459 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 397 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13138017 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1024097 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6504 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.804842 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.182667 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 126328884 85.33% 85.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1364567 0.92% 86.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1757577 1.19% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2627928 1.78% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1817598 1.23% 90.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1139974 0.77% 91.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2881875 1.95% 93.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 793207 0.54% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9338521 6.31% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131386008 85.80% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1369017 0.89% 86.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759019 1.15% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2640315 1.72% 89.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1819667 1.19% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142419 0.75% 91.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2920911 1.91% 93.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 807762 0.53% 93.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9283189 6.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 148050131 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.036505 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.243946 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34138786 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89344652 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19542719 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1039822 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3984152 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2096721 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174752 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 115904821 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572765 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3984152 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 36116919 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36990471 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 46307759 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18567490 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6083340 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 109034273 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 3076 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1021710 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4089268 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 41156 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 113585552 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 502111824 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 502019660 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92164 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 77687957 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 35897594 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898050 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797560 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12232946 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20954804 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13881914 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1960286 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2534637 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 99654588 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1554944 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124705745 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186396 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23520309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 64631044 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 267642 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 148050131 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.842321 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.546134 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 153128307 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.036203 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.240647 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35537493 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 93048586 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19509299 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1086349 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3946580 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2100058 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 174557 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 116122172 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 568338 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3946580 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37621271 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39594801 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 46881047 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18412397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6672211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 108597287 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4175 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1156489 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4484156 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 30967 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 113073752 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 499820515 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 499727174 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 93341 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 77686691 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 35387060 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 898607 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 797702 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13307124 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21058263 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13875749 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1965166 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2564814 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 99781831 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1555350 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124613166 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 199798 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23638127 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65777806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 268083 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 153128307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.813783 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.516400 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 103452672 69.88% 69.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13854502 9.36% 79.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7174552 4.85% 84.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5822865 3.93% 88.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12669865 8.56% 96.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2797622 1.89% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1712436 1.16% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 433578 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 132039 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107849903 70.43% 70.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14560254 9.51% 79.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7302452 4.77% 84.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5913038 3.86% 88.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12593494 8.22% 96.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2809204 1.83% 98.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1536315 1.00% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 438168 0.29% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 125479 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 148050131 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 153128307 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 59948 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8388673 94.51% 95.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 427083 4.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53462 0.61% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8367005 94.75% 95.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 409700 4.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 106530 0.09% 0.09% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58643579 47.03% 47.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95161 0.08% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 13 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.19% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53352582 42.78% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12505747 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58482659 46.93% 47.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95330 0.08% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 11 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 5 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53414157 42.86% 89.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12512351 10.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124705745 # Type of FU issued -system.cpu.iq.rate 0.305615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8875706 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406599918 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 124750196 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85869603 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23265 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12672 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10345 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 133462587 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12334 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 642048 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 124613166 # Type of FU issued +system.cpu.iq.rate 0.301258 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8830169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.070861 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 411460543 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 124996425 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85630389 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 22925 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12868 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10343 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 133324707 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12098 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 646336 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5239514 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10265 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 34172 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2083712 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5343093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 35068 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2077574 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107049 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1151692 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107202 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1049886 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3984152 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28395992 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 447371 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 101464012 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 233619 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20954804 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13881914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 964089 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112476 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6557 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 34172 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 381147 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 331860 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 713007 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121711788 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52474170 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2993957 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3946580 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 29463666 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 540836 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 101593235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 217276 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21058263 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13875749 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 964547 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 125689 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 40656 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 35068 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 381127 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 332167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 713294 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121438397 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52461807 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3174769 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 254480 # number of nop insts executed -system.cpu.iew.exec_refs 64857639 # number of memory reference insts executed -system.cpu.iew.exec_branches 11392260 # Number of branches executed -system.cpu.iew.exec_stores 12383469 # Number of stores executed -system.cpu.iew.exec_rate 0.298278 # Inst execution rate -system.cpu.iew.wb_sent 120307041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85879948 # cumulative count of insts written-back -system.cpu.iew.wb_producers 46962413 # num instructions producing a value -system.cpu.iew.wb_consumers 87363153 # num instructions consuming a value +system.cpu.iew.exec_nop 256054 # number of nop insts executed +system.cpu.iew.exec_refs 64853171 # number of memory reference insts executed +system.cpu.iew.exec_branches 11412736 # Number of branches executed +system.cpu.iew.exec_stores 12391364 # Number of stores executed +system.cpu.iew.exec_rate 0.293583 # Inst execution rate +system.cpu.iew.wb_sent 120063166 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85640732 # cumulative count of insts written-back +system.cpu.iew.wb_producers 46459932 # num instructions producing a value +system.cpu.iew.wb_consumers 84649521 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.210465 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.537554 # average fanout of values written-back +system.cpu.iew.wb_rate 0.207040 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.548851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 59729525 # The number of committed instructions -system.cpu.commit.commitCommittedOps 77077115 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 24198873 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1287302 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 621123 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 144148394 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.534707 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.521609 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 59728648 # The number of committed instructions +system.cpu.commit.commitCommittedOps 77076220 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 24329020 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1287267 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 625309 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 149264139 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.516375 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.492760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 116600934 80.89% 80.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13538329 9.39% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3987949 2.77% 93.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2150587 1.49% 94.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1741345 1.21% 95.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028717 0.71% 96.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1566098 1.09% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 669906 0.46% 98.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2864529 1.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121340444 81.29% 81.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13976446 9.36% 90.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3929866 2.63% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2230737 1.49% 94.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1774137 1.19% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1064202 0.71% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1398926 0.94% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 658331 0.44% 98.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891050 1.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 144148394 # Number of insts commited each cycle -system.cpu.commit.committedInsts 59729525 # Number of instructions committed -system.cpu.commit.committedOps 77077115 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 149264139 # Number of insts commited each cycle +system.cpu.commit.committedInsts 59728648 # Number of instructions committed +system.cpu.commit.committedOps 77076220 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27513492 # Number of memory references committed -system.cpu.commit.loads 15715290 # Number of loads committed -system.cpu.commit.membars 413064 # Number of memory barriers committed -system.cpu.commit.branches 9904425 # Number of branches committed +system.cpu.commit.refs 27513345 # Number of memory references committed +system.cpu.commit.loads 15715170 # Number of loads committed +system.cpu.commit.membars 413057 # Number of memory barriers committed +system.cpu.commit.branches 9904308 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68617780 # Number of committed integer instructions. -system.cpu.commit.function_calls 995959 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2864529 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68616986 # Number of committed integer instructions. +system.cpu.commit.function_calls 995953 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2891050 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240802540 # The number of ROB reads -system.cpu.rob.rob_writes 206662154 # The number of ROB writes -system.cpu.timesIdled 1878638 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 259997793 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4593518134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 59579144 # Number of Instructions Simulated -system.cpu.committedOps 76926734 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 59579144 # Number of Instructions Simulated -system.cpu.cpi 6.848838 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.848838 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146010 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.146010 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 552215109 # number of integer regfile reads -system.cpu.int_regfile_writes 88113131 # number of integer regfile writes -system.cpu.fp_regfile_reads 8314 # number of floating regfile reads -system.cpu.fp_regfile_writes 2878 # number of floating regfile writes -system.cpu.misc_regfile_reads 131767968 # number of misc regfile reads -system.cpu.misc_regfile_writes 912736 # number of misc regfile writes -system.cpu.icache.replacements 990445 # number of replacements -system.cpu.icache.tagsinuse 511.614969 # Cycle average of tags in use -system.cpu.icache.total_refs 11943122 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 990957 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.052109 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6217994000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.614969 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999248 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999248 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11943122 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11943122 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11943122 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11943122 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11943122 # number of overall hits -system.cpu.icache.overall_hits::total 11943122 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1075156 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1075156 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1075156 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1075156 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1075156 # number of overall misses -system.cpu.icache.overall_misses::total 1075156 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15637742995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15637742995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15637742995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15637742995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15637742995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13018278 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13018278 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13018278 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13018278 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13018278 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.082588 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.082588 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.082588 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.082588 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.082588 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14544.627008 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14544.627008 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14544.627008 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14544.627008 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2121995 # number of cycles access was blocked +system.cpu.rob.rob_reads 246021016 # The number of ROB reads +system.cpu.rob.rob_writes 206855771 # The number of ROB writes +system.cpu.timesIdled 1910853 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 260514433 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4591368963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 59578267 # Number of Instructions Simulated +system.cpu.committedOps 76925839 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 59578267 # Number of Instructions Simulated +system.cpu.cpi 6.942846 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.942846 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144033 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144033 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 551124722 # number of integer regfile reads +system.cpu.int_regfile_writes 87730818 # number of integer regfile writes +system.cpu.fp_regfile_reads 8186 # number of floating regfile reads +system.cpu.fp_regfile_writes 2858 # number of floating regfile writes +system.cpu.misc_regfile_reads 131789755 # number of misc regfile reads +system.cpu.misc_regfile_writes 912697 # number of misc regfile writes +system.cpu.icache.replacements 991190 # number of replacements +system.cpu.icache.tagsinuse 511.611770 # Cycle average of tags in use +system.cpu.icache.total_refs 12061455 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991702 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.162378 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6426198000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.611770 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999242 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999242 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12061455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12061455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12061455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12061455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12061455 # number of overall hits +system.cpu.icache.overall_hits::total 12061455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1076423 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1076423 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1076423 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1076423 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1076423 # number of overall misses +system.cpu.icache.overall_misses::total 1076423 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16851120991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16851120991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16851120991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16851120991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16851120991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13137878 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13137878 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13137878 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13137878 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13137878 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.081933 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.081933 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.081933 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.081933 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.081933 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15654.738881 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15654.738881 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15654.738881 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15654.738881 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2871493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 461 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 7342.543253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6228.835141 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 67776 # number of writebacks -system.cpu.icache.writebacks::total 67776 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84152 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84152 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84152 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84152 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84152 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991004 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 991004 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 991004 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 991004 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 991004 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11660559495 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11660559495 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11660559495 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 6997000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076124 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076124 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076124 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11766.410120 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11766.410120 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11766.410120 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 67899 # number of writebacks +system.cpu.icache.writebacks::total 67899 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84680 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84680 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84680 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84680 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84680 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991743 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991743 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991743 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991743 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991743 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12825867499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12825867499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12825867499 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7992500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7992500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075487 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075487 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075487 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12932.652410 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12932.652410 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12932.652410 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 644124 # number of replacements -system.cpu.dcache.tagsinuse 511.991568 # Cycle average of tags in use -system.cpu.dcache.total_refs 21775548 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644636 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.779603 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 49161000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991568 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999984 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13910712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13910712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7293091 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7293091 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282930 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282930 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285654 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285654 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21203803 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21203803 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21203803 # number of overall hits -system.cpu.dcache.overall_hits::total 21203803 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 740801 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 740801 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2957315 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2957315 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13662 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 17 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 17 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3698116 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3698116 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3698116 # number of overall misses -system.cpu.dcache.overall_misses::total 3698116 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10501483000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 106800352759 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 200535500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 452000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117301835759 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117301835759 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117301835759 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14651513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14651513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 643139 # number of replacements +system.cpu.dcache.tagsinuse 511.991335 # Cycle average of tags in use +system.cpu.dcache.total_refs 21733833 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643651 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.766487 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50933000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991335 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 13904166 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13904166 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7257095 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7257095 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 283844 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 283844 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285639 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285639 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21161261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21161261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21161261 # number of overall hits +system.cpu.dcache.overall_hits::total 21161261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 765252 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 765252 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2993311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2993311 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13765 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13765 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 19 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3758563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3758563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3758563 # number of overall misses +system.cpu.dcache.overall_misses::total 3758563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14844603000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129412035593 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 223977000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 405000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144256638593 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144256638593 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144256638593 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14669418 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14669418 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10250406 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10250406 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296592 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285671 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24901919 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24901919 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24901919 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24901919 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050561 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288507 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046063 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000060 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148507 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148507 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148507 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148507 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14175.848845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14175.848845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36113.959033 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36113.959033 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14678.341385 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26588.235294 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31719.350004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31719.350004 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14079439 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7830500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2852 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 275 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4936.689691 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 28474.545455 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 297609 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285658 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919824 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919824 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919824 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919824 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052166 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292019 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046252 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000067 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.150826 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.150826 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.150826 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.150826 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19398.319769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19398.319769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43233.742031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43233.742031 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16271.485652 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 21315.789474 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38380.795691 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38380.795691 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32633902 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7260500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7285 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4479.602196 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25655.477032 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608100 # number of writebacks -system.cpu.dcache.writebacks::total 608100 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 354542 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 354542 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2708293 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1346 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3062835 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3062835 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3062835 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386259 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386259 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249022 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249022 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12316 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635281 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635281 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635281 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4943544500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8596724439 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 143823500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 395000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13540268939 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13540268939 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147158057500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42257629539 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 189415687039 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026363 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041525 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000060 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025511 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025511 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12798.522494 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34521.947615 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.776876 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 23235.294118 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21313.826384 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21313.826384 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607543 # number of writebacks +system.cpu.dcache.writebacks::total 607543 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379767 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379767 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2744505 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3124272 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3124272 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3124272 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385485 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385485 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248806 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248806 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12312 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 19 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634291 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634291 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634291 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6242554097 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9246380950 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164108000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 341500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15488935047 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15488935047 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147082070000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41215087708 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 188297157708 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026278 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024273 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041370 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000067 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025453 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025453 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16194.025960 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37163.014357 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13329.109812 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 17973.684211 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24419.288697 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24419.288697 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -922,16 +918,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1290934638893 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1290934638893 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1290934638893 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1298563544001 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1298563544001 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1298563544001 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88048 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88049 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |