diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
| commit | 09b2430e95df4f744a000bac34100eeb9ebcb878 (patch) | |
| tree | 1db0ab99b4186f15335a866fd7239ba51755b7d9 /tests/long/fs/10.linux-boot/ref/arm/linux | |
| parent | f205d83359dfb3c4f75159f83081b5e356c3c4b4 (diff) | |
| download | gem5-09b2430e95df4f744a000bac34100eeb9ebcb878.tar.xz | |
stats: update patches for branch predictor and fetch updates.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux')
16 files changed, 5199 insertions, 5206 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 366d8d2c3..c2660d718 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -707,6 +707,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 28e40a40b..b7a2e0ce5 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -21,14 +22,13 @@ warn: 2291164927000: Instruction results do not match! (Values may not actually warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: 2483733168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2497502762000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2498707540000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2497502713500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2498707539500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 warn: 2519748168000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2520262198000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2525920507000: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0x200da -warn: 2525942893500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2526450197000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2527009496000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2527010611500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -warn: 2527557612000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 +warn: 2520262039500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2525942762500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2526449392000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2527008451000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2527009567500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2527556775500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index e0cb5000c..444ce680b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 20:59:50 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 22:59:32 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2533147650000 because m5_exit instruction encountered +Exiting @ tick 2533144795000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index b54fd326b..6f639a911 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143504000 # Number of ticks simulated -final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2533143973500 # Number of ticks simulated +final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65433 # Simulator instruction rate (inst/s) -host_op_rate 84194 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2748425484 # Simulator tick rate (ticks/s) -host_mem_usage 408856 # Number of bytes of host memory used -host_seconds 921.67 # Real time elapsed on the host +host_inst_rate 55009 # Simulator instruction rate (inst/s) +host_op_rate 70781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2310577470 # Simulator tick rate (ticks/s) +host_mem_usage 405260 # Number of bytes of host memory used +host_seconds 1096.33 # Real time elapsed on the host sim_insts 60307579 # Number of instructions simulated sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096820 # Total number of read requests seen -system.physmem.writeReqs 813121 # Total number of write requests seen -system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196480 # Total number of bytes read from memory -system.physmem.bytesWritten 52039744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096817 # Total number of read requests seen +system.physmem.writeReqs 813117 # Total number of write requests seen +system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196288 # Total number of bytes read from memory +system.physmem.bytesWritten 52039488 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142364000 # Total gap between requests +system.physmem.totGap 2533142848500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59103 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59099 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see @@ -160,8 +160,8 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::28 32584 # Wh system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482965000 # Total cycles spent in databus access -system.physmem.totBankLat 16912788750 # Total cycles spent in bank access -system.physmem.avgQLat 26048.65 # Average queueing delay per request -system.physmem.avgBankLat 1120.31 # Average bank access latency per request +system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests +system.physmem.totBusLat 75482950000 # Total cycles spent in databus access +system.physmem.totBankLat 16911785000 # Total cycles spent in bank access +system.physmem.avgQLat 26049.00 # Average queueing delay per request +system.physmem.avgBankLat 1120.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.96 # Average memory access latency +system.physmem.avgMemAccLat 32169.24 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -187,11 +187,11 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020273 # Number of row buffer hits during reads -system.physmem.writeRowHits 793117 # Number of row buffer hits during writes +system.physmem.readRowHits 15020272 # Number of row buffer hits during reads +system.physmem.writeRowHits 793090 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.58 # Average gap between requests +system.physmem.avgGap 159217.68 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,14 +210,14 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14678084 # Number of BP lookups -system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits +system.cpu.branchPred.lookups 14675749 # Number of BP lookups +system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses @@ -266,27 +266,27 @@ system.cpu.checker.numWorkItemsStarted 0 # nu system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51401633 # DTB read hits -system.cpu.dtb.read_misses 64365 # DTB read misses -system.cpu.dtb.write_hits 11702282 # DTB write hits -system.cpu.dtb.write_misses 15903 # DTB write misses +system.cpu.dtb.read_hits 51399217 # DTB read hits +system.cpu.dtb.read_misses 64403 # DTB read misses +system.cpu.dtb.write_hits 11701345 # DTB write hits +system.cpu.dtb.write_misses 15902 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 6544 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 6540 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465998 # DTB read accesses -system.cpu.dtb.write_accesses 11718185 # DTB write accesses +system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51463620 # DTB read accesses +system.cpu.dtb.write_accesses 11717247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63103915 # DTB hits -system.cpu.dtb.misses 80268 # DTB misses -system.cpu.dtb.accesses 63184183 # DTB accesses -system.cpu.itb.inst_hits 12333169 # ITB inst hits -system.cpu.itb.inst_misses 11311 # ITB inst misses +system.cpu.dtb.hits 63100562 # DTB hits +system.cpu.dtb.misses 80305 # DTB misses +system.cpu.dtb.accesses 63180867 # DTB accesses +system.cpu.itb.inst_hits 12332677 # ITB inst hits +system.cpu.itb.inst_misses 11271 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -295,113 +295,113 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 4950 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 4946 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12344480 # ITB inst accesses -system.cpu.itb.hits 12333169 # DTB hits -system.cpu.itb.misses 11311 # DTB misses -system.cpu.itb.accesses 12344480 # DTB accesses -system.cpu.numCycles 471839315 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12343948 # ITB inst accesses +system.cpu.itb.hits 12332677 # DTB hits +system.cpu.itb.misses 11271 # DTB misses +system.cpu.itb.accesses 12343948 # DTB accesses +system.cpu.numCycles 471840254 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -430,13 +430,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -452,7 +452,7 @@ system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued @@ -464,84 +464,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued -system.cpu.iq.rate 0.263513 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued +system.cpu.iq.rate 0.263498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220929 # number of nop insts executed -system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed -system.cpu.iew.exec_branches 11562998 # Number of branches executed -system.cpu.iew.exec_stores 12213915 # Number of stores executed -system.cpu.iew.exec_rate 0.257621 # Inst execution rate -system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47225460 # num instructions producing a value -system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value +system.cpu.iew.exec_nop 221732 # number of nop insts executed +system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed +system.cpu.iew.exec_branches 11561583 # Number of branches executed +system.cpu.iew.exec_stores 12213002 # Number of stores executed +system.cpu.iew.exec_rate 0.257606 # Inst execution rate +system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47221894 # num instructions producing a value +system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle system.cpu.commit.committedInsts 60457960 # Number of instructions committed system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -552,261 +552,261 @@ system.cpu.commit.branches 9961316 # Nu system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242401590 # The number of ROB reads -system.cpu.rob.rob_writes 202045449 # The number of ROB writes -system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 242393474 # The number of ROB reads +system.cpu.rob.rob_writes 202038068 # The number of ROB writes +system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60307579 # Number of Instructions Simulated system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550352195 # number of integer regfile reads -system.cpu.int_regfile_writes 88467764 # number of integer regfile writes -system.cpu.fp_regfile_reads 8269 # number of floating regfile reads -system.cpu.fp_regfile_writes 2928 # number of floating regfile writes -system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.int_regfile_reads 550318453 # number of integer regfile reads +system.cpu.int_regfile_writes 88458214 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.replacements 979629 # number of replacements system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. +system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits -system.cpu.icache.overall_hits::total 11270072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses -system.cpu.icache.overall_misses::total 1059286 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits +system.cpu.icache.overall_hits::total 11269534 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059538 # 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number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905786256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910865586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026748 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985825 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985825 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,161 +927,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643539 # number of replacements +system.cpu.dcache.replacements 643553 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13756144 # 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number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962746 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962746 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13508 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses -system.cpu.dcache.overall_misses::total 3700421 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3700578 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700578 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700578 # number of overall misses +system.cpu.dcache.overall_misses::total 3700578 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks -system.cpu.dcache.writebacks::total 607840 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks +system.cpu.dcache.writebacks::total 607832 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1103,10 +1103,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 2403b9510..053c6a286 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1077,6 +1077,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index e8e271d58..4ccac5e7b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index d8e2a14f0..8d856e1ed 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 21:11:40 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 23:05:46 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1102937390000 because m5_exit instruction encountered +Exiting @ tick 1102934903000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 434326c81..5e12f3369 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102950 # Number of seconds simulated -sim_ticks 1102950399000 # Number of ticks simulated -final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102940 # Number of seconds simulated +sim_ticks 1102940172000 # Number of ticks simulated +final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57810 # Simulator instruction rate (inst/s) -host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1035290197 # Simulator tick rate (ticks/s) -host_mem_usage 414988 # Number of bytes of host memory used -host_seconds 1065.35 # Real time elapsed on the host -sim_insts 61588287 # Number of instructions simulated -sim_ops 79281553 # Number of ops (including micro ops) simulated +host_inst_rate 65652 # Simulator instruction rate (inst/s) +host_op_rate 84510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1175755462 # Simulator tick rate (ticks/s) +host_mem_usage 411412 # Number of bytes of host memory used +host_seconds 938.07 # Real time elapsed on the host +sim_insts 61586245 # Number of instructions simulated +sim_ops 79276446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory -system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory +system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257953 # Total number of read requests seen -system.physmem.writeReqs 823537 # Total number of write requests seen -system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508992 # Total number of bytes read from memory -system.physmem.bytesWritten 52706368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257967 # Total number of read requests seen +system.physmem.writeReqs 823548 # Total number of write requests seen +system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400509888 # Total number of bytes read from memory +system.physmem.bytesWritten 52707072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102949217500 # Total gap between requests +system.physmem.totGap 1102939019000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.readPktSize::6 163014 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66701 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66712 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -160,16 +160,16 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see @@ -182,8 +182,8 @@ system.physmem.wrQLenPdf::18 35806 # Wh system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see @@ -192,14 +192,14 @@ system.physmem.wrQLenPdf::28 32711 # Wh system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see -system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests -system.physmem.totBusLat 31289160000 # Total cycles spent in databus access -system.physmem.totBankLat 8530335000 # Total cycles spent in bank access -system.physmem.avgQLat 31830.81 # Average queueing delay per request -system.physmem.avgBankLat 1363.15 # Average bank access latency per request +system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests +system.physmem.totBusLat 31289230000 # Total cycles spent in databus access +system.physmem.totBankLat 8532328750 # Total cycles spent in bank access +system.physmem.avgQLat 31830.77 # Average queueing delay per request +system.physmem.avgBankLat 1363.46 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38193.95 # Average memory access latency +system.physmem.avgMemAccLat 38194.23 # Average memory access latency system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s @@ -207,12 +207,12 @@ system.physmem.avgConsumedWrBW 6.62 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 11.98 # Average write queue length over time -system.physmem.readRowHits 6213974 # Number of row buffer hits during reads -system.physmem.writeRowHits 800028 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.05 # Average write queue length over time +system.physmem.readRowHits 6213954 # Number of row buffer hits during reads +system.physmem.writeRowHits 800040 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155751.01 # Average gap between requests +system.physmem.avgGap 155749.02 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -231,251 +231,251 @@ system.realview.nvmem.bw_inst_read::total 406 # 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mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.739209 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.751971 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567474 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567605 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567546 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098746 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098746 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6001263 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits +system.cpu0.branchPred.lookups 5998401 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907872 # DTB read hits -system.cpu0.dtb.read_misses 28815 # DTB read misses -system.cpu0.dtb.write_hits 5138143 # DTB write hits -system.cpu0.dtb.write_misses 5606 # DTB write misses +system.cpu0.dtb.read_hits 8907261 # DTB read hits +system.cpu0.dtb.read_misses 28773 # DTB read misses +system.cpu0.dtb.write_hits 5136781 # DTB write hits +system.cpu0.dtb.write_misses 5705 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936687 # DTB read accesses -system.cpu0.dtb.write_accesses 5143749 # DTB write accesses +system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936034 # DTB read accesses +system.cpu0.dtb.write_accesses 5142486 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046015 # DTB hits -system.cpu0.dtb.misses 34421 # DTB misses -system.cpu0.dtb.accesses 14080436 # DTB accesses -system.cpu0.itb.inst_hits 4220167 # ITB inst hits -system.cpu0.itb.inst_misses 5223 # ITB inst misses +system.cpu0.dtb.hits 14044042 # DTB hits +system.cpu0.dtb.misses 34478 # DTB misses +system.cpu0.dtb.accesses 14078520 # DTB accesses +system.cpu0.itb.inst_hits 4215431 # ITB inst hits +system.cpu0.itb.inst_misses 5154 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,530 +718,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses -system.cpu0.itb.hits 4220167 # DTB hits -system.cpu0.itb.misses 5223 # DTB misses -system.cpu0.itb.accesses 4225390 # DTB accesses -system.cpu0.numCycles 67827032 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses +system.cpu0.itb.hits 4215431 # DTB hits +system.cpu0.itb.misses 5154 # DTB misses +system.cpu0.itb.accesses 4220585 # DTB accesses +system.cpu0.numCycles 67803924 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued -system.cpu0.iq.rate 0.549010 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued +system.cpu0.iq.rate 0.549040 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118689 # number of nop insts executed -system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4854206 # Number of branches executed -system.cpu0.iew.exec_stores 5397839 # Number of stores executed -system.cpu0.iew.exec_rate 0.543462 # Inst execution rate -system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18281082 # num instructions producing a value -system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value +system.cpu0.iew.exec_nop 118468 # number of nop insts executed +system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4853073 # Number of branches executed +system.cpu0.iew.exec_stores 5396490 # Number of stores executed +system.cpu0.iew.exec_rate 0.543517 # Inst execution rate +system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18277167 # num instructions producing a value +system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23679748 # Number of instructions committed -system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23678008 # Number of instructions committed +system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11426897 # Number of memory references committed -system.cpu0.commit.loads 6276420 # Number of loads committed -system.cpu0.commit.membars 229667 # Number of memory barriers committed -system.cpu0.commit.branches 4245051 # Number of branches committed +system.cpu0.commit.refs 11424361 # Number of memory references committed +system.cpu0.commit.loads 6275038 # Number of loads committed +system.cpu0.commit.membars 229662 # Number of memory barriers committed +system.cpu0.commit.branches 4244821 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489354 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489334 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75566033 # The number of ROB reads -system.cpu0.rob.rob_writes 75750322 # The number of ROB writes -system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23599006 # Number of Instructions Simulated -system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated -system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads -system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads -system.cpu0.fp_regfile_writes 900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes -system.cpu0.icache.replacements 392871 # number of replacements -system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use -system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75534199 # The number of ROB reads +system.cpu0.rob.rob_writes 75722713 # The number of ROB writes +system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23597266 # Number of Instructions Simulated +system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated +system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads +system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads +system.cpu0.fp_regfile_writes 902 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes +system.cpu0.icache.replacements 392511 # number of replacements +system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use +system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits -system.cpu0.icache.overall_hits::total 3794104 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses -system.cpu0.icache.overall_misses::total 424196 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits +system.cpu0.icache.overall_hits::total 3789958 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses +system.cpu0.icache.overall_misses::total 423709 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30672 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30672 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30672 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30672 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30672 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30672 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393037 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393037 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393037 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393037 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393037 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276008 # number of replacements -system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 275921 # number of replacements +system.cpu0.dcache.tagsinuse 460.698692 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9260016 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276433 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.498229 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits -system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses -system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits +system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks -system.cpu0.dcache.writebacks::total 256612 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks +system.cpu0.dcache.writebacks::total 256512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1249,38 +1249,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9071093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits +system.cpu1.branchPred.lookups 9068423 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42899284 # DTB read hits -system.cpu1.dtb.read_misses 36667 # DTB read misses -system.cpu1.dtb.write_hits 6823776 # DTB write hits -system.cpu1.dtb.write_misses 10740 # DTB write misses +system.cpu1.dtb.read_hits 42898238 # DTB read hits +system.cpu1.dtb.read_misses 36741 # DTB read misses +system.cpu1.dtb.write_hits 6823025 # DTB write hits +system.cpu1.dtb.write_misses 10725 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42935951 # DTB read accesses -system.cpu1.dtb.write_accesses 6834516 # DTB write accesses +system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42934979 # DTB read accesses +system.cpu1.dtb.write_accesses 6833750 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49723060 # DTB hits -system.cpu1.dtb.misses 47407 # DTB misses -system.cpu1.dtb.accesses 49770467 # DTB accesses -system.cpu1.itb.inst_hits 8396614 # ITB inst hits -system.cpu1.itb.inst_misses 5496 # ITB inst misses +system.cpu1.dtb.hits 49721263 # DTB hits +system.cpu1.dtb.misses 47466 # DTB misses +system.cpu1.dtb.accesses 49768729 # DTB accesses +system.cpu1.itb.inst_hits 8394494 # ITB inst hits +system.cpu1.itb.inst_misses 5446 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1289,114 +1289,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses -system.cpu1.itb.hits 8396614 # DTB hits -system.cpu1.itb.misses 5496 # DTB misses -system.cpu1.itb.accesses 8402110 # DTB accesses -system.cpu1.numCycles 408759365 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses +system.cpu1.itb.hits 8394494 # DTB hits +system.cpu1.itb.misses 5446 # DTB misses +system.cpu1.itb.accesses 8399940 # DTB accesses +system.cpu1.numCycles 408755802 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1424,13 +1424,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued @@ -1443,11 +1443,11 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued @@ -1456,363 +1456,367 @@ system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Ty system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued -system.cpu1.iq.rate 0.218037 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued +system.cpu1.iq.rate 0.218023 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104622 # number of nop insts executed -system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7000416 # Number of branches executed -system.cpu1.iew.exec_stores 7109526 # Number of stores executed -system.cpu1.iew.exec_rate 0.212092 # Inst execution rate -system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29911901 # num instructions producing a value -system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value +system.cpu1.iew.exec_nop 104827 # number of nop insts executed +system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6999376 # Number of branches executed +system.cpu1.iew.exec_stores 7108814 # Number of stores executed +system.cpu1.iew.exec_rate 0.212079 # Inst execution rate +system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29908204 # num instructions producing a value +system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38058920 # Number of instructions committed -system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38058618 # Number of instructions committed +system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16590474 # Number of memory references committed -system.cpu1.commit.loads 9752596 # Number of loads committed -system.cpu1.commit.membars 190088 # Number of memory barriers committed -system.cpu1.commit.branches 5966646 # Number of branches committed +system.cpu1.commit.refs 16590369 # Number of memory references committed +system.cpu1.commit.loads 9752527 # Number of loads committed +system.cpu1.commit.membars 190082 # Number of memory barriers committed +system.cpu1.commit.branches 5966603 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534484 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534481 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172926580 # The number of ROB reads -system.cpu1.rob.rob_writes 131236338 # The number of ROB writes -system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37989281 # Number of Instructions Simulated -system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated -system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads +system.cpu1.rob.rob_reads 172920681 # The number of ROB reads +system.cpu1.rob.rob_writes 131224345 # The number of ROB writes +system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37988979 # Number of Instructions Simulated +system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated +system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads -system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes -system.cpu1.icache.replacements 596801 # number of replacements -system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use -system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. +system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads +system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes +system.cpu1.icache.replacements 596769 # number of replacements +system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use +system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits -system.cpu1.icache.overall_hits::total 7752714 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses -system.cpu1.icache.overall_misses::total 641884 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits +system.cpu1.icache.overall_hits::total 7750669 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses +system.cpu1.icache.overall_misses::total 641966 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076492 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13479.566661 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13479.566661 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2249 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.630303 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44655 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44655 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44655 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44655 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44655 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44655 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597311 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597311 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597311 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597311 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597311 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597311 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076959992 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076959992 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076959992 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7076959992 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076959992 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7076959992 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360372 # number of replacements -system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 360267 # number of replacements +system.cpu1.dcache.tagsinuse 474.654017 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12671092 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360637 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.135308 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94868 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12441592 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12441592 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12441592 # number of overall hits -system.cpu1.dcache.overall_hits::total 12441592 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 400129 # 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number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67909770997 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 474.654017 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927059 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927059 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8304151 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8304151 # 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number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1556589 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13972 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13972 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10605 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10605 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1955768 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1955768 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1955768 # number of overall misses +system.cpu1.dcache.overall_misses::total 1955768 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6101251500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6101251500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61874023496 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61874023496 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129109000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129109000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53792000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53792000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67975274996 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67975274996 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67975274996 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67975274996 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703330 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703330 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks -system.cpu1.dcache.writebacks::total 324455 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks +system.cpu1.dcache.writebacks::total 324294 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1834,18 +1838,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 814bf6bde..faf182914 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -630,6 +630,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index 3ee89fc27..eda827fb8 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index cc635c8e8..59b881f50 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 20:56:17 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 22:58:34 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2533147650000 because m5_exit instruction encountered +Exiting @ tick 2533144795000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 21b68a213..9b1cbcf2d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,128 +1,128 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.533144 # Number of seconds simulated -sim_ticks 2533143504000 # Number of ticks simulated -final_tick 2533143504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2533143973500 # Number of ticks simulated +final_tick 2533143973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80573 # Simulator instruction rate (inst/s) -host_op_rate 103675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3384348477 # Simulator tick rate (ticks/s) -host_mem_usage 408856 # Number of bytes of host memory used -host_seconds 748.49 # Real time elapsed on the host +host_inst_rate 64483 # Simulator instruction rate (inst/s) +host_op_rate 82972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2708528376 # Simulator tick rate (ticks/s) +host_mem_usage 405264 # Number of bytes of host memory used +host_seconds 935.25 # Real time elapsed on the host sim_insts 60307579 # Number of instructions simulated sim_ops 77599125 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 796736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093520 # Number of bytes read from this memory -system.physmem.bytes_read::total 129430672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 796736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3782592 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 796608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory +system.physmem.bytes_read::total 129430480 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796608 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3782336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6798664 # Number of bytes written to this memory +system.physmem.bytes_written::total 6798408 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142120 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096820 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59103 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 12447 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59099 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813121 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47189456 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813117 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47189447 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1061 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3589816 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51094883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314525 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1493240 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3589765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51094798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314474 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1493139 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1190644 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2683884 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1493240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47189456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2683783 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1493139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47189447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1061 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4780460 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096820 # Total number of read requests seen -system.physmem.writeReqs 813121 # Total number of write requests seen -system.physmem.cpureqs 218357 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966196480 # Total number of bytes read from memory -system.physmem.bytesWritten 52039744 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129430672 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6798664 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 314474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4780409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53778581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096817 # Total number of read requests seen +system.physmem.writeReqs 813117 # Total number of write requests seen +system.physmem.cpureqs 218351 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966196288 # Total number of bytes read from memory +system.physmem.bytesWritten 52039488 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129430480 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6798408 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 227 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4678 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943951 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4679 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943948 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 943440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943388 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 944196 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 943983 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943145 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 944197 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 943985 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 943146 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 943274 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943869 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943805 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943868 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943807 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943302 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943206 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 943616 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 943708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943088 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 942997 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943623 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50838 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 943622 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50409 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50438 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51152 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50435 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51153 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50912 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50279 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50800 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50900 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51241 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50709 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 50623 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2238337 # Number of times wr buffer was full causing retry -system.physmem.totGap 2533142364000 # Total gap between requests +system.physmem.totGap 2533142848500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154576 # Categorize read packet sizes +system.physmem.readPktSize::6 154573 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754018 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59103 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1040115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981189 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 950309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3550321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2676376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2687982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2649582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157630 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 108239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16713 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59099 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1040033 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 950276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3550309 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2676403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2688030 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2649604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108698 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 157635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 108246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 16712 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 16586 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 21915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 10858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 10857 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -139,8 +139,8 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2634 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 2677 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 2715 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 2739 # What write queue length does an incoming req see @@ -160,8 +160,8 @@ system.physmem.wrQLenPdf::17 35353 # Wh system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32771 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32719 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32676 # What write queue length does an incoming req see @@ -171,14 +171,14 @@ system.physmem.wrQLenPdf::28 32584 # Wh system.physmem.wrQLenPdf::29 32560 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32538 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see -system.physmem.totQLat 393245939250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 485641693000 # Sum of mem lat for all requests -system.physmem.totBusLat 75482965000 # Total cycles spent in databus access -system.physmem.totBankLat 16912788750 # Total cycles spent in bank access -system.physmem.avgQLat 26048.65 # Average queueing delay per request -system.physmem.avgBankLat 1120.31 # Average bank access latency per request +system.physmem.totQLat 393251142750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 485645877750 # Sum of mem lat for all requests +system.physmem.totBusLat 75482950000 # Total cycles spent in databus access +system.physmem.totBankLat 16911785000 # Total cycles spent in bank access +system.physmem.avgQLat 26049.00 # Average queueing delay per request +system.physmem.avgBankLat 1120.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32168.96 # Average memory access latency +system.physmem.avgMemAccLat 32169.24 # Average memory access latency system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s @@ -187,11 +187,11 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.14 # Data bus utilization in percentage system.physmem.avgRdQLen 0.19 # Average read queue length over time system.physmem.avgWrQLen 9.55 # Average write queue length over time -system.physmem.readRowHits 15020273 # Number of row buffer hits during reads -system.physmem.writeRowHits 793117 # Number of row buffer hits during writes +system.physmem.readRowHits 15020272 # Number of row buffer hits during reads +system.physmem.writeRowHits 793090 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes -system.physmem.avgGap 159217.58 # Average gap between requests +system.physmem.avgGap 159217.68 # Average gap between requests system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -210,38 +210,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14678084 # Number of BP lookups -system.cpu.branchPred.condPredicted 11764424 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 705314 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9806272 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7951789 # Number of BTB hits +system.cpu.branchPred.lookups 14675749 # Number of BP lookups +system.cpu.branchPred.condPredicted 11761615 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 705306 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9809113 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7951342 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.088807 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1399019 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 81.060765 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398937 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 72620 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51401633 # DTB read hits -system.cpu.dtb.read_misses 64365 # DTB read misses -system.cpu.dtb.write_hits 11702282 # DTB write hits -system.cpu.dtb.write_misses 15903 # DTB write misses +system.cpu.dtb.read_hits 51399217 # DTB read hits +system.cpu.dtb.read_misses 64403 # DTB read misses +system.cpu.dtb.write_hits 11701345 # DTB write hits +system.cpu.dtb.write_misses 15902 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3559 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2575 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 399 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3557 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2566 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 409 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1330 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51465998 # DTB read accesses -system.cpu.dtb.write_accesses 11718185 # DTB write accesses +system.cpu.dtb.perms_faults 1299 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51463620 # DTB read accesses +system.cpu.dtb.write_accesses 11717247 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63103915 # DTB hits -system.cpu.dtb.misses 80268 # DTB misses -system.cpu.dtb.accesses 63184183 # DTB accesses -system.cpu.itb.inst_hits 12333169 # ITB inst hits -system.cpu.itb.inst_misses 11311 # ITB inst misses +system.cpu.dtb.hits 63100562 # DTB hits +system.cpu.dtb.misses 80305 # DTB misses +system.cpu.dtb.accesses 63180867 # DTB accesses +system.cpu.itb.inst_hits 12332677 # ITB inst hits +system.cpu.itb.inst_misses 11271 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -250,113 +250,113 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2477 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2475 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2979 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2981 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 12344480 # ITB inst accesses -system.cpu.itb.hits 12333169 # DTB hits -system.cpu.itb.misses 11311 # DTB misses -system.cpu.itb.accesses 12344480 # DTB accesses -system.cpu.numCycles 471839315 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 12343948 # ITB inst accesses +system.cpu.itb.hits 12332677 # DTB hits +system.cpu.itb.misses 11271 # DTB misses +system.cpu.itb.accesses 12343948 # DTB accesses +system.cpu.numCycles 471840254 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30570275 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 96049459 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14678084 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9350808 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21162167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5300670 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 119262 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 95593563 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87521 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 195771 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 307 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 12329483 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 900673 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5698 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.785111 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.150333 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30570540 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 96039987 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14675749 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9350279 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21160212 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5300332 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 123049 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95587623 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 87979 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195754 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 322 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 12329197 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 900896 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5353 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.785063 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.150272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130222829 86.03% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1303268 0.86% 86.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1713149 1.13% 88.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2496945 1.65% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2215858 1.46% 91.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107759 0.73% 91.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2757122 1.82% 93.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 745476 0.49% 94.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8807292 5.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 130221030 86.03% 86.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1303083 0.86% 86.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1712964 1.13% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2496255 1.65% 89.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2215475 1.46% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1108052 0.73% 91.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2757455 1.82% 93.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 745629 0.49% 94.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8805968 5.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151369698 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031108 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.203564 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32533087 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 95216874 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19187667 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 962846 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3469224 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1957624 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171486 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 112641564 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 566291 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3469224 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34475717 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36705773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52523534 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18152425 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043025 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 106121315 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20520 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004083 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063852 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 110544866 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 485535846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 485445234 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90612 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 151365911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031103 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.203543 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32532272 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95215917 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19186051 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962874 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3468797 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957839 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171569 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 112632707 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 566700 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3468797 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 34474935 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36706470 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52522148 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18150584 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6042977 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 106114460 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20538 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4062916 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 612 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 110534596 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 485505463 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 485414558 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90905 # Number of floating rename lookups system.cpu.rename.CommittedMaps 78389874 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32154991 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830680 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 737251 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12167564 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 20329502 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13519419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1975005 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2483431 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97943833 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1983956 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 124335595 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 167777 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 21753420 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 57059209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 501571 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151369698 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.821403 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.534931 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 32144721 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737120 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12168217 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 20326621 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13518825 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978093 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2487494 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97939378 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983579 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 124329035 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167924 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 21751378 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 57069924 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501194 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151365911 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.821381 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.534880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 107127102 70.77% 70.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13547292 8.95% 79.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7070046 4.67% 84.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5943115 3.93% 88.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12603566 8.33% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2786171 1.84% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1700250 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 465001 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127155 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 107121434 70.77% 70.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13552589 8.95% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7069165 4.67% 84.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5942277 3.93% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12602111 8.33% 96.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2786608 1.84% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1699306 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 465403 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 127018 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151369698 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151365911 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60916 0.69% 0.69% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60927 0.69% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 2 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available @@ -385,13 +385,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8365801 94.64% 95.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 413031 4.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365559 94.64% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412870 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 58634354 47.16% 47.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93273 0.08% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 58631029 47.16% 47.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93272 0.08% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued @@ -407,7 +407,7 @@ system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued @@ -419,84 +419,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 18 0.00% 47.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52919784 42.56% 90.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12322346 9.91% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52917261 42.56% 90.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12321634 9.91% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 124335595 # Type of FU issued -system.cpu.iq.rate 0.263513 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8839750 # FU busy when requested +system.cpu.iq.FU_type_0::total 124329035 # Type of FU issued +system.cpu.iq.rate 0.263498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8839358 # FU busy when requested system.cpu.iq.fu_busy_rate 0.071096 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 409105295 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 121697619 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85975011 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23030 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12486 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10280 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 132799466 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12213 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 624029 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 409088132 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 121690697 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85968255 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23084 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12548 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10294 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 132792486 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12241 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623354 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4674977 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6508 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 4672096 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6462 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 30066 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1787339 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1786745 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107736 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 893802 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107738 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 893837 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3469224 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27949054 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 432986 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100148718 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 201036 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 20329502 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13519419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1411238 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 112362 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3588 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 3468797 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27950970 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 433267 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100144689 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 200366 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 20326621 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13518825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410950 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 112625 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3575 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 30066 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 350846 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269150 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 619996 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121555637 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52088672 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2779958 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 350763 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269062 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619825 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 121548947 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52086338 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2780088 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 220929 # number of nop insts executed -system.cpu.iew.exec_refs 64302587 # number of memory reference insts executed -system.cpu.iew.exec_branches 11562998 # Number of branches executed -system.cpu.iew.exec_stores 12213915 # Number of stores executed -system.cpu.iew.exec_rate 0.257621 # Inst execution rate -system.cpu.iew.wb_sent 120394624 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85985291 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47225460 # num instructions producing a value -system.cpu.iew.wb_consumers 88174567 # num instructions consuming a value +system.cpu.iew.exec_nop 221732 # number of nop insts executed +system.cpu.iew.exec_refs 64299340 # number of memory reference insts executed +system.cpu.iew.exec_branches 11561583 # Number of branches executed +system.cpu.iew.exec_stores 12213002 # Number of stores executed +system.cpu.iew.exec_rate 0.257606 # Inst execution rate +system.cpu.iew.wb_sent 120388158 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85978549 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47221894 # num instructions producing a value +system.cpu.iew.wb_consumers 88170402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182234 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535590 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535575 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 21490031 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 21486542 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1482385 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 536346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147900474 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.525688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.515007 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 536246 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 147897114 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.525700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.515001 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 120451739 81.44% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13317188 9.00% 90.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3905098 2.64% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2119368 1.43% 94.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1946193 1.32% 95.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 968094 0.65% 96.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1600636 1.08% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 702304 0.47% 98.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889854 1.95% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 120445936 81.44% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13320013 9.01% 90.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3904517 2.64% 93.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2120442 1.43% 94.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1947230 1.32% 95.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 967442 0.65% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1598856 1.08% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 701557 0.47% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2891121 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147900474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 147897114 # Number of insts commited each cycle system.cpu.commit.committedInsts 60457960 # Number of instructions committed system.cpu.commit.committedOps 77749506 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -507,261 +507,261 @@ system.cpu.commit.branches 9961316 # Nu system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. system.cpu.commit.int_insts 68854760 # Number of committed integer instructions. system.cpu.commit.function_calls 991257 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889854 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 2891121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 242401590 # The number of ROB reads -system.cpu.rob.rob_writes 202045449 # The number of ROB writes -system.cpu.timesIdled 1769758 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320469617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 242393474 # The number of ROB reads +system.cpu.rob.rob_writes 202038068 # The number of ROB writes +system.cpu.timesIdled 1769308 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320474343 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.quiesceCycles 4594364653 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu.committedInsts 60307579 # Number of Instructions Simulated system.cpu.committedOps 77599125 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 60307579 # Number of Instructions Simulated -system.cpu.cpi 7.823881 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.823881 # CPI: Total CPI of All Threads +system.cpu.cpi 7.823896 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.823896 # CPI: Total CPI of All Threads system.cpu.ipc 0.127814 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.127814 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 550352189 # number of integer regfile reads -system.cpu.int_regfile_writes 88467762 # number of integer regfile writes -system.cpu.fp_regfile_reads 8269 # number of floating regfile reads -system.cpu.fp_regfile_writes 2928 # number of floating regfile writes -system.cpu.misc_regfile_reads 30128398 # number of misc regfile reads +system.cpu.int_regfile_reads 550318447 # number of integer regfile reads +system.cpu.int_regfile_writes 88458212 # number of integer regfile writes +system.cpu.fp_regfile_reads 8290 # number of floating regfile reads +system.cpu.fp_regfile_writes 2932 # number of floating regfile writes +system.cpu.misc_regfile_reads 30125052 # number of misc regfile reads system.cpu.misc_regfile_writes 831890 # number of misc regfile writes -system.cpu.icache.replacements 979593 # number of replacements +system.cpu.icache.replacements 979629 # number of replacements system.cpu.icache.tagsinuse 511.615707 # Cycle average of tags in use -system.cpu.icache.total_refs 11270072 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 980105 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 11.498841 # Average number of references to valid blocks. +system.cpu.icache.total_refs 11269534 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980141 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 11.497870 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 511.615707 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999249 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999249 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 11270072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 11270072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 11270072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 11270072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 11270072 # number of overall hits -system.cpu.icache.overall_hits::total 11270072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1059286 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1059286 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1059286 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1059286 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1059286 # number of overall misses -system.cpu.icache.overall_misses::total 1059286 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13991116996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13991116996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13991116996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13991116996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13991116996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12329358 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12329358 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12329358 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12329358 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12329358 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.085916 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.085916 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.085916 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.085916 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.085916 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13208.063730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13208.063730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13208.063730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13208.063730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4509 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 11269534 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11269534 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11269534 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11269534 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11269534 # number of overall hits +system.cpu.icache.overall_hits::total 11269534 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059538 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059538 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059538 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059538 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059538 # number of overall misses +system.cpu.icache.overall_misses::total 1059538 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13993400496 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13993400496 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13993400496 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13993400496 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13993400496 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13993400496 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 12329072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 12329072 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 12329072 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 12329072 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 12329072 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 12329072 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085938 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085938 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085938 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085938 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085938 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085938 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.077515 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.077515 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.077515 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.077515 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.077515 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4855 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 308 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 305 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 14.639610 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 15.918033 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79147 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79147 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79147 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 79147 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 79147 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 79147 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980139 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 980139 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 980139 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 980139 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 980139 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 980139 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11380145996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11380145996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11380145996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11380145996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11380145996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11380145996 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79361 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79361 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79361 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79361 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79361 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79361 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980177 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980177 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980177 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980177 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980177 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980177 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11379164996 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11379164996 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11379164996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11379164996 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11379164996 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11379164996 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 7553500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.079496 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.079496 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.079496 # 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average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -770,8 +770,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59103 # number of writebacks -system.cpu.l2cache.writebacks::total 59103 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 59099 # number of writebacks +system.cpu.l2cache.writebacks::total 59099 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits @@ -781,98 +781,98 @@ system.cpu.l2cache.demand_mshr_hits::total 74 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 42 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12330 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10647 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23020 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10645 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 542440021 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 499891739 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1044944802 # number of ReadReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5073016629 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5073016629 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2463540 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5578018589 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6123071652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2519791 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93251 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 543887277 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5572159369 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6118603437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 542440021 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5578018589 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6123071652 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5079330 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002492267 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007571597 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903234989 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903234989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167002548267 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167007627597 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 26903237989 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 26903237989 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5079330 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905727256 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910806586 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026754 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 193905786256 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 193910865586 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026748 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015984 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986491 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986491 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.985825 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.985825 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.214286 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.214286 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541238 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.092637 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000779 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000190 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012594 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223333 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.092637 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541224 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.092645 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000800 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000191 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012592 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.092645 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44110.890268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46881.068846 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45420.799652 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 44000.650633 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46960.238516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 45398.827041 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38088.283961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38126.365322 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38126.365322 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60086.341463 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59995.023810 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46625.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44110.890268 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38739.132698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39168.838539 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 44000.650633 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38780.137162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39197.944113 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -882,161 +882,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643539 # number of replacements +system.cpu.dcache.replacements 643553 # number of replacements system.cpu.dcache.tagsinuse 511.992821 # Cycle average of tags in use -system.cpu.dcache.total_refs 21509590 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644051 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.397340 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 21507678 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 644065 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.393645 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 42249000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.992821 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999986 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13756144 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13756144 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7259539 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7259539 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 243175 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 243175 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 13754193 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13754193 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7259605 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7259605 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243146 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243146 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247602 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247602 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21015683 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21015683 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21015683 # number of overall hits -system.cpu.dcache.overall_hits::total 21015683 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737609 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737609 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2962812 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2962812 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13513 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13513 # number of LoadLockedReq misses +system.cpu.dcache.demand_hits::cpu.data 21013798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21013798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21013798 # number of overall hits +system.cpu.dcache.overall_hits::total 21013798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2962746 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2962746 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13508 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13508 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3700421 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3700421 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3700421 # number of overall misses -system.cpu.dcache.overall_misses::total 3700421 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9797923500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104330736229 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180578000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180578000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3700578 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700578 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700578 # number of overall misses +system.cpu.dcache.overall_misses::total 3700578 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9800700500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 104414938731 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180553500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180553500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 218000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 218000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 114128659729 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 114128659729 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 114128659729 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14493753 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14493753 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114215639231 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114215639231 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114215639231 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492025 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492025 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 10222351 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 10222351 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256688 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256688 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256654 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256654 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 247616 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247616 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24716104 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24716104 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24716104 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24716104 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050892 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289837 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052644 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052644 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 24714376 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714376 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714376 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714376 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050913 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289830 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052631 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052631 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149717 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149717 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149717 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149717 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.356765 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.356765 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35213.417601 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35213.417601 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13363.279805 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13363.279805 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.149734 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149734 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149734 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149734 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13283.105775 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13283.105775 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35242.622463 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35242.622463 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13366.412496 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13366.412496 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15571.428571 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15571.428571 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30842.074383 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30842.074383 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29695 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 17222 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2648 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30864.270185 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30864.270185 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 29973 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 17225 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2670 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 252 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.214124 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 68.341270 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.225843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 68.353175 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607840 # number of writebacks -system.cpu.dcache.writebacks::total 607840 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351729 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 351729 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2713855 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1338 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3065584 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3065584 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3065584 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385880 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385880 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248957 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248957 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks +system.cpu.dcache.writebacks::total 607832 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351946 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351946 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2713780 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1332 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065726 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3065726 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3065726 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385886 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385886 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248966 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248966 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12176 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12176 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634837 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634837 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634837 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4811592500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182885914 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141167000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141167000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634852 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634852 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634852 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4812474000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8188067914 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141180000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141180000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 190000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 190000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12994478414 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12994478414 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395775000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742499011 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138274011 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026624 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024354 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047431 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047431 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13000541914 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13000541914 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395833000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36742502511 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 219138335511 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024355 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047441 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047441 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025685 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025685 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12469.141961 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32868.671755 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.825462 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.825462 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025688 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025688 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12471.232437 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32888.297655 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11594.940867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11594.940867 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13571.428571 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13571.428571 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20468.999781 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20468.999781 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20478.067194 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20478.067194 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1058,10 +1058,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610747140 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610747140 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1229610747140 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1229610797601 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229610797601 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1229610797601 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index a9a41c46d..22443d9d9 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -773,6 +773,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index cb0094499..d1147fb64 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,167 +1,175 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401342 # Number of seconds simulated -sim_ticks 2401342466000 # Number of ticks simulated -final_tick 2401342466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401153 # Number of seconds simulated +sim_ticks 2401153455000 # Number of ticks simulated +final_tick 2401153455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 244723 # Simulator instruction rate (inst/s) -host_op_rate 314293 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9740625246 # Simulator tick rate (ticks/s) -host_mem_usage 401684 # Number of bytes of host memory used -host_seconds 246.53 # Real time elapsed on the host -sim_insts 60331304 # Number of instructions simulated -sim_ops 77482270 # Number of ops (including micro ops) simulated +host_inst_rate 200255 # Simulator instruction rate (inst/s) +host_op_rate 257182 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7970039029 # Simulator tick rate (ticks/s) +host_mem_usage 397936 # Number of bytes of host memory used +host_seconds 301.27 # Real time elapsed on the host +sim_insts 60331276 # Number of instructions simulated +sim_ops 77481997 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 501920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7085968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7085840 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 678208 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 178368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1313020 # Number of bytes read from this memory -system.physmem.bytes_read::total 124662764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 501920 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.inst 177920 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1312828 # Number of bytes read from this memory +system.physmem.bytes_read::total 124662252 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502176 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 178368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 765600 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3747328 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 177920 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 765408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746944 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory -system.physmem.bytes_written::total 6763144 # Number of bytes written to this memory +system.physmem.bytes_written::total 6762760 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14045 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110752 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110750 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10596 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10597 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20530 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512442 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58552 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2780 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20527 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512434 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58546 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814534 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 812500 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47818298 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2950836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2951015 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35530 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282451 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 546786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51913780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35527 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74278 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620864 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83059 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 551965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74098 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 546749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51917653 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35530 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74098 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318767 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560477 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620913 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83065 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 552008 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2816463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47818298 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3571700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3571928 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 35530 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365516 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1098750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54730181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12618170 # Total number of read requests seen -system.physmem.writeReqs 398699 # Total number of write requests seen -system.physmem.cpureqs 55066 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807562880 # Total number of bytes read from memory -system.physmem.bytesWritten 25516736 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102918908 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2643116 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 1 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2351 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789127 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788778 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788875 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789205 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789031 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788756 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788906 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788958 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788649 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788041 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788042 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788288 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788136 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788329 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788749 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24964 # Track writes on a per bank basis +system.physmem.bw_total::cpu2.inst 74098 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1098757 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54734116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12597264 # Total number of read requests seen +system.physmem.writeReqs 398689 # Total number of write requests seen +system.physmem.cpureqs 55044 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 806224896 # Total number of bytes read from memory +system.physmem.bytesWritten 25516096 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102751100 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2642476 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 787593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 787339 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 787599 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 787924 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 787752 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 787476 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 787626 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 787678 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 787361 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 786762 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 786761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 787020 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 787004 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 786857 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 787043 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 787469 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24766 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24768 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25057 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24742 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25296 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25174 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24837 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24743 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25297 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24838 # Track writes on a per bank basis system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24968 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24890 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25225 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24963 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24891 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400307249500 # Total gap between requests +system.physmem.totGap 2400118241500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::3 12562016 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35243 # Categorize read packet sizes +system.physmem.readPktSize::6 35233 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 381227 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17472 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 816053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260822 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249570 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91349 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6979 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6966 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17462 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 814730 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 790825 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 796437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2993221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2257059 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2257380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2245823 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91200 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6958 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6938 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,29 +186,29 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3012 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3011 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17322 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17312 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17303 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14405 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see @@ -209,320 +217,294 @@ system.physmem.wrQLenPdf::28 14353 # Wh system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see -system.physmem.totQLat 277225501500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 353051170250 # Sum of mem lat for all requests -system.physmem.totBusLat 63090845000 # Total cycles spent in databus access -system.physmem.totBankLat 12734823750 # Total cycles spent in bank access -system.physmem.avgQLat 21970.34 # Average queueing delay per request +system.physmem.totQLat 276742406750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 352442416750 # Sum of mem lat for all requests +system.physmem.totBusLat 62986320000 # Total cycles spent in databus access +system.physmem.totBankLat 12713690000 # Total cycles spent in bank access +system.physmem.avgQLat 21968.45 # Average queueing delay per request system.physmem.avgBankLat 1009.24 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27979.59 # Average memory access latency -system.physmem.avgRdBW 336.30 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27977.70 # Average memory access latency +system.physmem.avgRdBW 335.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.86 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.79 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563520 # Number of row buffer hits during reads -system.physmem.writeRowHits 392353 # Number of row buffer hits during writes +system.physmem.readRowHits 12542718 # Number of row buffer hits during reads +system.physmem.writeRowHits 392355 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184399.74 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 63278 # number of replacements -system.l2c.tagsinuse 50361.338948 # Cycle average of tags in use -system.l2c.total_refs 1750374 # Total number of references to valid blocks. -system.l2c.sampled_refs 128673 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.603273 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374434052500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36832.479753 # Average occupied blocks per requestor +system.physmem.avgGap 184681.97 # Average gap between requests +system.l2c.replacements 63270 # number of replacements +system.l2c.tagsinuse 50360.149873 # Cycle average of tags in use +system.l2c.total_refs 1749953 # Total number of references to valid blocks. +system.l2c.sampled_refs 128663 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.601059 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374435295000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36831.103707 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5142.503015 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3774.307963 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5142.534834 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3774.448687 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.237683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 747.699491 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 9.796874 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.itb.walker 0.004225 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1464.578885 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1588.737598 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562019 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu1.inst 800.238422 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.714108 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 9.797174 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1464.546789 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.772692 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.561998 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078468 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057591 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078469 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057594 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.011409 # Average percentage of cache occupancy system.l2c.occ_percent::cpu2.dtb.walker 0.000149 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022348 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024242 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768453 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 9023 # number of ReadReq hits +system.l2c.occ_percent::cpu2.inst 0.022347 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024243 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768435 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 9031 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461813 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 169129 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1136 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 133321 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 66093 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18237 # 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -686,27 +656,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8066281 # DTB read hits -system.cpu0.dtb.read_misses 6214 # DTB read misses -system.cpu0.dtb.write_hits 6622863 # DTB write hits -system.cpu0.dtb.write_misses 2042 # DTB write misses +system.cpu0.dtb.read_hits 8076292 # DTB read hits +system.cpu0.dtb.read_misses 6232 # DTB read misses +system.cpu0.dtb.write_hits 6627548 # DTB write hits +system.cpu0.dtb.write_misses 2039 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 695 # 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Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.749624 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 16.234496 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.932852 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034667 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.031708 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 477.646185 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.780881 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 16.177069 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.932903 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.034728 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.031596 # 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number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 135194 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287622 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 422816 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 135194 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287622 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 422816 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1553223000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3386037488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4939260488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1553223000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3386037488 # 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mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016057 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070888 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009350 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11681.820196 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11681.820196 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.845659 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11772.526052 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11681.820196 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 630049 # number of replacements +system.cpu0.dcache.replacements 629965 # number of replacements system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23214638 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630561 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.815848 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 23216121 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630477 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.823105 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.732545 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.762803 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.501768 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968228 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.019068 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012699 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.769504 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.745655 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.481956 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968300 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.019034 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012660 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6947999 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1896291 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4462491 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13306781 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5945013 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1350334 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2123860 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9419207 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131148 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34213 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72919 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238280 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137519 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35934 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73941 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247394 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12893012 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3246625 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6586351 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22725988 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12893012 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3246625 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6586351 # number of overall hits -system.cpu0.dcache.overall_hits::total 22725988 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169124 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65573 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 283564 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 518261 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167141 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29694 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 600320 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 797155 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6371 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1721 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # 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number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4087103500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5001080000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 729946000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18483212402 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19213158402 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22529500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52387500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74917000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1643922500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22570315902 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24214238402 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1643922500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22570315902 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24214238402 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7117123 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1961864 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4746055 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13825042 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6112154 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1380028 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2724180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_hits::cpu0.data 6957822 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1890811 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4457613 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13306246 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5949587 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1349737 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2121933 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9421257 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131174 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34256 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72800 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238230 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137548 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35976 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73869 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12907409 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3240548 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6579546 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22727503 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12907409 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3240548 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6579546 # number of overall hits +system.cpu0.dcache.overall_hits::total 22727503 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169428 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 65419 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 282959 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 517806 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167221 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29767 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 598117 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 795105 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6374 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1720 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3877 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11971 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 3 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336649 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 95186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 881076 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1312911 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336649 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 95186 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 881076 # number of overall misses +system.cpu0.dcache.overall_misses::total 1312911 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 911962500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4076352000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4988314500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 730880500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18449241407 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19180121907 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22516000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52369500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74885500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 39000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1642843000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22525593407 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24168436407 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1642843000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22525593407 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24168436407 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7127250 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1956230 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4740572 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13824052 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6116808 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1379504 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2720050 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137519 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35934 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76794 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250247 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35934 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73943 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137548 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35976 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76677 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250201 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137548 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35976 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73872 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 247396 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13229277 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3341892 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7470235 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24041404 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13229277 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3341892 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7470235 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24041404 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023763 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033424 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059747 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037487 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027346 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021517 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220367 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078027 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046328 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047893 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050460 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047821 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025418 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028507 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118321 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054715 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025418 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028507 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118321 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054715 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13938.305400 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.337024 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9649.732471 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24582.272513 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30788.933239 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 24102.161314 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.935503 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13519.354839 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6260.299156 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13244058 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3335734 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7460622 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24040414 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13244058 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3335734 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7460622 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24040414 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023772 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033441 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059689 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037457 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027338 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021578 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.219892 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077827 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046340 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047810 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050563 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047846 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000041 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025419 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028535 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118097 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054613 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025419 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028535 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118097 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054613 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13940.330791 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.157783 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9633.558707 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24553.381261 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30845.539262 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 24122.753482 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.697674 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13507.737942 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6255.575975 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17255.949069 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25535.382360 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18408.046125 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17255.949069 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25535.382360 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18408.046125 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9020 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1069 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1100 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 51 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.200000 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 20.960784 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18408.282364 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18408.282364 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9007 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1035 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1102 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 47 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.173321 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 22.021277 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597703 # number of writebacks -system.cpu0.dcache.writebacks::total 597703 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146204 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 146204 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 547277 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 547277 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 408 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 408 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 693481 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 693481 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 693481 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 693481 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65573 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137360 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202933 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29694 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53043 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82737 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1721 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3467 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5188 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 95267 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 190403 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 285670 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 95267 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 190403 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 285670 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 782830500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1785427500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568258000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 670558000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1431904990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2102462990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19087500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40642000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59729500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1453388500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3217332490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4670720990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1453388500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3217332490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4670720990 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27581235500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28989086000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56570321500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1280021500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14116548125 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396569625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861257000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43105634125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71966891125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033424 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028942 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014679 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021517 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019471 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008098 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047893 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045147 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020732 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011882 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028507 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025488 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011882 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11938.305400 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12998.161765 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.694244 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22582.272513 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26995.173538 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25411.399857 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.935503 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11722.526680 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11513.010794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597677 # number of writebacks +system.cpu0.dcache.writebacks::total 597677 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145837 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 145837 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 545226 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 545226 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 406 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 691063 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691063 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 691063 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691063 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65419 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137122 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202541 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29767 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52891 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82658 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1720 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3471 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5191 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 95186 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 190013 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285199 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 95186 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190013 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285199 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 781124500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1779796500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2560921000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 671346500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1430416990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2101763490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19076000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40648000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59724000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1452471000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3210213490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4662684490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1452471000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3210213490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4662684490 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27580693500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009829000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56590522500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281089000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14115638625 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396727625 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861782500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43125467625 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71987250125 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028925 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014651 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021578 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019445 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008091 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047810 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020747 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011863 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011863 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11940.330791 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.656802 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12643.963444 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22553.381261 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27044.619879 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25427.224104 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.697674 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11710.746183 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11505.297631 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15255.949069 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16897.488432 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16350.057724 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1128,27 +1098,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2177390 # DTB read hits -system.cpu1.dtb.read_misses 2104 # DTB read misses -system.cpu1.dtb.write_hits 1466734 # DTB write hits -system.cpu1.dtb.write_misses 391 # DTB write misses +system.cpu1.dtb.read_hits 2171794 # DTB read hits +system.cpu1.dtb.read_misses 2101 # DTB read misses +system.cpu1.dtb.write_hits 1466259 # DTB write hits +system.cpu1.dtb.write_misses 389 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1711 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 40 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2179494 # DTB read accesses -system.cpu1.dtb.write_accesses 1467125 # DTB write accesses +system.cpu1.dtb.read_accesses 2173895 # DTB read accesses +system.cpu1.dtb.write_accesses 1466648 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3644124 # DTB hits -system.cpu1.dtb.misses 2495 # DTB misses -system.cpu1.dtb.accesses 3646619 # DTB accesses -system.cpu1.itb.inst_hits 8441472 # ITB inst hits -system.cpu1.itb.inst_misses 1131 # ITB inst misses +system.cpu1.dtb.hits 3638053 # DTB hits +system.cpu1.dtb.misses 2490 # DTB misses +system.cpu1.dtb.accesses 3640543 # DTB accesses +system.cpu1.itb.inst_hits 8419414 # ITB inst hits +system.cpu1.itb.inst_misses 1129 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1157,73 +1127,73 @@ system.cpu1.itb.flush_tlb 277 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 829 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8442603 # ITB inst accesses -system.cpu1.itb.hits 8441472 # DTB hits -system.cpu1.itb.misses 1131 # DTB misses -system.cpu1.itb.accesses 8442603 # DTB accesses -system.cpu1.numCycles 574629535 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8420543 # ITB inst accesses +system.cpu1.itb.hits 8419414 # DTB hits +system.cpu1.itb.misses 1129 # DTB misses +system.cpu1.itb.accesses 8420543 # DTB accesses +system.cpu1.numCycles 574251142 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8231527 # Number of instructions committed -system.cpu1.committedOps 10483049 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9384758 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses -system.cpu1.num_func_calls 317840 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1148947 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9384758 # number of integer instructions -system.cpu1.num_fp_insts 1998 # number of float instructions -system.cpu1.num_int_register_reads 54113079 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10168310 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read +system.cpu1.committedInsts 8213191 # Number of instructions committed +system.cpu1.committedOps 10466435 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9372254 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses +system.cpu1.num_func_calls 317964 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1146067 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9372254 # number of integer instructions +system.cpu1.num_fp_insts 2062 # number of float instructions +system.cpu1.num_int_register_reads 54024867 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10146423 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3817736 # number of memory refs -system.cpu1.num_load_insts 2273251 # Number of load instructions -system.cpu1.num_store_insts 1544485 # Number of store instructions -system.cpu1.num_idle_cycles 533738024.963358 # Number of idle cycles -system.cpu1.num_busy_cycles 40891510.036642 # Number of busy cycles -system.cpu1.not_idle_fraction 0.071162 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.928838 # Percentage of idle cycles +system.cpu1.num_mem_refs 3811897 # number of memory refs +system.cpu1.num_load_insts 2267853 # Number of load instructions +system.cpu1.num_store_insts 1544044 # Number of store instructions +system.cpu1.num_idle_cycles 537580210.089888 # Number of idle cycles +system.cpu1.num_busy_cycles 36670931.910112 # Number of busy cycles +system.cpu1.not_idle_fraction 0.063859 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.936141 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4718167 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3836083 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222496 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3137475 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2530778 # Number of BTB hits +system.cpu2.branchPred.lookups 4709991 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3829375 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 221875 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3139297 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2527298 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.662890 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410861 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21436 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.505221 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 410694 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21534 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10866526 # DTB read hits -system.cpu2.dtb.read_misses 22717 # DTB read misses -system.cpu2.dtb.write_hits 3271799 # DTB write hits -system.cpu2.dtb.write_misses 5746 # DTB write misses +system.cpu2.dtb.read_hits 10865348 # DTB read hits +system.cpu2.dtb.read_misses 22611 # DTB read misses +system.cpu2.dtb.write_hits 3267482 # DTB write hits +system.cpu2.dtb.write_misses 5780 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 908 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 162 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 877 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 154 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 438 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10889243 # DTB read accesses -system.cpu2.dtb.write_accesses 3277545 # DTB write accesses +system.cpu2.dtb.perms_faults 449 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10887959 # DTB read accesses +system.cpu2.dtb.write_accesses 3273262 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14138325 # DTB hits -system.cpu2.dtb.misses 28463 # DTB misses -system.cpu2.dtb.accesses 14166788 # DTB accesses -system.cpu2.itb.inst_hits 4062010 # ITB inst hits -system.cpu2.itb.inst_misses 4544 # ITB inst misses +system.cpu2.dtb.hits 14132830 # DTB hits +system.cpu2.dtb.misses 28391 # DTB misses +system.cpu2.dtb.accesses 14161221 # DTB accesses +system.cpu2.itb.inst_hits 4058794 # ITB inst hits +system.cpu2.itb.inst_misses 4496 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1232,114 +1202,114 @@ system.cpu2.itb.flush_tlb 276 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1576 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1567 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 990 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1061 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4066554 # ITB inst accesses -system.cpu2.itb.hits 4062010 # DTB hits -system.cpu2.itb.misses 4544 # DTB misses -system.cpu2.itb.accesses 4066554 # DTB accesses -system.cpu2.numCycles 88259424 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4063290 # ITB inst accesses +system.cpu2.itb.hits 4058794 # DTB hits +system.cpu2.itb.misses 4496 # DTB misses +system.cpu2.itb.accesses 4063290 # DTB accesses +system.cpu2.numCycles 88265633 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9446644 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32376030 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4718167 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2941639 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6823560 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1815993 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51150 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19328654 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 814 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 980 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33196 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57154 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 380 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4060600 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 310025 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2087 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36989038 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050362 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436921 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9438008 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32342862 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4709991 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2937992 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6815885 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1813158 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 52200 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19319240 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 990 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33528 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57014 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 272 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4057414 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 309972 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1938 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36961797 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050032 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436638 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30170666 81.57% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382975 1.04% 82.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 509806 1.38% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812610 2.20% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 650446 1.76% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344174 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1009971 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 238143 0.64% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2870247 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30150982 81.57% 81.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 382433 1.03% 82.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 508858 1.38% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812110 2.20% 86.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 648973 1.76% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344473 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1008779 2.73% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 237853 0.64% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2867336 7.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36989038 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053458 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.366828 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10060365 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19264823 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6175765 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 293250 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1193736 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 611236 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 54016 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36687044 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 183513 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1193736 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10634106 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6560148 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11167231 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5875066 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1557700 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34442910 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2428 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 416233 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 878364 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 86 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36942900 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157448988 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157420907 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 28081 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25732227 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11210672 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231165 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207502 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3338949 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6517311 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3844285 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 533485 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 782358 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31699556 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 512260 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34239526 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54408 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7411685 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19905699 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155950 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36989038 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925667 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.579936 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36961797 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053362 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.366426 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10050266 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19257143 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6169060 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 292369 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1191852 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 610072 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53860 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36648451 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 182697 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1191852 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10623039 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6559507 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11162234 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5869128 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1554979 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34406679 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2425 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 416595 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 876326 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 106 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36902595 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157291448 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157264010 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27438 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25708511 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11194083 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 230845 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207258 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3329183 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6509687 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3839458 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 526321 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 767723 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31666176 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511259 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34215654 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53951 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7402351 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19875920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155450 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36961797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925703 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.580463 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24424083 66.03% 66.03% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3914413 10.58% 76.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2344925 6.34% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1979398 5.35% 88.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782245 7.52% 95.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 897303 2.43% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 479565 1.30% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 132664 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34442 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24411546 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3907285 10.57% 76.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2341872 6.34% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974558 5.34% 88.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782177 7.53% 95.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 896473 2.43% 98.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 480042 1.30% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133126 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34718 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36989038 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36961797 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16741 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16658 1.09% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -1368,148 +1338,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1406719 91.75% 92.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109821 7.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407260 91.71% 92.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110601 7.21% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61341 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19346638 56.50% 56.68% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25970 0.08% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.76% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11366450 33.20% 89.96% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3438720 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61295 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19329502 56.49% 56.67% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25951 0.08% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 9 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 376 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11364260 33.21% 89.96% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3434245 10.04% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34239526 # Type of FU issued -system.cpu2.iq.rate 0.387942 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1533281 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044781 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107077115 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39628603 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27373114 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7012 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3867 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3171 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35707743 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3723 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207144 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34215654 # Type of FU issued +system.cpu2.iq.rate 0.387644 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534519 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044848 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107003021 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39584963 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27346219 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6827 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3771 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3100 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35685269 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3609 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207108 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1578939 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1781 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9287 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 581487 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1576105 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1884 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9268 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 580803 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5366547 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352710 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5370889 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352686 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1193736 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4865575 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91265 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32289220 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60072 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6517311 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3844285 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 370110 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31382 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2364 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9287 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105801 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88656 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 194457 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33253955 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11078248 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 985571 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1191852 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4868557 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91379 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32255245 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 59750 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6509687 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3839458 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 369212 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31393 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2360 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9268 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105822 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88057 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 193879 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33230591 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11076582 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 985063 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 77404 # number of nop insts executed -system.cpu2.iew.exec_refs 14484069 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3693959 # Number of branches executed -system.cpu2.iew.exec_stores 3405821 # Number of stores executed -system.cpu2.iew.exec_rate 0.376775 # Inst execution rate -system.cpu2.iew.wb_sent 32835376 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27376285 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15639881 # num instructions producing a value -system.cpu2.iew.wb_consumers 28443914 # num instructions consuming a value +system.cpu2.iew.exec_nop 77810 # number of nop insts executed +system.cpu2.iew.exec_refs 14478078 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3688656 # Number of branches executed +system.cpu2.iew.exec_stores 3401496 # Number of stores executed +system.cpu2.iew.exec_rate 0.376484 # Inst execution rate +system.cpu2.iew.wb_sent 32812407 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27349319 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15625261 # num instructions producing a value +system.cpu2.iew.wb_consumers 28412503 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.310180 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549850 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309852 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549943 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7353370 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356310 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 169242 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35795177 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.689030 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.716377 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7344146 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 355809 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 168786 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35769820 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.688862 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.716544 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27161144 75.88% 75.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4182796 11.69% 87.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1257934 3.51% 91.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 650072 1.82% 92.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 572405 1.60% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318145 0.89% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 398611 1.11% 96.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 289517 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 964553 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27147085 75.89% 75.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4176329 11.68% 87.57% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1256730 3.51% 91.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 649005 1.81% 92.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 570906 1.60% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 316592 0.89% 95.38% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 399111 1.12% 96.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 290067 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 963995 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35795177 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19948032 # Number of instructions committed -system.cpu2.commit.committedOps 24663934 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35769820 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19931262 # Number of instructions committed +system.cpu2.commit.committedOps 24640483 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8201170 # Number of memory references committed -system.cpu2.commit.loads 4938372 # Number of loads committed -system.cpu2.commit.membars 94284 # Number of memory barriers committed -system.cpu2.commit.branches 3159330 # Number of branches committed -system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21896584 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294432 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 964553 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8192237 # Number of memory references committed +system.cpu2.commit.loads 4933582 # Number of loads committed +system.cpu2.commit.membars 94126 # Number of memory barriers committed +system.cpu2.commit.branches 3155533 # Number of branches committed +system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21875712 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294009 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 963995 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66322359 # The number of ROB reads -system.cpu2.rob.rob_writes 65269716 # The number of ROB writes -system.cpu2.timesIdled 360610 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51270386 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567282777 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19896304 # Number of Instructions Simulated -system.cpu2.committedOps 24612206 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19896304 # Number of Instructions Simulated -system.cpu2.cpi 4.435971 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.435971 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.225430 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.225430 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153619479 # number of integer regfile reads -system.cpu2.int_regfile_writes 29201382 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22411 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20842 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9012056 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240747 # number of misc regfile writes +system.cpu2.rob.rob_reads 66266303 # The number of ROB reads +system.cpu2.rob.rob_writes 65202475 # The number of ROB writes +system.cpu2.timesIdled 360564 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51303836 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567277023 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19879493 # Number of Instructions Simulated +system.cpu2.committedOps 24588714 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19879493 # Number of Instructions Simulated +system.cpu2.cpi 4.440034 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.440034 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.225223 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.225223 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153509449 # number of integer regfile reads +system.cpu2.int_regfile_writes 29174173 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22340 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20840 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9001304 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240409 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1524,10 +1494,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981147786186 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981147786186 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981147786186 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981147786186 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 979501914046 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 979501914046 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 979501914046 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 979501914046 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index 9fab0b34a..4166fc5d7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.physmem system.realview.nvmem +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1029,6 +1029,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 73a40b4c9..8c9cf8058 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,148 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.541289 # Number of seconds simulated -sim_ticks 2541288973500 # Number of ticks simulated -final_tick 2541288973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.541288 # Number of seconds simulated +sim_ticks 2541288206500 # Number of ticks simulated +final_tick 2541288206500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61532 # Simulator instruction rate (inst/s) -host_op_rate 79175 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2592785663 # Simulator tick rate (ticks/s) -host_mem_usage 411940 # Number of bytes of host memory used -host_seconds 980.14 # Real time elapsed on the host -sim_insts 60309889 # Number of instructions simulated -sim_ops 77602313 # Number of ops (including micro ops) simulated +host_inst_rate 64704 # Simulator instruction rate (inst/s) +host_op_rate 83256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2726411009 # Simulator tick rate (ticks/s) +host_mem_usage 408332 # Number of bytes of host memory used +host_seconds 932.10 # Real time elapsed on the host +sim_insts 60310239 # Number of instructions simulated +sim_ops 77602695 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 501184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4156432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 298496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4937244 # Number of bytes read from this memory -system.physmem.bytes_read::total 131006380 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 501184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 298496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799680 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784960 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1345340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1670772 # Number of bytes written to this memory -system.physmem.bytes_written::total 6801072 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4160720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 298048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4933980 # Number of bytes read from this memory +system.physmem.bytes_read::total 131009132 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503232 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 298048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 801280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3786176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1345260 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1670852 # Number of bytes written to this memory +system.physmem.bytes_written::total 6802288 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7831 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64978 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77151 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293479 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59140 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 336335 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 417693 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813168 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47657126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 197216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1635561 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 117459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1942811 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51551154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 197216 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 117459 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314675 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529393 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 657451 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2676229 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47657126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 630 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 197216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2164953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 117459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2600262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54227384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293479 # Total number of read requests seen -system.physmem.writeReqs 813168 # Total number of write requests seen -system.physmem.cpureqs 218447 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978782656 # Total number of bytes read from memory -system.physmem.bytesWritten 52042752 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131006380 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6801072 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 10 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4687 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956234 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 955730 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955668 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956486 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956267 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955440 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955563 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956167 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955610 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 955926 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956037 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955427 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955317 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50432 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51159 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50913 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50185 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50857 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50902 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51249 # Track writes on a per bank basis +system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7863 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 65045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4657 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 77100 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293522 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 336315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 417713 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813187 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47657140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 198022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1637248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 117282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1941527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51552253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 198022 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 117282 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315305 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489865 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 657482 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2676709 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489865 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47657140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 198022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2166610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 117282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2599009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54228961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293522 # Total number of read requests seen +system.physmem.writeReqs 813187 # Total number of write requests seen +system.physmem.cpureqs 218489 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978785408 # Total number of bytes read from memory +system.physmem.bytesWritten 52043968 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131009132 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6802288 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4667 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956238 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 955736 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955671 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956488 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955445 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956169 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956096 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955614 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955529 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 955925 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955982 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50430 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51154 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50910 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50187 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51363 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50809 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51186 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51250 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 50729 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51233 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50633 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1856346 # Number of times wr buffer was full causing retry -system.physmem.totGap 2541287786000 # Total gap between requests +system.physmem.numWrRetry 1856598 # Number of times wr buffer was full causing retry +system.physmem.totGap 2541287063000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154620 # Categorize read packet sizes +system.physmem.readPktSize::6 154663 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59140 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 992061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3604876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718031 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2698984 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 60219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109990 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109908 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9982 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 11017 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59159 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054970 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 992041 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961924 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3604913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718058 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2698919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 60155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59416 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160422 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109940 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10954 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -156,46 +168,46 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2749 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2934 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2910 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35358 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35346 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35291 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 35277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32510 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32476 # What write queue length does an incoming req see -system.physmem.totQLat 346721486500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 439895947750 # Sum of mem lat for all requests -system.physmem.totBusLat 76467345000 # Total cycles spent in databus access -system.physmem.totBankLat 16707116250 # Total cycles spent in bank access -system.physmem.avgQLat 22671.21 # Average queueing delay per request +system.physmem.wrQLenPdf::18 35258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32493 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32483 # What write queue length does an incoming req see +system.physmem.totQLat 346675714750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 439850413500 # Sum of mem lat for all requests +system.physmem.totBusLat 76467555000 # Total cycles spent in databus access +system.physmem.totBankLat 16707143750 # Total cycles spent in bank access +system.physmem.avgQLat 22668.16 # Average queueing delay per request system.physmem.avgBankLat 1092.43 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28763.65 # Average memory access latency +system.physmem.avgMemAccLat 28760.59 # Average memory access latency system.physmem.avgRdBW 385.15 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.48 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.55 # Average consumed read bandwidth in MB/s @@ -203,243 +215,235 @@ system.physmem.avgConsumedWrBW 2.68 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.13 # Average write queue length over time -system.physmem.readRowHits 15218362 # Number of row buffer hits during reads -system.physmem.writeRowHits 794635 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.14 # Average write queue length over time +system.physmem.readRowHits 15218363 # Number of row buffer hits during reads +system.physmem.writeRowHits 794663 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.025787 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015847 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988372 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988448 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.988408 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.083333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.508840 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.571050 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.541281 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.091706 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015540 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.195537 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009602 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.253689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.091706 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44257.251609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46034.955512 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44333.289689 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10073.116484 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10034.874398 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39806.414207 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.888795 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38419.733648 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55440.960000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.991831 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40212.673043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45442.026587 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37786.741539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39283.448356 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10052.097882 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.130045 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39846.195494 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37287.299468 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38438.418461 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 55825 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49834 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42636.911028 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40251.394129 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81932.818182 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45410.372343 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37804.827188 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39309.990960 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -622,155 +634,155 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7614306 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6072650 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 380012 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4955572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4051897 # Number of BTB hits +system.cpu0.branchPred.lookups 7613725 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6072642 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 379429 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4956500 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4052223 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.764466 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 730604 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39458 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.755735 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731018 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39412 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26054511 # DTB read hits -system.cpu0.dtb.read_misses 40169 # DTB read misses -system.cpu0.dtb.write_hits 5887052 # DTB write hits -system.cpu0.dtb.write_misses 9355 # DTB write misses +system.cpu0.dtb.read_hits 26054269 # DTB read hits +system.cpu0.dtb.read_misses 40148 # DTB read misses +system.cpu0.dtb.write_hits 5888543 # DTB write hits +system.cpu0.dtb.write_misses 9328 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5627 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1395 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5631 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1467 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 272 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26094680 # DTB read accesses -system.cpu0.dtb.write_accesses 5896407 # DTB write accesses +system.cpu0.dtb.perms_faults 635 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26094417 # DTB read accesses +system.cpu0.dtb.write_accesses 5897871 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31941563 # DTB hits -system.cpu0.dtb.misses 49524 # DTB misses -system.cpu0.dtb.accesses 31991087 # DTB accesses -system.cpu0.itb.inst_hits 6108612 # ITB inst hits -system.cpu0.itb.inst_misses 7590 # ITB inst misses +system.cpu0.dtb.hits 31942812 # DTB hits +system.cpu0.dtb.misses 49476 # DTB misses +system.cpu0.dtb.accesses 31992288 # DTB accesses +system.cpu0.itb.inst_hits 6107608 # ITB inst hits +system.cpu0.itb.inst_misses 7459 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 771 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 772 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2620 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1574 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1567 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6116202 # ITB inst accesses -system.cpu0.itb.hits 6108612 # DTB hits -system.cpu0.itb.misses 7590 # DTB misses -system.cpu0.itb.accesses 6116202 # DTB accesses -system.cpu0.numCycles 239083473 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6115067 # ITB inst accesses +system.cpu0.itb.hits 6107608 # DTB hits +system.cpu0.itb.misses 7459 # DTB misses +system.cpu0.itb.accesses 6115067 # DTB accesses +system.cpu0.numCycles 239065725 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15485568 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 47808985 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7614306 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4782501 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10601732 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2558486 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 88790 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49524477 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1650 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 49879 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101149 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 238 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6106475 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 397023 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3536 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77625046 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.761902 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.119269 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15475182 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47810378 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7613725 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4783241 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10599303 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2556412 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 92588 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49524214 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1680 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1986 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51259 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101215 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 252 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6105640 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 396425 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3088 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77615764 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762044 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119690 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67030834 86.35% 86.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 688188 0.89% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 885369 1.14% 88.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1227712 1.58% 89.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1142460 1.47% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 576598 0.74% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1323002 1.70% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 397300 0.51% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4353583 5.61% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67024086 86.35% 86.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 687549 0.89% 87.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 884780 1.14% 88.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1227446 1.58% 89.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1139052 1.47% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576391 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1322616 1.70% 93.88% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 397461 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4356383 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77625046 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 77615764 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.031848 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.199968 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16533020 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49254882 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9604301 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 549145 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1681530 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1023916 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 90477 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56278023 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 301850 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1681530 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17466172 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18987810 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27019642 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9149380 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3318436 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53462165 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13485 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 622165 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2153440 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 547 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 55626962 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 243359254 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 243311426 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 47828 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40393377 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15233585 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 429285 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 381212 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6745205 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10341737 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6773194 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1063883 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1311451 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 49606690 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1043899 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63171257 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 95885 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10502922 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26495317 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 267486 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77625046 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.813800 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519198 # Number of insts issued each cycle +system.cpu0.fetch.rate 0.199988 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16521961 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49260251 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9602479 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 548826 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1680126 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1023427 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 90450 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56271590 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 301516 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1680126 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17454704 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18993172 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27018669 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9147780 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3319243 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53454491 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13507 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 621630 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2155035 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 566 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55623215 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 243327513 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243280007 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 47506 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40387894 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15235321 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429274 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381163 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6745844 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10343403 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6774259 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1062911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1310407 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49609262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043693 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63170275 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 95774 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10510467 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26507766 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 267313 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77615764 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813885 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519252 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 54791410 70.58% 70.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7205110 9.28% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3690427 4.75% 84.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3148985 4.06% 88.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6276259 8.09% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1405987 1.81% 98.57% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 810578 1.04% 99.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 230421 0.30% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 65869 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54780189 70.58% 70.58% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7210578 9.29% 79.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3685843 4.75% 84.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3149398 4.06% 88.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6278761 8.09% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1404530 1.81% 98.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 809241 1.04% 99.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 231115 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 66109 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77625046 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77615764 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 29841 0.67% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 2 0.00% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 29823 0.67% 0.67% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 3 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.67% # attempts to use FU when none available @@ -798,13 +810,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.67% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.67% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4229016 94.75% 95.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 204408 4.58% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4228133 94.76% 95.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 204148 4.58% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 195533 0.31% 0.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 29939610 47.39% 47.70% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46892 0.07% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195616 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29937335 47.39% 47.70% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46928 0.07% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.78% # Type of FU issued @@ -817,485 +829,485 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.78% # Ty system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1207 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1205 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 47.78% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 47.78% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26772486 42.38% 90.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6215505 9.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26771956 42.38% 90.16% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6217218 9.84% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63171257 # Type of FU issued -system.cpu0.iq.rate 0.264223 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4463267 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070653 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 208563844 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61162491 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44139446 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12207 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6555 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5480 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67432539 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6452 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 322060 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63170275 # Type of FU issued +system.cpu0.iq.rate 0.264238 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4462107 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070636 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208551330 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61172484 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44142185 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12154 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6481 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5464 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67430354 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6412 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323195 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2267012 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3473 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16117 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 886206 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2268860 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3534 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16121 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 886667 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17168110 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367587 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17166750 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367684 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1681530 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14225625 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 233605 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50767973 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 106118 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10341737 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6773194 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 742853 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 56514 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3354 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16117 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 186814 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 146956 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 333770 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62000418 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26414197 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1170839 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1680126 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14230285 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 233349 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50770143 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 105944 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10343403 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6774259 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742754 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3335 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16121 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 186307 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 146952 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 333259 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62002420 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26414016 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1167855 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117384 # number of nop insts executed -system.cpu0.iew.exec_refs 32572588 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6026978 # Number of branches executed -system.cpu0.iew.exec_stores 6158391 # Number of stores executed -system.cpu0.iew.exec_rate 0.259325 # Inst execution rate -system.cpu0.iew.wb_sent 61472286 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44144926 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24307807 # num instructions producing a value -system.cpu0.iew.wb_consumers 44674584 # num instructions consuming a value +system.cpu0.iew.exec_nop 117188 # number of nop insts executed +system.cpu0.iew.exec_refs 32573974 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6027717 # Number of branches executed +system.cpu0.iew.exec_stores 6159958 # Number of stores executed +system.cpu0.iew.exec_rate 0.259353 # Inst execution rate +system.cpu0.iew.wb_sent 61473665 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44147649 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24301400 # num instructions producing a value +system.cpu0.iew.wb_consumers 44653762 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.184642 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.544108 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.184667 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544218 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10350620 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 776413 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 290797 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 75943516 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.525572 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.508217 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10356873 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 776380 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 290234 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 75935638 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525589 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.508198 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61731521 81.29% 81.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6903711 9.09% 90.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2039504 2.69% 93.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1132941 1.49% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1032773 1.36% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 549051 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702703 0.93% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 370837 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1480475 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61722766 81.28% 81.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6904437 9.09% 90.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2039889 2.69% 93.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1134781 1.49% 94.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1032872 1.36% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 547307 0.72% 96.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 702356 0.92% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 369637 0.49% 98.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1481593 1.95% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 75943516 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31268406 # Number of instructions committed -system.cpu0.commit.committedOps 39913766 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 75935638 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31265183 # Number of instructions committed +system.cpu0.commit.committedOps 39910920 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13961713 # Number of memory references committed -system.cpu0.commit.loads 8074725 # Number of loads committed -system.cpu0.commit.membars 212370 # Number of memory barriers committed -system.cpu0.commit.branches 5203416 # Number of branches committed +system.cpu0.commit.refs 13962135 # Number of memory references committed +system.cpu0.commit.loads 8074543 # Number of loads committed +system.cpu0.commit.membars 212305 # Number of memory barriers committed +system.cpu0.commit.branches 5202337 # Number of branches committed system.cpu0.commit.fp_insts 5433 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35263906 # Number of committed integer instructions. -system.cpu0.commit.function_calls 513958 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1480475 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 35261936 # Number of committed integer instructions. +system.cpu0.commit.function_calls 513908 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1481593 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 123750130 # The number of ROB reads -system.cpu0.rob.rob_writes 102252787 # The number of ROB writes -system.cpu0.timesIdled 884124 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161458427 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289647904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31189179 # Number of Instructions Simulated -system.cpu0.committedOps 39834539 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31189179 # Number of Instructions Simulated -system.cpu0.cpi 7.665590 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.665590 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.130453 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.130453 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 280633966 # number of integer regfile reads -system.cpu0.int_regfile_writes 45420954 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22760 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19830 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15480243 # number of misc regfile reads -system.cpu0.misc_regfile_writes 429707 # number of misc regfile writes -system.cpu0.icache.replacements 984233 # number of replacements -system.cpu0.icache.tagsinuse 511.604349 # Cycle average of tags in use -system.cpu0.icache.total_refs 11036411 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984745 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.207380 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123744681 # The number of ROB reads +system.cpu0.rob.rob_writes 102258102 # The number of ROB writes +system.cpu0.timesIdled 883709 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161449961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289675923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31185911 # Number of Instructions Simulated +system.cpu0.committedOps 39831648 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31185911 # Number of Instructions Simulated +system.cpu0.cpi 7.665825 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.665825 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130449 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130449 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 280645626 # number of integer regfile reads +system.cpu0.int_regfile_writes 45419186 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22697 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19806 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15480369 # number of misc regfile reads +system.cpu0.misc_regfile_writes 429671 # number of misc regfile writes +system.cpu0.icache.replacements 983987 # number of replacements +system.cpu0.icache.tagsinuse 511.561827 # Cycle average of tags in use +system.cpu0.icache.total_refs 11034736 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984499 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.208479 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6522889000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 356.507188 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 155.097161 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.696303 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.302924 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5565457 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5470954 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11036411 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5565457 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5470954 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11036411 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5565457 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5470954 # number of overall hits -system.cpu0.icache.overall_hits::total 11036411 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 540893 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 524443 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065336 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 540893 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 524443 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065336 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 540893 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 524443 # number of overall misses -system.cpu0.icache.overall_misses::total 1065336 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7322738992 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6974356493 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14297095485 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7322738992 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6974356493 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14297095485 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7322738992 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6974356493 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14297095485 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6106350 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5995397 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12101747 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6106350 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5995397 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12101747 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6106350 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5995397 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12101747 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088579 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087474 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088032 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088579 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087474 # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13298.597737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13420.268803 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4718 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 357.606132 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 153.955695 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.698449 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.300695 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5565566 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5469170 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11034736 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5565566 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5994167 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12099682 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6105515 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5994167 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12099682 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6105515 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5994167 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12099682 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088436 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087585 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088014 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088436 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087585 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088014 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088436 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087585 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088014 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13532.691039 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13278.624438 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.441305 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13407.441305 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13532.691039 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13278.624438 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13407.441305 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4578 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 353 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 340 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.365439 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.464706 # 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number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 41021 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 39404 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 80425 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 41021 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 39404 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 80425 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 498928 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 485593 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 984521 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 498928 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 485593 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 984521 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 498928 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 485593 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 984521 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5964947994 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 5687451995 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11652399989 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5964947994 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 5687451995 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11652399989 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5964947994 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 5687451995 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11652399989 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7526000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7526000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7526000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081374 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.081374 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081830 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.080911 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.081374 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.532475 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11952.269532 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11715.284336 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.532475 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.081368 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.081368 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.081718 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.081011 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.081368 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11835.603292 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.528641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11712.384641 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11835.603292 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 643981 # number of replacements +system.cpu0.dcache.replacements 643944 # number of replacements system.cpu0.dcache.tagsinuse 511.992715 # Cycle average of tags in use -system.cpu0.dcache.total_refs 21533340 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 644493 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.411286 # Average number of references to valid blocks. +system.cpu0.dcache.total_refs 21531615 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 644456 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.410528 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43205000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 320.784691 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 191.208024 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.626533 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.373453 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 318.816885 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 193.175830 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.622689 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.377297 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999986 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7106515 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 6670987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13777502 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3768669 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3492995 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 7261664 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125802 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117658 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 243460 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127804 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119816 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247620 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10875184 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 10163982 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 21039166 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10875184 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 10163982 # number of overall hits -system.cpu0.dcache.overall_hits::total 21039166 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 435450 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 315528 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 750978 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1386539 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1574618 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2961157 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6834 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 6765 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13599 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1821989 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1890146 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3712135 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1821989 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1890146 # number of overall misses -system.cpu0.dcache.overall_misses::total 3712135 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6465601500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 4868577500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11334179000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 52482898858 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 61975315789 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 114458214647 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92223500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 94082500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 186306000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 52000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 117000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 58948500358 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 66843893289 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 125792393647 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 58948500358 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 66843893289 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 125792393647 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7541965 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 6986515 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 14528480 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5155208 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 5067613 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10222821 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 132636 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 124423 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 257059 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 127809 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 119820 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247629 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12697173 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 12054128 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24751301 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12697173 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 12054128 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24751301 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.057737 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.045162 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.051690 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.268959 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.310722 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.289661 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.051524 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054371 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052902 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000033 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000036 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.143496 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.156805 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.149977 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.143496 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.156805 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.149977 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14848.091629 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15429.938072 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.557971 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37851.729276 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39358.952958 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38653.207056 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13494.805385 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13907.243163 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13699.977940 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_hits::cpu0.data 7106399 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 6669591 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13775990 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3768165 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3493394 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 7261559 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 125825 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 117550 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 243375 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127797 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 119821 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247618 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10874564 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 10162985 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 21037549 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10874564 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 10162985 # number of overall hits +system.cpu0.dcache.overall_hits::total 21037549 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 435409 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 315775 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 751184 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1387586 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1573694 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2961280 # 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number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6813593935 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13686568421 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91950216500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90410818500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182361035000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14891141407 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18622831131 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33513972538 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106847737316 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109028071995 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875809311 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028335 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024693 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026584 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106841357907 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109033649631 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215875007538 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028325 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024716 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026590 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023129 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025606 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046337 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048841 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000039 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000033 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for demand accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025590 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046091 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048965 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047481 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000047 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000050 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.025664 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026221 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025077 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026215 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025084 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.025664 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13567.853199 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13454.175531 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13517.075716 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33287.757611 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34627.697778 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33986.047507 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11664.009112 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12118.561790 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11890.002454 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13570.863488 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13459.536635 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13521.104300 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33324.999044 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34625.388955 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34002.412143 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11721.822346 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12099.457950 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.253258 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 13000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20630.078246 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22543.402175 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.561806 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 12000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20647.623655 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22537.837426 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21547.271707 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1310,154 +1322,154 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7038093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5643597 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 344397 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4629014 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3810883 # Number of BTB hits +system.cpu1.branchPred.lookups 7039242 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5645782 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 344121 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4649860 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3812908 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 82.326020 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 671158 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34749 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 82.000490 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671568 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 34742 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25308103 # DTB read hits -system.cpu1.dtb.read_misses 36468 # DTB read misses -system.cpu1.dtb.write_hits 5825949 # DTB write hits -system.cpu1.dtb.write_misses 9352 # DTB write misses +system.cpu1.dtb.read_hits 25307959 # DTB read hits +system.cpu1.dtb.read_misses 36376 # DTB read misses +system.cpu1.dtb.write_hits 5825723 # DTB write hits +system.cpu1.dtb.write_misses 9311 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5514 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1257 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5515 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1387 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 246 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 652 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25344571 # DTB read accesses -system.cpu1.dtb.write_accesses 5835301 # DTB write accesses +system.cpu1.dtb.perms_faults 651 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25344335 # DTB read accesses +system.cpu1.dtb.write_accesses 5835034 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31134052 # DTB hits -system.cpu1.dtb.misses 45820 # DTB misses -system.cpu1.dtb.accesses 31179872 # DTB accesses -system.cpu1.itb.inst_hits 5997509 # ITB inst hits -system.cpu1.itb.inst_misses 6989 # ITB inst misses +system.cpu1.dtb.hits 31133682 # DTB hits +system.cpu1.dtb.misses 45687 # DTB misses +system.cpu1.dtb.accesses 31179369 # DTB accesses +system.cpu1.itb.inst_hits 5996114 # ITB inst hits +system.cpu1.itb.inst_misses 6834 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 668 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 667 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2597 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2600 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1435 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6004498 # ITB inst accesses -system.cpu1.itb.hits 5997509 # DTB hits -system.cpu1.itb.misses 6989 # DTB misses -system.cpu1.itb.accesses 6004498 # DTB accesses -system.cpu1.numCycles 234155519 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6002948 # ITB inst accesses +system.cpu1.itb.hits 5996114 # DTB hits +system.cpu1.itb.misses 6834 # DTB misses +system.cpu1.itb.accesses 6002948 # DTB accesses +system.cpu1.numCycles 234172204 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15142136 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46597306 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 7038093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4482041 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10279188 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2613913 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 81086 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47501023 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 1008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2061 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 42896 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94668 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 141 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5995399 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 442650 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3270 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74933804 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.773237 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.138568 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15150430 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46599302 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7039242 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4484476 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10276938 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2612454 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 82512 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47518747 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2108 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 42921 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94711 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 94 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5994168 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 443200 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2937 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74957939 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.773072 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.138667 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64662280 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 620375 0.83% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 831799 1.11% 88.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1204715 1.61% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1045196 1.39% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 534648 0.71% 91.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1368616 1.83% 93.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 351624 0.47% 94.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4314551 5.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64688840 86.30% 86.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 619651 0.83% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 831575 1.11% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1205005 1.61% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1040099 1.39% 91.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 534718 0.71% 91.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368218 1.83% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 351871 0.47% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4317962 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74933804 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.030057 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.199002 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16155094 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47289878 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9321974 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 458622 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1706108 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 946431 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86032 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54867135 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 286067 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1706108 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17091509 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18549403 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25716073 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8765190 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3103459 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51703267 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7138 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 482463 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2122538 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 91 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53752733 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 237374868 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 237332026 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42842 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37999603 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15753129 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 403463 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 357307 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6254395 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9847442 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6700780 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 890369 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1126759 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47663057 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 942444 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60816475 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 81421 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10551432 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27971257 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 236318 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74933804 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.811603 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.521433 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74957939 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.030060 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198996 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16159118 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47313522 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9319419 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 458702 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1705045 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 945660 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85957 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54861176 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 287371 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1705045 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17094797 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18547389 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25741637 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8764339 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3102678 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51699813 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7117 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 482642 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2122595 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53761457 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 237355866 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 237312988 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42878 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 38005573 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15755883 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 403501 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 357316 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6247551 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9846699 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6699378 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 894839 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1124277 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47671789 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 942558 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60820762 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80974 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10554667 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27991193 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236389 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74957939 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.811399 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521506 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53188932 70.98% 70.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6663266 8.89% 79.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3530113 4.71% 84.58% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2889463 3.86% 88.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6218055 8.30% 96.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1440706 1.92% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 733706 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 209896 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59667 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53217841 71.00% 71.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6660852 8.89% 79.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3522155 4.70% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2891310 3.86% 88.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6221103 8.30% 96.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1440067 1.92% 98.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 734950 0.98% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210065 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59596 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74933804 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74957939 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 24001 0.55% 0.55% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24217 0.55% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 1 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.55% # attempts to use FU when none available @@ -1486,13 +1498,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.55% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.55% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.55% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4142238 94.88% 95.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 199692 4.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4143294 94.86% 95.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 200406 4.59% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 168133 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28440656 46.76% 47.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46730 0.08% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 168050 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28446121 46.77% 47.05% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46643 0.08% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.12% # Type of FU issued @@ -1505,129 +1517,129 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.12% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 904 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 906 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.12% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.12% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 26040768 42.82% 89.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6119264 10.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040786 42.82% 89.94% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6118237 10.06% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60816475 # Type of FU issued +system.cpu1.iq.FU_type_0::total 60820762 # Type of FU issued system.cpu1.iq.rate 0.259727 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4365932 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.071789 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 201049061 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 59165079 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41785793 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10680 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5951 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 65008639 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5635 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 303573 # Number of loads that had data forwarded from stores +system.cpu1.iq.fu_busy_cnt 4367918 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.071816 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 201083162 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 59177242 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41793523 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10683 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5961 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4808 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 65014989 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5641 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 303389 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2266828 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3041 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14605 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 855166 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2265840 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3135 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14672 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 854347 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16935844 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457097 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16937147 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 456872 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1706108 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 13962333 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 229984 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48711452 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 98533 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9847442 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6700780 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 669329 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 49837 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3707 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14605 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166001 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 133612 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 299613 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59448141 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25635797 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1368334 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1705045 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13964953 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 229910 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48720174 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 98231 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9846699 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6699378 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669323 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 49676 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3736 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14672 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165888 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 133425 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 299313 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59456626 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635805 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1364136 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105951 # number of nop insts executed -system.cpu1.iew.exec_refs 31702689 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5524822 # Number of branches executed -system.cpu1.iew.exec_stores 6066892 # Number of stores executed -system.cpu1.iew.exec_rate 0.253883 # Inst execution rate -system.cpu1.iew.wb_sent 58868959 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41790607 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22765083 # num instructions producing a value -system.cpu1.iew.wb_consumers 41748877 # num instructions consuming a value +system.cpu1.iew.exec_nop 105827 # number of nop insts executed +system.cpu1.iew.exec_refs 31702395 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5527346 # Number of branches executed +system.cpu1.iew.exec_stores 6066590 # Number of stores executed +system.cpu1.iew.exec_rate 0.253901 # Inst execution rate +system.cpu1.iew.wb_sent 58878116 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41798331 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22764679 # num instructions producing a value +system.cpu1.iew.wb_consumers 41753721 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.178474 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.545286 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.178494 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.545213 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10475750 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 706126 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 259614 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73227696 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.516730 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.497193 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10481198 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 706169 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 259373 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73252894 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.516596 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.497283 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59700930 81.53% 81.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6668134 9.11% 90.63% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1908648 2.61% 93.24% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1011673 1.38% 94.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 958934 1.31% 95.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 524760 0.72% 96.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 701730 0.96% 97.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 374533 0.51% 98.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1378354 1.88% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59734394 81.55% 81.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6658117 9.09% 90.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1908666 2.61% 93.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1009766 1.38% 94.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 959602 1.31% 95.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 525640 0.72% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 705032 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 372807 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1378870 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73227696 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 29191864 # Number of instructions committed -system.cpu1.commit.committedOps 37838928 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73252894 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29195437 # Number of instructions committed +system.cpu1.commit.committedOps 37842156 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13426228 # Number of memory references committed -system.cpu1.commit.loads 7580614 # Number of loads committed -system.cpu1.commit.membars 191280 # Number of memory barriers committed -system.cpu1.commit.branches 4758264 # Number of branches committed +system.cpu1.commit.refs 13425890 # Number of memory references committed +system.cpu1.commit.loads 7580859 # Number of loads committed +system.cpu1.commit.membars 191347 # Number of memory barriers committed +system.cpu1.commit.branches 4759387 # Number of branches committed system.cpu1.commit.fp_insts 4779 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33593707 # Number of committed integer instructions. -system.cpu1.commit.function_calls 477362 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1378354 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 33596023 # Number of committed integer instructions. +system.cpu1.commit.function_calls 477418 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1378870 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 119292034 # The number of ROB reads -system.cpu1.rob.rob_writes 98387822 # The number of ROB writes -system.cpu1.timesIdled 873010 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159221715 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285865988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 29120710 # Number of Instructions Simulated -system.cpu1.committedOps 37767774 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 29120710 # Number of Instructions Simulated -system.cpu1.cpi 8.040859 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.040859 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.124365 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.124365 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 269346342 # number of integer regfile reads -system.cpu1.int_regfile_writes 42878504 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22102 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19714 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14810651 # number of misc regfile reads -system.cpu1.misc_regfile_writes 402789 # number of misc regfile writes +system.cpu1.rob.rob_reads 119325211 # The number of ROB reads +system.cpu1.rob.rob_writes 98404070 # The number of ROB writes +system.cpu1.timesIdled 873125 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159214265 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285839594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29124328 # Number of Instructions Simulated +system.cpu1.committedOps 37771047 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29124328 # Number of Instructions Simulated +system.cpu1.cpi 8.040433 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.040433 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124371 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124371 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 269378788 # number of integer regfile reads +system.cpu1.int_regfile_writes 42887039 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22080 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19702 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14812812 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402828 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1642,17 +1654,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192717579972 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192717579972 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192717579972 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192668399444 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192668399444 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192668399444 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83049 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |